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https://github.com/espressif/esp-idf.git
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280 lines
12 KiB
C
280 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "soc/lldesc.h"
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#include "soc/soc_caps.h"
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#include "hal/i2s_hal.h"
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#include "driver/i2s_types.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp_clock_output.h"
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#endif
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#if SOC_GDMA_SUPPORTED
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#include "esp_private/gdma.h"
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#endif
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_gpio_reserve.h"
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#include "esp_pm.h"
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#include "esp_err.h"
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// If ISR handler is allowed to run whilst cache is disabled,
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// Make sure all the code and related variables used by the handler are in the SRAM
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#if CONFIG_I2S_ISR_IRAM_SAFE
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED)
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#define I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED)
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#define I2S_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
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#endif //CONFIG_I2S_ISR_IRAM_SAFE
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#define I2S_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT)
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#if SOC_PERIPH_CLK_CTRL_SHARED
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#define I2S_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define I2S_CLOCK_SRC_ATOMIC()
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#endif
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#if !SOC_RCC_IS_INDEPENDENT
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#define I2S_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define I2S_RCC_ATOMIC()
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#endif
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#define I2S_NULL_POINTER_CHECK(tag, p) ESP_RETURN_ON_FALSE((p), ESP_ERR_INVALID_ARG, tag, "input parameter '"#p"' is NULL")
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/**
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* @brief i2s channel state for checking if the operation in under right driver state
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*/
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typedef enum {
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I2S_CHAN_STATE_REGISTER, /*!< i2s channel is registered (not initialized) */
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I2S_CHAN_STATE_READY, /*!< i2s channel is disabled (initialized) */
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I2S_CHAN_STATE_RUNNING, /*!< i2s channel is idling (initialized and enabled) */
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} i2s_state_t;
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/**
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* @brief Group of I2S callbacks
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* @note The callbacks are all running under ISR environment
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* @note When CONFIG_I2S_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
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* The variables used in the function should be in the SRAM as well.
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* @note Declare the internal type to remove the dependency of `i2s_common.h`
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*/
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typedef struct {
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i2s_isr_callback_t on_recv; /**< Callback of data received event, only for rx channel
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* The event data includes DMA buffer address and size that just finished receiving data
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*/
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i2s_isr_callback_t on_recv_q_ovf; /**< Callback of receiving queue overflowed event, only for rx channel
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* The event data includes buffer size that has been overwritten
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*/
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i2s_isr_callback_t on_sent; /**< Callback of data sent event, only for tx channel
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* The event data includes DMA buffer address and size that just finished sending data
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*/
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i2s_isr_callback_t on_send_q_ovf; /**< Callback of sending queue overflowed event, only for tx channel
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* The event data includes buffer size that has been overwritten
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*/
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} i2s_event_callbacks_internal_t;
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/**
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* @brief i2s channel level configurations
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* @note It performs as channel handle
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*/
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typedef struct {
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#if SOC_GDMA_SUPPORTED
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gdma_channel_handle_t dma_chan; /*!< gdma channel handle */
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#else
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intr_handle_t dma_chan; /*!< interrupt channel handle */
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#endif
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uint32_t desc_num; /*!< I2S DMA buffer number, it is also the number of DMA descriptor */
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uint32_t frame_num; /*!< I2S frame number in one DMA buffer. One frame means one-time sample data in all slots */
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uint32_t buf_size; /*!< dma buffer size */
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bool auto_clear_after_cb; /*!< Set to auto clear DMA TX descriptor after callback, i2s will always send zero automatically if no data to send */
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bool auto_clear_before_cb; /*!< Set to auto clear DMA TX descriptor before callback, i2s will always send zero automatically if no data to send */
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uint32_t rw_pos; /*!< reading/writing pointer position */
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void *curr_ptr; /*!< Pointer to current dma buffer */
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void *curr_desc; /*!< Pointer to current dma descriptor used for pre-load */
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lldesc_t **desc; /*!< dma descriptor array */
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uint8_t **bufs; /*!< dma buffer array */
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} i2s_dma_t;
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/**
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* @brief i2s controller level configurations
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* @note Both i2s rx and tx channel are under its control
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*/
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typedef struct {
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i2s_port_t id; /*!< i2s port id */
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i2s_hal_context_t hal; /*!< hal context */
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uint32_t chan_occupancy; /*!< channel occupancy (rx/tx) */
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bool full_duplex; /*!< is full_duplex */
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i2s_chan_handle_t tx_chan; /*!< tx channel handler */
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i2s_chan_handle_t rx_chan; /*!< rx channel handler */
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int mclk; /*!< MCK out pin, shared by tx/rx*/
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#if CONFIG_IDF_TARGET_ESP32
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esp_clock_output_mapping_handle_t mclk_out_hdl; /*!< The handle of MCLK output signal */
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#endif
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} i2s_controller_t;
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struct i2s_channel_obj_t {
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/* Channel basic information */
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i2s_controller_t *controller; /*!< Parent pointer to controller object */
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i2s_comm_mode_t mode; /*!< i2s channel communication mode */
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i2s_role_t role; /*!< i2s role */
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i2s_dir_t dir; /*!< i2s channel direction */
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i2s_dma_t dma; /*!< i2s dma object */
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i2s_state_t state; /*!< i2s driver state. Ensuring the driver working in a correct sequence */
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/* Stored configurations */
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int intr_prio_flags;/*!< i2s interrupt priority flags */
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void *mode_info; /*!< Slot, clock and gpio information of each mode */
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#if SOC_I2S_SUPPORTS_APLL
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bool apll_en; /*!< Flag of whether APLL enabled */
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#endif
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uint32_t active_slot; /*!< Active slot number */
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uint32_t total_slot; /*!< Total slot number */
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/* Locks and queues */
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SemaphoreHandle_t mutex; /*!< Mutex semaphore for the channel operations */
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SemaphoreHandle_t binary; /*!< Binary semaphore for writing / reading / enabling / disabling */
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#if CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock; /*!< Power management lock, to avoid apb clock frequency changes while i2s is working */
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#endif
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QueueHandle_t msg_queue; /*!< Message queue handler, used for transporting data between interrupt and read/write task */
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uint64_t reserve_gpio_mask; /*!< The gpio mask that has been reserved by I2S */
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i2s_event_callbacks_internal_t callbacks; /*!< Callback functions */
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void *user_data; /*!< User data for callback functions */
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void (*start)(i2s_chan_handle_t); /*!< start tx/rx channel */
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void (*stop)(i2s_chan_handle_t); /*!< stop tx/rx channel */
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};
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/**
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* @brief i2s platform level configurations
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* @note All i2s controllers' resources are involved
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*/
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typedef struct {
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portMUX_TYPE spinlock; /*!< Platform level lock */
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i2s_controller_t *controller[SOC_I2S_NUM]; /*!< Controller object */
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const char *comp_name[SOC_I2S_NUM]; /*!< The component name that occupied i2s controller */
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} i2s_platform_t;
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extern i2s_platform_t g_i2s; /*!< Global i2s instance for driver internal use */
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/**
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* @brief Initialize I2S DMA interrupt
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*
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* @param handle I2S channel handle
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* @param intr_flag I2S interrupt flags, `ESP_INTR_FLAG_XXX` defined in `esp_intr_alloc.h`
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* @return
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* - ESP_OK Initialize interrupt success
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* - ESP_ERR_INVALID_ARG Wrong port id or NULL pointer
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*/
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esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag);
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/**
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* @brief Free I2S DMA descriptor and DMA buffer
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*
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* @param handle I2S channel handle
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* @return
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* - ESP_OK Free success
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* - ESP_ERR_INVALID_ARG NULL pointer
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*/
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esp_err_t i2s_free_dma_desc(i2s_chan_handle_t handle);
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/**
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* @brief Allocate memory for I2S DMA descriptor and DMA buffer
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*
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* @param handle I2S channel handle
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* @param num Number of DMA descriptors
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* @param bufsize The DMA buffer size
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*
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* @return
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* - ESP_OK Allocate memory success
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* - ESP_ERR_INVALID_ARG NULL pointer or bufsize is too big
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* - ESP_ERR_NO_MEM No memory for DMA descriptor and DMA buffer
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*/
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esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bufsize);
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/**
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* @brief Get DMA buffer size
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*
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* @param handle I2S channel handle
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* @param data_bit_width Data bit width in one slot
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* @param dma_frame_num Frame number in one DMA buffer
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*
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* @return
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* - DMA buffer size
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*/
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uint32_t i2s_get_buf_size(i2s_chan_handle_t handle, uint32_t data_bit_width, uint32_t dma_frame_num);
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/**
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* @brief Get the frequency of the source clock
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*
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* @param clk_src clock source
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* @param mclk_freq_hz Expected mclk frequency in Hz
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* @return
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* - Actual source clock frequency
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*/
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uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, uint32_t mclk_freq_hz);
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/**
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* @brief Check gpio validity and attach to corresponding signal
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*
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* @param handle I2S channel handle
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* @param gpio GPIO number
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* @param signal_idx Signal index
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* @param is_input Is input gpio
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* @param is_invert Is invert gpio
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*/
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void i2s_gpio_check_and_set(i2s_chan_handle_t handle, int gpio, uint32_t signal_idx, bool is_input, bool is_invert);
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/**
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* @brief Check gpio validity and output mclk signal
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*
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* @param handle I2S channel handle
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* @param id I2S port id
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* @param gpio_num GPIO number
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* @param clk_src The clock source of this I2S port
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* @param is_invert Is invert the GPIO
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* @return
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* - ESP_OK Set mclk output gpio success
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* - ESP_ERR_INVALID_ARG Invalid GPIO number
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*/
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esp_err_t i2s_check_set_mclk(i2s_chan_handle_t handle, i2s_port_t id, int gpio_num, i2s_clock_src_t clk_src, bool is_invert);
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/**
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* @brief Attach data out signal and data in signal to a same gpio
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*
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* @param handle I2S channel handle
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* @param gpio GPIO number
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* @param out_sig_idx Data out signal index
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* @param in_sig_idx Data in signal index
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*/
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void i2s_gpio_loopback_set(i2s_chan_handle_t handle, int gpio, uint32_t out_sig_idx, uint32_t in_sig_idx);
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/**
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* @brief Reserve the GPIO that configured as I2S output signal
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*
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* @param handle I2S channel handle
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* @param gpio_num The output gpio number to be reserved
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*/
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void i2s_output_gpio_reserve(i2s_chan_handle_t handle, int gpio_num);
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/**
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* @brief Revoke the GPIO that configured as I2S output signal
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*
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* @param handle I2S channel handle
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* @param gpio_mask The output gpio mask to be revoked
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*/
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void i2s_output_gpio_revoke(i2s_chan_handle_t handle, uint64_t gpio_mask);
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#ifdef __cplusplus
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}
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#endif
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