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102 lines
4.2 KiB
C
102 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include "sdkconfig.h"
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#include "hal/twai_hal.h"
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#include "hal/efuse_hal.h"
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#include "soc/soc_caps.h"
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//Default values written to various registers on initialization
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#define TWAI_HAL_INIT_TEC 0
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#define TWAI_HAL_INIT_REC 0
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#define TWAI_HAL_INIT_EWL 96
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/* ---------------------------- Init and Config ----------------------------- */
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bool twai_hal_init(twai_hal_context_t *hal_ctx, const twai_hal_config_t *config)
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{
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//Initialize HAL context
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hal_ctx->dev = TWAI_LL_GET_HW(config->controller_id);
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hal_ctx->state_flags = 0;
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hal_ctx->clock_source_hz = config->clock_source_hz;
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//Initialize TWAI controller, and set default values to registers
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twai_ll_enter_reset_mode(hal_ctx->dev);
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if (!twai_ll_is_in_reset_mode(hal_ctx->dev)) { //Must enter reset mode to write to config registers
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return false;
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}
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#if SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
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twai_ll_enable_extended_reg_layout(hal_ctx->dev); //Changes the address layout of the registers
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#endif
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twai_ll_set_mode(hal_ctx->dev, TWAI_MODE_LISTEN_ONLY); //Freeze REC by changing to LOM mode
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//Both TEC and REC should start at 0
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twai_ll_set_tec(hal_ctx->dev, TWAI_HAL_INIT_TEC);
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twai_ll_set_rec(hal_ctx->dev, TWAI_HAL_INIT_REC);
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twai_ll_set_err_warn_lim(hal_ctx->dev, TWAI_HAL_INIT_EWL); //Set default value of for EWL
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return true;
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}
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void twai_hal_deinit(twai_hal_context_t *hal_ctx)
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{
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//Clear any pending registers
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(void) twai_ll_get_and_clear_intrs(hal_ctx->dev);
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twai_ll_set_enabled_intrs(hal_ctx->dev, 0);
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twai_ll_clear_arb_lost_cap(hal_ctx->dev);
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twai_ll_clear_err_code_cap(hal_ctx->dev);
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hal_ctx->dev = NULL;
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}
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void twai_hal_configure(twai_hal_context_t *hal_ctx, const twai_timing_config_t *t_config, const twai_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider)
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{
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uint32_t brp = t_config->brp;
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// both quanta_resolution_hz and brp can affect the baud rate
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// but a non-zero quanta_resolution_hz takes higher priority
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if (t_config->quanta_resolution_hz) {
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brp = hal_ctx->clock_source_hz / t_config->quanta_resolution_hz;
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}
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//Configure bus timing, acceptance filter, CLKOUT, and interrupts
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twai_ll_set_bus_timing(hal_ctx->dev, brp, t_config->sjw, t_config->tseg_1, t_config->tseg_2, t_config->triple_sampling);
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twai_ll_set_acc_filter(hal_ctx->dev, f_config->acceptance_code, f_config->acceptance_mask, f_config->single_filter);
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twai_ll_set_clkout(hal_ctx->dev, clkout_divider);
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twai_ll_set_enabled_intrs(hal_ctx->dev, intr_mask);
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(void) twai_ll_get_and_clear_intrs(hal_ctx->dev); //Clear any latched interrupts
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}
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/* -------------------------------- Actions --------------------------------- */
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void twai_hal_start(twai_hal_context_t *hal_ctx, twai_mode_t mode)
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{
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twai_ll_set_mode(hal_ctx->dev, mode); //Set operating mode
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//Clear the TEC and REC
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twai_ll_set_tec(hal_ctx->dev, 0);
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#ifdef CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM
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/*
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Errata workaround: Prevent transmission of dominant error frame while in listen only mode by setting REC to 128
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before exiting reset mode. This forces the controller to be error passive (thus only transmits recessive bits).
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The TEC/REC remain frozen in listen only mode thus ensuring we remain error passive.
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*/
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if (mode == TWAI_MODE_LISTEN_ONLY) {
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twai_ll_set_rec(hal_ctx->dev, 128);
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} else
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#endif
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{
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twai_ll_set_rec(hal_ctx->dev, 0);
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}
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(void) twai_ll_get_and_clear_intrs(hal_ctx->dev); //Clear any latched interrupts
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TWAI_HAL_SET_BITS(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_RUNNING);
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twai_ll_exit_reset_mode(hal_ctx->dev);
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}
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void twai_hal_stop(twai_hal_context_t *hal_ctx)
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{
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twai_ll_enter_reset_mode(hal_ctx->dev);
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(void) twai_ll_get_and_clear_intrs(hal_ctx->dev);
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twai_ll_set_mode(hal_ctx->dev, TWAI_MODE_LISTEN_ONLY); //Freeze REC by changing to LOM mode
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//Any TX is immediately halted on entering reset mode
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TWAI_HAL_CLEAR_BITS(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_TX_BUFF_OCCUPIED | TWAI_HAL_STATE_FLAG_RUNNING);
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}
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