mirror of
				https://github.com/espressif/esp-idf.git
				synced 2025-10-31 04:59:55 +00:00 
			
		
		
		
	 793382107f
			
		
	
	793382107f
	
	
	
		
			
			In esp32c2 and esp32c61 memory_layout.c files, the config used to allow MALLOC_CAP_EXEC was CONFIG_ESP_SYSTEM_MEMPROT_FEATURE when CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT should be used. Closes https://github.com/espressif/esp-idf/issues/14836
		
			
				
	
	
		
			92 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			92 lines
		
	
	
		
			3.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
 | |
|  * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
 | |
|  *
 | |
|  * SPDX-License-Identifier: Apache-2.0
 | |
|  */
 | |
| 
 | |
| #include <stdint.h>
 | |
| #include <stdlib.h>
 | |
| #include "esp_attr.h"
 | |
| #include "sdkconfig.h"
 | |
| #include "soc/soc.h"
 | |
| #include "heap_memory_layout.h"
 | |
| #include "esp_heap_caps.h"
 | |
| 
 | |
| /* Memory layout for ESP32C61 SoC
 | |
|  * Note that the external memory is not represented in this file since
 | |
|  * it is handled by the esp_psram component
 | |
|  */
 | |
| 
 | |
| /**
 | |
|  * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
 | |
|  * Each type of memory map consists of one or more regions in the address space.
 | |
|  * Each type contains an array of prioritized capabilities.
 | |
|  * Types with later entries are only taken if earlier ones can't fulfill the memory request.
 | |
|  *
 | |
|  * - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
 | |
|  * - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
 | |
|  * - Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
 | |
|  * - Most other malloc caps only fit in one region anyway.
 | |
|  *
 | |
|  */
 | |
| 
 | |
| /* Index of memory in `soc_memory_types[]` */
 | |
| enum {
 | |
|     SOC_MEMORY_TYPE_RAM,
 | |
| };
 | |
| 
 | |
| /* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
 | |
| #ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT
 | |
| #define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
 | |
| #else
 | |
| #define ESP32C61_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_EXEC)
 | |
| #endif
 | |
| 
 | |
| /**
 | |
|  * Defined the attributes and allocation priority of each memory on the chip,
 | |
|  * The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
 | |
|  * if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
 | |
|  * in turn to continue matching.
 | |
|  */
 | |
| const soc_memory_type_desc_t soc_memory_types[] = {
 | |
|     /*                           Mem Type Name   High Priority Matching                      Medium Priority Matching    Low Priority Matching */
 | |
|     [SOC_MEMORY_TYPE_RAM]    = { "RAM",          { ESP32C61_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0,                         0 }},
 | |
| };
 | |
| 
 | |
| const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
 | |
| 
 | |
| /**
 | |
|  * @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
 | |
|  *
 | |
|  * @note Because of requirements in the coalescing code which merges adjacent regions,
 | |
|  *       this list should always be sorted from low to high by start address.
 | |
|  *
 | |
|  */
 | |
| 
 | |
| /**
 | |
|  * Register the shared buffer area of the last memory block into the heap during heap initialization
 | |
|  */
 | |
| #define APP_USABLE_DIRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 | |
| 
 | |
| const soc_memory_region_t soc_memory_regions[] = {
 | |
|     { SOC_DIRAM_DRAM_LOW,   (APP_USABLE_DIRAM_END - SOC_DIRAM_DRAM_LOW),  SOC_MEMORY_TYPE_RAM,     SOC_DIRAM_IRAM_LOW,     false}, //D/IRAM, can be used as trace memory
 | |
|     { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM,     APP_USABLE_DIRAM_END,    true}, //D/IRAM, can be used as trace memory (ROM reserved area)
 | |
| };
 | |
| 
 | |
| const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
 | |
| 
 | |
| 
 | |
| extern int _data_start, _heap_start, _iram_start, _iram_end;
 | |
| 
 | |
| /**
 | |
|  * Reserved memory regions.
 | |
|  * These are removed from the soc_memory_regions array when heaps are created.
 | |
|  *
 | |
|  */
 | |
| 
 | |
| // Static data region. DRAM used by data+bss and possibly rodata
 | |
| SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data);
 | |
| 
 | |
| // Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
 | |
| SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
 |