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335d39b869
- Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration - Remove FPGA build
35 lines
980 B
C
35 lines
980 B
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gpio_periph.h"
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const uint32_t GPIO_HOLD_MASK[] = {
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BIT(0), //GPIO0 // LP_AON_GPIO_HOLD0_REG
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BIT(1), //GPIO1
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BIT(2), //GPIO2
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BIT(3), //GPIO3
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BIT(4), //GPIO4
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BIT(5), //GPIO5
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BIT(6), //GPIO6
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BIT(7), //GPIO7
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BIT(8), //GPIO8
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BIT(9), //GPIO9
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BIT(10), //GPIO10
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BIT(11), //GPIO11
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BIT(12), //GPIO12
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BIT(13), //GPIO13
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BIT(14), //GPIO14
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BIT(15), //GPIO15
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BIT(16), //GPIO16
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BIT(17), //GPIO17
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BIT(18), //GPIO18
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BIT(19), //GPIO19
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BIT(20), //GPIO20
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BIT(21), //GPIO21
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};
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_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
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