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https://github.com/espressif/esp-idf.git
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227 lines
8.4 KiB
C
227 lines
8.4 KiB
C
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The HAL layer for SPI Slave HD
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#include <string.h>
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "sdkconfig.h"
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#include "soc/spi_periph.h"
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#include "soc/lldesc.h"
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#include "hal/spi_slave_hd_hal.h"
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#include "soc/soc_caps.h"
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//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
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#if SOC_GDMA_SUPPORTED
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#include "soc/gdma_struct.h"
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#include "hal/gdma_ll.h"
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#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL)
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#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);
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#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable);
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#define spi_dma_ll_rx_start(dev, addr) do {\
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gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#define spi_dma_ll_tx_start(dev, addr) do {\
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gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#endif
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static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal)
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{
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spi_dma_ll_rx_enable_burst_data(hal->dma_in, 1);
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spi_dma_ll_tx_enable_burst_data(hal->dma_out, 1);
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spi_dma_ll_rx_enable_burst_desc(hal->dma_in, 1);
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spi_dma_ll_tx_enable_burst_desc(hal->dma_out, 1);
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}
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void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config)
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{
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memset(hal, 0, sizeof(spi_slave_hd_hal_context_t));
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spi_dev_t* hw = SPI_LL_GET_HW(hal_config->host_id);
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hal->dev = hw;
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hal->dma_in = hal_config->dma_in;
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hal->dma_out = hal_config->dma_out;
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//Configure slave
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s_spi_slave_hd_hal_dma_init_config(hal);
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spi_ll_slave_hd_init(hw);
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spi_ll_set_addr_bitlen(hw, hal_config->address_bits);
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spi_ll_set_command_bitlen(hw, hal_config->command_bits);
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spi_ll_set_dummy(hw, hal_config->dummy_bits);
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spi_ll_set_rx_lsbfirst(hw, hal_config->rx_lsbfirst);
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spi_ll_set_tx_lsbfirst(hw, hal_config->tx_lsbfirst);
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spi_ll_slave_set_mode(hw, hal_config->mode, (hal_config->dma_chan != 0));
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spi_ll_disable_intr(hw, UINT32_MAX);
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spi_ll_clear_intr(hw, UINT32_MAX);
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spi_ll_set_intr(hw, SPI_LL_INTR_WR_DONE | SPI_LL_INTR_CMD8);
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bool workaround_required = false;
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if (!spi_ll_get_intr(hw, SPI_LL_INTR_WR_DONE)) {
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hal->intr_not_triggered |= SPI_EV_RECV;
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workaround_required = true;
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}
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if (!spi_ll_get_intr(hw, SPI_LL_INTR_CMD8)) {
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hal->intr_not_triggered |= SPI_EV_SEND;
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workaround_required = true;
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}
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if (workaround_required) {
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//Workaround if the previous interrupts are not writable
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spi_ll_set_intr(hw, SPI_LL_INTR_TRANS_DONE);
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}
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spi_ll_slave_hd_set_len_cond(hw, SPI_LL_TRANS_LEN_COND_WRBUF |
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SPI_LL_TRANS_LEN_COND_WRDMA |
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SPI_LL_TRANS_LEN_COND_RDBUF |
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SPI_LL_TRANS_LEN_COND_RDDMA);
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spi_ll_slave_set_seg_mode(hal->dev, true);
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}
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void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len)
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{
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lldesc_setup_link(hal->dmadesc_rx, out_buf, len, true);
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spi_ll_dma_fifo_reset(hal->dev);
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spi_dma_ll_rx_reset(hal->dma_in);
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spi_ll_slave_reset(hal->dev);
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spi_ll_infifo_full_clr(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_WR_DONE);
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spi_ll_slave_set_rx_bitlen(hal->dev, len * 8);
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spi_ll_dma_rx_enable(hal->dev, 1);
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spi_dma_ll_rx_start(hal->dma_in, &hal->dmadesc_rx[0]);
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}
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void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len)
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{
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lldesc_setup_link(hal->dmadesc_tx, data, len, false);
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spi_ll_dma_fifo_reset(hal->dev);
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spi_dma_ll_tx_reset(hal->dma_out);
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spi_ll_slave_reset(hal->dev);
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spi_ll_outfifo_empty_clr(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8);
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spi_ll_dma_tx_enable(hal->dev, 1);
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spi_dma_ll_tx_start(hal->dma_out, &hal->dmadesc_tx[0]);
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}
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static spi_ll_intr_t get_event_intr(spi_event_t ev)
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{
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spi_ll_intr_t intr = 0;
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if (ev & SPI_EV_BUF_TX) intr |= SPI_LL_INTR_RDBUF;
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if (ev & SPI_EV_BUF_RX) intr |= SPI_LL_INTR_WRBUF;
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if (ev & SPI_EV_SEND) intr |= SPI_LL_INTR_CMD8;
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if (ev & SPI_EV_RECV) intr |= SPI_LL_INTR_WR_DONE;
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if (ev & SPI_EV_CMD9) intr |= SPI_LL_INTR_CMD9;
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if (ev & SPI_EV_CMDA) intr |= SPI_LL_INTR_CMDA;
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if (ev & SPI_EV_TRANS) intr |= SPI_LL_INTR_TRANS_DONE;
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return intr;
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}
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bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(ev);
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if (spi_ll_get_intr(hal->dev, intr)) {
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spi_ll_clear_intr(hal->dev, intr);
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return true;
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}
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return false;
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}
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bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
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{
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//The trans_done interrupt is used for the workaround when some interrupt is not writable
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spi_ll_intr_t intr = get_event_intr(ev);
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// Workaround for these interrupts not writable
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uint32_t missing_intr = hal->intr_not_triggered & ev;
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if (missing_intr) {
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if ((missing_intr & SPI_EV_RECV) && spi_ll_get_intr(hal->dev, SPI_LL_INTR_WR_DONE)) {
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hal->intr_not_triggered &= ~SPI_EV_RECV;
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}
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if ((missing_intr & SPI_EV_SEND) && spi_ll_get_intr(hal->dev, SPI_LL_INTR_CMD8)) {
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hal->intr_not_triggered &= ~SPI_EV_SEND;
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}
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if (spi_ll_get_intr(hal->dev, SPI_LL_INTR_TRANS_DONE)) {
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spi_ll_disable_intr(hal->dev, SPI_LL_INTR_TRANS_DONE);
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}
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}
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if (spi_ll_get_intr(hal->dev, intr)) {
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spi_ll_disable_intr(hal->dev, intr);
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return true;
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}
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return false;
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}
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void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(ev);
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spi_ll_enable_intr(hal->dev, intr);
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}
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void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(ev);
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// Workaround for these interrupts not writable
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if (hal->intr_not_triggered & ev & (SPI_EV_RECV | SPI_EV_SEND)) {
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intr |= SPI_LL_INTR_TRANS_DONE;
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}
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spi_ll_enable_intr(hal->dev, intr);
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}
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void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len)
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{
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spi_ll_read_buffer_byte(hal->dev, addr, out_data, len);
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}
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void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *data, size_t len)
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{
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spi_ll_write_buffer_byte(hal->dev, addr, data, len);
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}
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int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal)
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{
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return spi_ll_slave_hd_get_last_addr(hal->dev);
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}
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int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal)
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{
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//this is by -byte
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return spi_ll_slave_get_rx_byte_len(hal->dev);
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}
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int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal)
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{
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lldesc_t* desc = &hal->dmadesc_rx[0];
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return lldesc_get_received_len(desc, NULL);
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}
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