Files
esp-idf/examples/system
Sudeep Mohanty bc74cf808d feat(ulp-riscv): Added Kconfig option to enable ULP RISC-V interrupts
This commit adds a Kconfig option, CONFIG_ULP_RISCV_INTERRUPT_ENABLE, to
enable interrupts on the ULP RISC-V core on the esp32s2 and esp32s3.
2024-02-21 11:45:06 +01:00
..

System Examples

Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates), deep sleep logging, and event loops.

See the README.md file in the upper level examples directory for more information about examples.