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f709faea7c
RTC_CNTL_COCPU_SHUT_RESET_EN register was being reset during ULP RISC-V initialization which does not let the ULP RISC-V coprocessor to reset after it goes to halt. For proper operation of the coprocessor, it must be reset after each cycle and hence this commit keeps RTC_CNTL_COCPU_SHUT_RESET_EN set.
61 lines
1.5 KiB
C
61 lines
1.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "ulp_riscv_utils.h"
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#include "ulp_riscv_register_ops.h"
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#include "soc/soc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/soc_ulp.h"
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void ulp_riscv_rescue_from_monitor(void)
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{
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/* Rescue RISCV from monitor state. */
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
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}
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void ulp_riscv_wakeup_main_processor(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SW_CPU_INT);
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}
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void ulp_riscv_halt(void)
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{
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/* Setting the delay time after RISCV recv `DONE` signal, Ensure that action `RESET` can be executed in time. */
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REG_SET_FIELD(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_2_CLK_DIS, 0x3F);
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/* suspends the ulp operation*/
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
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/* Resets the processor */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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while(1);
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}
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void ulp_riscv_delay_cycles(uint32_t cycles)
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{
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uint32_t start = ULP_RISCV_GET_CCOUNT();
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while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) {
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/* Wait */
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}
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}
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void ulp_riscv_timer_stop(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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}
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void ulp_riscv_timer_resume(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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}
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void ulp_riscv_gpio_wakeup_clear(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR);
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}
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