mirror of
https://github.com/espressif/esp-idf.git
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279 lines
11 KiB
C
279 lines
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_types.h>
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#include <sys/lock.h>
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#include <stdatomic.h>
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#include "freertos/FreeRTOS.h"
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#include "sdkconfig.h"
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#include "esp_log.h"
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#include "esp_check.h"
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#include "esp_heap_caps.h"
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#include "driver/isp_hist.h"
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#include "esp_private/isp_private.h"
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typedef struct isp_hist_controller_t {
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_Atomic isp_fsm_t fsm;
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portMUX_TYPE spinlock;
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intr_handle_t intr_handle;
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isp_proc_handle_t isp_proc;
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QueueHandle_t evt_que;
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esp_isp_hist_cbs_t cbs;
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void *user_data;
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} isp_hist_controller_t;
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static const char *TAG = "ISP_hist";
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/*---------------------------------------------
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hist
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----------------------------------------------*/
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static esp_err_t s_isp_claim_hist_controller(isp_proc_handle_t isp_proc, isp_hist_ctlr_t hist_ctlr)
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{
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assert(isp_proc && hist_ctlr);
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bool found = false;
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portENTER_CRITICAL(&isp_proc->spinlock);
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if (!isp_proc->hist_ctlr) {
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isp_proc->hist_ctlr = hist_ctlr;
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found = true;
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}
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portEXIT_CRITICAL(&isp_proc->spinlock);
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if (!found) {
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return ESP_ERR_NOT_FOUND;
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}
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return ESP_OK;
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}
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static void s_isp_declaim_hist_controller(isp_hist_ctlr_t hist_ctlr)
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{
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if (hist_ctlr && hist_ctlr->isp_proc) {
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portENTER_CRITICAL(&hist_ctlr->isp_proc->spinlock);
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hist_ctlr->isp_proc->hist_ctlr = NULL;
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portEXIT_CRITICAL(&hist_ctlr->isp_proc->spinlock);
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}
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}
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static void s_isp_hist_free_controller(isp_hist_ctlr_t hist_ctlr)
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{
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if (hist_ctlr) {
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if (hist_ctlr->intr_handle) {
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esp_intr_free(hist_ctlr->intr_handle);
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}
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if (hist_ctlr->evt_que) {
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vQueueDeleteWithCaps(hist_ctlr->evt_que);
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}
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free(hist_ctlr);
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}
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}
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static esp_err_t s_esp_isp_hist_config_hardware(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg)
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{
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for (int i = 0; i < SOC_ISP_HIST_INTERVAL_NUMS; i++) {
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ESP_RETURN_ON_FALSE((hist_cfg->segment_threshold[i] > 0 && hist_cfg->segment_threshold[i] < 256), ESP_ERR_INVALID_ARG, TAG, "invalid segment threshold");
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}
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ESP_RETURN_ON_FALSE(hist_cfg->rgb_coefficient.coeff_r.integer == 0 && hist_cfg->rgb_coefficient.coeff_g.integer == 0 && hist_cfg->rgb_coefficient.coeff_b.integer == 0, \
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ESP_ERR_INVALID_ARG, TAG, "The rgb_coefficient's integer value is bigger than 0");
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int weight_sum = 0;
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for (int i = 0; i < SOC_ISP_HIST_BLOCK_X_NUMS * SOC_ISP_HIST_BLOCK_Y_NUMS; i++) {
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ESP_RETURN_ON_FALSE(hist_cfg->window_weight[i].integer == 0, ESP_ERR_INVALID_ARG, TAG, "The subwindow weight's integer value is bigger than -");
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weight_sum = weight_sum + hist_cfg->window_weight[i].decimal;
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}
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ESP_RETURN_ON_FALSE(weight_sum == 256, ESP_ERR_INVALID_ARG, TAG, "The sum of all subwindow weight's decimal value is not 256");
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isp_ll_hist_set_mode(isp_proc->hal.hw, hist_cfg->hist_mode);
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isp_hal_hist_window_config(&isp_proc->hal, &hist_cfg->window);
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isp_ll_hist_set_subwindow_weight(isp_proc->hal.hw, hist_cfg->window_weight);
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isp_ll_hist_set_segment_threshold(isp_proc->hal.hw, hist_cfg->segment_threshold);
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if (hist_cfg->hist_mode == ISP_HIST_SAMPLING_RGB) {
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isp_ll_hist_set_rgb_coefficient(isp_proc->hal.hw, &hist_cfg->rgb_coefficient);
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}
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return ESP_OK;
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}
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esp_err_t esp_isp_new_hist_controller(isp_proc_handle_t isp_proc, const esp_isp_hist_config_t *hist_cfg, isp_hist_ctlr_t *ret_hdl)
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{
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esp_err_t ret = ESP_FAIL;
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ESP_RETURN_ON_FALSE(isp_proc && hist_cfg && ret_hdl, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_hist_ctlr_t hist_ctlr = heap_caps_calloc(1, sizeof(isp_hist_controller_t), ISP_MEM_ALLOC_CAPS);
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ESP_RETURN_ON_FALSE(hist_ctlr, ESP_ERR_NO_MEM, TAG, "no mem for hist controller");
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hist_ctlr->evt_que = xQueueCreateWithCaps(1, sizeof(isp_hist_result_t), ISP_MEM_ALLOC_CAPS);
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ESP_GOTO_ON_FALSE(hist_ctlr->evt_que, ESP_ERR_NO_MEM, err1, TAG, "no mem for hist event queue");
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atomic_init(&hist_ctlr->fsm, ISP_FSM_INIT);
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hist_ctlr->fsm = ISP_FSM_INIT;
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hist_ctlr->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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hist_ctlr->isp_proc = isp_proc;
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// Configure the hardware
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ESP_GOTO_ON_ERROR(s_esp_isp_hist_config_hardware(isp_proc, hist_cfg), err1, TAG, "configure HIST hardware failed");
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// Claim an hist controller
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ESP_GOTO_ON_ERROR(s_isp_claim_hist_controller(isp_proc, hist_ctlr), err1, TAG, "no available controller");
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// Register the HIGT ISR
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ESP_GOTO_ON_ERROR(esp_isp_register_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST), err2, TAG, "fail to register ISR");
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*ret_hdl = hist_ctlr;
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return ESP_OK;
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err2:
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s_isp_declaim_hist_controller(hist_ctlr);
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err1:
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s_isp_hist_free_controller(hist_ctlr);
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return ret;
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}
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esp_err_t esp_isp_del_hist_controller(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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ESP_RETURN_ON_FALSE(hist_ctlr->isp_proc->hist_ctlr == hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "controller isn't in use");
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ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
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// Deregister the HIST ISR
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ESP_RETURN_ON_FALSE(esp_isp_deregister_isr(hist_ctlr->isp_proc, ISP_SUBMODULE_HIST) == ESP_OK, ESP_FAIL, TAG, "fail to deregister ISR");
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s_isp_declaim_hist_controller(hist_ctlr);
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s_isp_hist_free_controller(hist_ctlr);
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_enable(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_fsm_t expected_fsm = ISP_FSM_INIT;
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ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
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ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
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isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, true);
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isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, true);
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_disable(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && hist_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
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ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_INIT),
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ESP_ERR_INVALID_STATE, TAG, "controller not in enable state");
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isp_ll_enable_intr(hist_ctlr->isp_proc->hal.hw, ISP_LL_EVENT_HIST_MASK, false);
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isp_ll_hist_clk_enable(hist_ctlr->isp_proc->hal.hw, false);
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esp_intr_disable(hist_ctlr->intr_handle);
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_get_oneshot_statistics(isp_hist_ctlr_t hist_ctlr, int timeout_ms, isp_hist_result_t *out_res)
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{
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ESP_RETURN_ON_FALSE_ISR(hist_ctlr && (out_res || timeout_ms == 0), ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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esp_err_t ret = ESP_OK;
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TickType_t ticks = timeout_ms < 0 ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms);
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isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
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ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ONESHOT), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet");
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// Reset the queue in case receiving the legacy data in the queue
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xQueueReset(hist_ctlr->evt_que);
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// Start the histogram reference statistics and waiting it done
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isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
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// Wait the statistics to finish and receive the result from the queue
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if (xQueueReceive(hist_ctlr->evt_que, out_res, ticks) != pdTRUE) {
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ret = ESP_ERR_TIMEOUT;
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}
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// Stop the histogram reference statistics
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isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
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atomic_store(&hist_ctlr->fsm, ISP_FSM_ENABLE);
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return ret;
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}
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esp_err_t esp_isp_hist_controller_start_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_fsm_t expected_fsm = ISP_FSM_ENABLE;
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ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_CONTINUOUS), ESP_ERR_INVALID_STATE, TAG, "controller is not enabled yet");
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isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, true);
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return ESP_OK;
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}
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esp_err_t esp_isp_hist_controller_stop_continuous_statistics(isp_hist_ctlr_t hist_ctlr)
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{
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ESP_RETURN_ON_FALSE_ISR(hist_ctlr, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
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isp_fsm_t expected_fsm = ISP_FSM_CONTINUOUS;
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ESP_RETURN_ON_FALSE_ISR(atomic_compare_exchange_strong(&hist_ctlr->fsm, &expected_fsm, ISP_FSM_ENABLE),
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ESP_ERR_INVALID_STATE, TAG, "controller is not running");
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isp_ll_hist_enable(hist_ctlr->isp_proc->hal.hw, false);
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return ESP_OK;
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}
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/*---------------------------------------------------------------
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INTR
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---------------------------------------------------------------*/
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bool IRAM_ATTR esp_isp_hist_isr(isp_proc_handle_t proc, uint32_t hist_events)
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{
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bool need_yield = false;
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if (hist_events & ISP_LL_EVENT_HIST_FDONE) {
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isp_hist_ctlr_t hist_ctlr = proc->hist_ctlr;
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uint32_t hist_value[ISP_HIST_SEGMENT_NUMS] = {};
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isp_ll_hist_get_histogram_value(proc->hal.hw, hist_value);
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// Get the statistics result
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esp_isp_hist_evt_data_t edata = {};
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for (int i = 0; i < ISP_HIST_SEGMENT_NUMS; i++) {
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edata.hist_result.hist_value[i] = hist_value[i];
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}
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// Invoke the callback if the callback is registered
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if (hist_ctlr->cbs.on_statistics_done) {
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need_yield |= hist_ctlr->cbs.on_statistics_done(hist_ctlr, &edata, hist_ctlr->user_data);
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}
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BaseType_t high_task_awake = false;
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// Send the event data to the queue, overwrite the legacy one if exist
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xQueueOverwriteFromISR(hist_ctlr->evt_que, &edata.hist_result, &high_task_awake);
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need_yield |= high_task_awake == pdTRUE;
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}
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return need_yield;
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}
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esp_err_t esp_isp_hist_register_event_callbacks(isp_hist_ctlr_t hist_ctlr, const esp_isp_hist_cbs_t *cbs, void *user_data)
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{
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ESP_RETURN_ON_FALSE(hist_ctlr && cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
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ESP_RETURN_ON_FALSE(atomic_load(&hist_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
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#if CONFIG_ISP_ISR_IRAM_SAFE
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if (cbs->on_statistics_done) {
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ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_env_change), ESP_ERR_INVALID_ARG, TAG, "on_statistics_done callback not in IRAM");
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}
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if (user_data) {
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ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
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}
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#endif
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hist_ctlr->cbs.on_statistics_done = cbs->on_statistics_done;
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hist_ctlr->user_data = user_data;
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return ESP_OK;
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}
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