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feat(ulp_riscv): Add pulse counter example code for ulp riscv Closes IDF-14106 See merge request espressif/esp-idf!42107
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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System Examples
Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates), deep sleep logging, and event loops.
See the README.md file in the upper level examples directory for more information about examples.