mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-19 07:55:54 +00:00
d15a9c2c48
Fixed memory leak in emac_esp_new_dma function. Polished ESP EMAC cache management. Added emac_periph definitions based on SoC features and improved(generalized) ESP EMAC GPIO initialization. Added ESP EMAC GPIO reservation. Added check for frame error condition indicated by EMAC DMA and created a target test.
296 lines
14 KiB
C
296 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_assert.h"
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#include "esp_err.h"
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#include "hal/eth_types.h"
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_EMAC_SUPPORTED
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#include "hal/emac_ll.h"
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/**
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* @brief Macros to check descriptors datatype size
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*/
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#define STR(s) #s
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#define TYPE_SIZE_ERR_MSG(DATATYPE, SIZE) #DATATYPE " should occupy " STR(SIZE) " bytes in memory"
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#define ASSERT_TYPE_SIZE(DATATYPE, SIZE) ESP_STATIC_ASSERT(sizeof(DATATYPE) == SIZE, TYPE_SIZE_ERR_MSG(DATATYPE, SIZE))
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#if CONFIG_IDF_TARGET_ESP32P4
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// Descriptor must be 64B aligned for ESP32P4 due to cache arrangement
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#define EMAC_HAL_DMA_DESC_SIZE (64)
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#else
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#define EMAC_HAL_DMA_DESC_SIZE (32)
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#endif
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/* DMA descriptor control bits */
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#define EMAC_HAL_TDES0_INTR_ON_COMPLET (1 << 30)
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#define EMAC_HAL_TDES0_CRC_APPEND_DISABLE (1 << 27)
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#define EMAC_HAL_TDES0_PAD_DISABLE (1 << 26)
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#define EMAC_HAL_TDES0_TX_TS_ENABLE (1 << 25)
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#define EMAC_HAL_TDES0_CRC_REPLACE_CTRL (1 << 24)
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#define EMAC_HAL_TDES0_IP_CRC_INSERT_HDR (1 << 22)
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#define EMAC_HAL_TDES0_IP_CRC_INSERT_HDR_PAYLOAD (2 << 22)
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#define EMAC_HAL_TDES0_IP_CRC_INSERT_HDR_PAYLOAD_PSEUDO (3 << 22)
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#define EMAC_HAL_TDES0_VLAN_REMOVE (1 << 18)
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#define EMAC_HAL_TDES0_VLAN_INSERT (2 << 18)
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#define EMAC_HAL_TDES0_VLAN_REPLACE (3 << 18)
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#define EMAC_HAL_TDES0_IP_CRC_INSERT_DISABLE_MASK (3 << 22)
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#define EMAC_HAL_TDES0_VLAN_INSERT_DISABLE_MASK (3 << 18)
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/**
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* @brief Ethernet DMA TX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t Deferred : 1; /*!< MAC defers before transmission */
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uint32_t UnderflowErr : 1; /*!< DMA encountered an empty transmit buffer */
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uint32_t ExcessiveDeferral : 1; /*!< Excessive deferral of over 24,288 bit times */
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uint32_t CollisionCount : 4; /*!< Number of collisions occurred before transmitted */
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uint32_t VLanFrame : 1; /*!< Transmitted frame is a VLAN-type frame */
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uint32_t ExcessiveCollision : 1; /*!< Transmission aborted after 16 successive collisions */
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uint32_t LateCollision : 1; /*!< Collision occurred after the collision window */
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uint32_t NoCarrier : 1; /*!< Carrier Sense signal from the PHY was not asserted */
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uint32_t LossCarrier : 1; /*!< Loss of carrier occurred during transmission */
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uint32_t PayloadChecksumErr : 1; /*!< Checksum error in TCP/UDP/ICMP datagram payload */
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uint32_t FrameFlushed : 1; /*!< DMA or MTL flushed the frame */
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uint32_t JabberTimeout : 1; /*!< MAC transmitter has experienced a jabber timeout */
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uint32_t ErrSummary : 1; /*!< Error Summary */
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uint32_t IPHeadErr : 1; /*!< IP Header Error */
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uint32_t TxTimestampStatus : 1; /*!< Timestamp captured for the transmit frame */
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uint32_t VLANInsertControl : 2; /*!< VLAN tagging or untagging before transmitting */
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uint32_t SecondAddressChained : 1; /*!< Second address in the descriptor is Next Descriptor address */
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uint32_t TransmitEndRing : 1; /*!< Descriptor list reached its final descriptor */
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uint32_t ChecksumInsertControl : 2; /*!< Control checksum calculation and insertion */
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uint32_t CRCReplacementControl : 1; /*!< Control CRC replace */
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uint32_t TransmitTimestampEnable : 1; /*!< Enable IEEE1588 hardware timestamping */
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uint32_t DisablePad : 1; /*!< Control add padding when frame short than 64 bytes */
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uint32_t DisableCRC : 1; /*!< Control append CRC to the end of frame */
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uint32_t FirstSegment : 1; /*!< Buffer contains the first segment of a frame */
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uint32_t LastSegment : 1; /*!< Buffer contains the last segment of a frame */
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uint32_t InterruptOnComplete : 1; /*!< Interrupt after frame transmitted */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} TDES0;
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union {
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struct {
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uint32_t TransmitBuffer1Size : 13; /*!< First data buffer byte size */
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uint32_t Reserved : 3; /*!< Reserved */
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uint32_t TransmitBuffer2Size : 13; /*!< Second data buffer byte size */
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uint32_t SAInsertControl : 3; /*!< Control MAC add or replace Source Address field */
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};
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uint32_t Value;
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} TDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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uint32_t Reserved1; /*!< Reserved */
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uint32_t Reserved2; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Transmit Frame Timestamp Low */
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uint32_t TimeStampHigh; /*!< Transmit Frame Timestamp High */
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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// descriptor must be aligned (due to cache arrangement)
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uint8_t CacheAlign[EMAC_HAL_DMA_DESC_SIZE - 32]; // 32 is size of EMAC DMA descriptor without alignment
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#endif
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} eth_dma_tx_descriptor_t;
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ASSERT_TYPE_SIZE(eth_dma_tx_descriptor_t, EMAC_HAL_DMA_DESC_SIZE);
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/**
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* @brief Ethernet DMA RX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t ExtendStatusAvailable : 1; /*!< Extended statsu is available in RDES4 */
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uint32_t CRCErr : 1; /*!< CRC error occurred on frame */
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uint32_t DribbleBitErr : 1; /*!< frame contains non int multiple of 8 bits */
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uint32_t ReceiveErr : 1; /*!< Receive error */
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uint32_t ReceiveWatchdogTimeout : 1; /*!< Receive Watchdog timeout */
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uint32_t FrameType : 1; /*!< Ethernet type or IEEE802.3 */
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uint32_t LateCollision : 1; /*!< Late collision occurred during reception */
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uint32_t TSAvailIPChecksumErrGiantFrame : 1; /*!< Timestamp available or IP Checksum error or Giant frame */
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uint32_t LastDescriptor : 1; /*!< Last buffer of the frame */
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uint32_t FirstDescriptor : 1; /*!< First buffer of the frame */
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uint32_t VLANTag : 1; /*!< VLAN Tag: received frame is a VLAN frame */
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uint32_t OverflowErr : 1; /*!< Frame was damaged due to buffer overflow */
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uint32_t LengthErr : 1; /*!< Frame size not matching with length field */
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uint32_t SourceAddrFilterFail : 1; /*!< SA field of frame failed the SA filter */
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uint32_t DescriptorErr : 1; /*!< Frame truncated and DMA doesn't own next descriptor */
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uint32_t ErrSummary : 1; /*!< Error Summary, OR of all errors in RDES */
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uint32_t FrameLength : 14; /*!< Byte length of received frame */
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uint32_t DestinationAddrFilterFail : 1; /*!< Frame failed in the DA Filter in the MAC */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} RDES0;
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union {
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struct {
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uint32_t ReceiveBuffer1Size : 13; /*!< First data buffer size in bytes */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t SecondAddressChained : 1; /*!< Seconde address is the Next Descriptor address */
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uint32_t ReceiveEndOfRing : 1; /*!< Descriptor reached its final descriptor */
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uint32_t ReceiveBuffer2Size : 13; /*!< Second data buffer size in bytes */
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uint32_t Reserved : 2; /*!< Reserved */
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uint32_t DisableInterruptOnComplete : 1; /*!< Disable the assertion of interrupt to host */
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};
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uint32_t Value;
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} RDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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volatile union {
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struct {
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uint32_t IPPayloadType : 3; /*!< Type of payload in the IP datagram */
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uint32_t IPHeadErr : 1; /*!< IP header error */
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uint32_t IPPayloadErr : 1; /*!< IP payload error */
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uint32_t IPChecksumBypass : 1; /*!< Checksum offload engine is bypassed */
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uint32_t IPv4PacketReceived : 1; /*!< Received packet is an IPv4 packet */
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uint32_t IPv6PacketReceived : 1; /*!< Received packet is an IPv6 packet */
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uint32_t MessageType : 4; /*!< PTP Message Type */
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uint32_t PTPFrameType : 1; /*!< PTP message is over Ethernet or IPv4/IPv6 */
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uint32_t PTPVersion : 1; /*!< Version of PTP protocol */
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uint32_t TimestampDropped : 1; /*!< Timestamp dropped because of overflow */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t AVPacketReceived : 1; /*!< AV packet is received */
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uint32_t AVTaggedPacketReceived : 1; /*!< AV tagged packet is received */
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uint32_t VLANTagPrioVal : 3; /*!< VLAN tag's user value in the received packekt */
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uint32_t Reserved2 : 3; /*!< Reserved */
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uint32_t Layer3FilterMatch : 1; /*!< Received frame matches one of the enabled Layer3 IP */
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uint32_t Layer4FilterMatch : 1; /*!< Received frame matches one of the enabled Layer4 IP */
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uint32_t Layer3Layer4FilterNumberMatch : 2; /*!< Number of Layer3 and Layer4 Filter that matches the received frame */
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uint32_t Reserved3 : 4; /*!< Reserved */
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};
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uint32_t Value;
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} ExtendedStatus;
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uint32_t Reserved; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Receive frame timestamp low */
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uint32_t TimeStampHigh; /*!< Receive frame timestamp high */
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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// descriptor must be aligned (due to cache arrangement)
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uint8_t CacheAlign[EMAC_HAL_DMA_DESC_SIZE - 32]; // 32 is size of EMAC DMA descriptor without alignment
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#endif
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} eth_dma_rx_descriptor_t;
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ASSERT_TYPE_SIZE(eth_dma_rx_descriptor_t, EMAC_HAL_DMA_DESC_SIZE);
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typedef struct emac_mac_dev_s *emac_mac_soc_regs_t;
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typedef struct emac_dma_dev_s *emac_dma_soc_regs_t;
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#if CONFIG_IDF_TARGET_ESP32
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typedef struct emac_ext_dev_s *emac_ext_soc_regs_t;
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#else
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typedef void *emac_ext_soc_regs_t;
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#endif
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typedef struct {
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emac_mac_soc_regs_t mac_regs;
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emac_dma_soc_regs_t dma_regs;
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emac_ext_soc_regs_t ext_regs;
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} emac_hal_context_t;
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/**
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* @brief EMAC related configuration
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*/
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typedef struct {
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eth_mac_dma_burst_len_t dma_burst_len; /*!< eth-type enum of chosen dma burst-len */
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} emac_hal_dma_config_t;
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void emac_hal_init(emac_hal_context_t *hal);
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#define emac_hal_get_phy_intf(hal) emac_ll_get_phy_intf((hal)->ext_regs)
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#define emac_hal_clock_enable_mii(hal) emac_ll_clock_enable_mii((hal)->ext_regs)
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#define emac_hal_clock_enable_rmii_input(hal) emac_ll_clock_enable_rmii_input((hal)->ext_regs)
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#ifdef CONFIG_IDF_TARGET_ESP32P4
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#define emac_hal_clock_rmii_rx_tx_div(hal, div) emac_ll_clock_rmii_rx_tx_div((hal)->ext_regs, div)
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#endif // CONFIG_IDF_TARGET_ESP32P4
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#define emac_hal_clock_enable_rmii_output(hal) emac_ll_clock_enable_rmii_output((hal)->ext_regs)
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#define emac_hal_reset(hal) emac_ll_reset((hal)->dma_regs)
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#define emac_hal_is_reset_done(hal) emac_ll_is_reset_done((hal)->dma_regs)
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void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq);
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void emac_hal_init_mac_default(emac_hal_context_t *hal);
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void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *hal_config);
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#define emac_hal_set_speed(hal, speed) emac_ll_set_port_speed((hal)->mac_regs, speed)
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#define emac_hal_set_duplex(hal, duplex) emac_ll_set_duplex((hal)->mac_regs, duplex)
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#define emac_hal_set_promiscuous(hal, enable) emac_ll_promiscuous_mode_enable((hal)->mac_regs, enable)
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/**
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* @brief Send MAC-CTRL frames to peer (EtherType=0x8808, opcode=0x0001, dest_addr=MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01))
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*/
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#define emac_hal_send_pause_frame(hal, enable) emac_ll_pause_frame_enable((hal)->ext_regs, enable)
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#define emac_hal_is_mii_busy(hal) emac_ll_is_mii_busy((hal)->mac_regs)
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void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write);
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#define emac_hal_set_phy_data(hal, reg_value) emac_ll_set_phy_data((hal)->mac_regs, reg_value)
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#define emac_hal_get_phy_data(hal) emac_ll_get_phy_data((hal)->mac_regs)
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void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
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/**
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* @brief Starts EMAC Transmission & Reception
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*
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* @param hal EMAC HAL context infostructure
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*/
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void emac_hal_start(emac_hal_context_t *hal);
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/**
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* @brief Stops EMAC Transmission & Reception
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*
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* @param hal EMAC HAL context infostructure
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* @return
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* - ESP_OK: succeed
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* - ESP_ERR_INVALID_STATE: previous frame transmission/reception is not completed. When this error occurs,
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* wait and repeat the EMAC stop again.
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*/
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esp_err_t emac_hal_stop(emac_hal_context_t *hal);
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void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable);
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#define emac_hal_get_intr_enable_status(hal) emac_ll_get_intr_enable_status((hal)->dma_regs)
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#define emac_hal_get_intr_status(hal) emac_ll_get_intr_status((hal)->dma_regs)
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#define emac_hal_clear_corresponding_intr(hal, bits) emac_ll_clear_corresponding_intr((hal)->dma_regs, bits)
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#define emac_hal_clear_all_intr(hal) emac_ll_clear_all_pending_intr((hal)->dma_regs)
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void emac_hal_set_rx_tx_desc_addr(emac_hal_context_t *hal, eth_dma_rx_descriptor_t *rx_desc, eth_dma_tx_descriptor_t *tx_desc);
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#define emac_hal_receive_poll_demand(hal) emac_ll_receive_poll_demand((hal)->dma_regs, 0)
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#define emac_hal_transmit_poll_demand(hal) emac_ll_transmit_poll_demand((hal)->dma_regs, 0)
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#endif // SOC_EMAC_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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