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58c3f6a421
Many files in the HAL layer depended on SOC_ macros without explicitly including soc_caps.h
275 lines
8.7 KiB
C
275 lines
8.7 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The HAL layer for I2S (common part)
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "hal/i2s_hal.h"
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#define I2S_TX_PDM_FP_DEF 960 // Set to the recommended value(960) in TRM
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#define I2S_RX_PDM_DSR_DEF 0
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void i2s_hal_set_tx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits)
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{
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if (bits <= I2S_BITS_PER_SAMPLE_16BIT) {
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i2s_ll_set_tx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
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} else {
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i2s_ll_set_tx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 2 : 3);
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}
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i2s_ll_set_tx_chan_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
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#if SOC_I2S_SUPPORTS_DMA_EQUAL
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i2s_ll_set_tx_dma_equal(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
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#endif
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}
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void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_sample_t bits)
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{
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if (bits <= I2S_BITS_PER_SAMPLE_16BIT) {
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i2s_ll_set_rx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
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} else {
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i2s_ll_set_rx_fifo_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 2 : 3);
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}
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i2s_ll_set_rx_chan_mod(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
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#if SOC_I2S_SUPPORTS_DMA_EQUAL
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i2s_ll_set_rx_dma_equal(hal->dev, (ch == I2S_CHANNEL_STEREO) ? 0 : 1);
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#endif
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}
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void i2s_hal_set_in_link(i2s_hal_context_t *hal, uint32_t bytes_num, uint32_t addr)
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{
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i2s_ll_set_in_link_addr(hal->dev, addr);
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i2s_ll_set_rx_eof_num(hal->dev, bytes_num);
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}
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#if SOC_I2S_SUPPORTS_PDM
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void i2s_hal_tx_pdm_cfg(i2s_hal_context_t *hal, uint32_t fp, uint32_t fs)
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{
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i2s_ll_tx_pdm_cfg(hal->dev, fp, fs);
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}
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void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, uint32_t *fp, uint32_t *fs)
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{
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i2s_ll_get_tx_pdm(hal->dev, fp, fs);
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}
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void i2s_hal_rx_pdm_cfg(i2s_hal_context_t *hal, uint32_t dsr)
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{
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i2s_ll_rx_pdm_cfg(hal->dev, dsr);
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}
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void i2s_hal_get_rx_pdm(i2s_hal_context_t *hal, uint32_t *dsr)
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{
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i2s_ll_get_rx_pdm(hal->dev, dsr);
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}
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#endif
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void i2s_hal_set_clk_div(i2s_hal_context_t *hal, int div_num, int div_a, int div_b, int tx_bck_div, int rx_bck_div)
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{
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i2s_ll_set_clkm_div_num(hal->dev, div_num);
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i2s_ll_set_clkm_div_a(hal->dev, div_a);
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i2s_ll_set_clkm_div_b(hal->dev, div_b);
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i2s_ll_set_tx_bck_div_num(hal->dev, tx_bck_div);
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i2s_ll_set_rx_bck_div_num(hal->dev, rx_bck_div);
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}
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void i2s_hal_set_tx_bits_mod(i2s_hal_context_t *hal, i2s_bits_per_sample_t bits)
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{
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i2s_ll_set_tx_bits_mod(hal->dev, bits);
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}
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void i2s_hal_set_rx_bits_mod(i2s_hal_context_t *hal, i2s_bits_per_sample_t bits)
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{
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i2s_ll_set_rx_bits_mod(hal->dev, bits);
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}
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void i2s_hal_reset(i2s_hal_context_t *hal)
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{
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// Reset I2S TX/RX module first, and then, reset DMA and FIFO.
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i2s_ll_reset_tx(hal->dev);
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i2s_ll_reset_rx(hal->dev);
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i2s_ll_reset_dma_in(hal->dev);
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i2s_ll_reset_dma_out(hal->dev);
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i2s_ll_reset_rx_fifo(hal->dev);
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i2s_ll_reset_tx_fifo(hal->dev);
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}
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void i2s_hal_start_tx(i2s_hal_context_t *hal)
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{
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i2s_ll_start_out_link(hal->dev);
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i2s_ll_start_tx(hal->dev);
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}
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void i2s_hal_start_rx(i2s_hal_context_t *hal)
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{
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i2s_ll_start_in_link(hal->dev);
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i2s_ll_start_rx(hal->dev);
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}
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void i2s_hal_stop_tx(i2s_hal_context_t *hal)
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{
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i2s_ll_stop_out_link(hal->dev);
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i2s_ll_stop_tx(hal->dev);
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}
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void i2s_hal_stop_rx(i2s_hal_context_t *hal)
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{
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i2s_ll_stop_in_link(hal->dev);
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i2s_ll_stop_rx(hal->dev);
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}
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void i2s_hal_format_config(i2s_hal_context_t *hal, const i2s_config_t *i2s_config)
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{
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switch (i2s_config->communication_format) {
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case I2S_COMM_FORMAT_STAND_MSB:
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if (i2s_config->mode & I2S_MODE_TX) {
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i2s_ll_set_tx_format_msb_align(hal->dev);
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}
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if (i2s_config->mode & I2S_MODE_RX) {
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i2s_ll_set_rx_format_msb_align(hal->dev);
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}
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break;
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case I2S_COMM_FORMAT_STAND_PCM_SHORT:
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if (i2s_config->mode & I2S_MODE_TX) {
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i2s_ll_set_tx_pcm_long(hal->dev);
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}
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if (i2s_config->mode & I2S_MODE_RX) {
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i2s_ll_set_rx_pcm_long(hal->dev);
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}
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break;
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case I2S_COMM_FORMAT_STAND_PCM_LONG:
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if (i2s_config->mode & I2S_MODE_TX) {
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i2s_ll_set_tx_pcm_short(hal->dev);
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}
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if (i2s_config->mode & I2S_MODE_RX) {
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i2s_ll_set_rx_pcm_short(hal->dev);
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}
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break;
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default: //I2S_COMM_FORMAT_STAND_I2S
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if (i2s_config->mode & I2S_MODE_TX) {
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i2s_ll_set_tx_format_philip(hal->dev);
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}
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if (i2s_config->mode & I2S_MODE_RX) {
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i2s_ll_set_rx_format_philip(hal->dev);
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}
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break;
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}
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}
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void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_config_t *i2s_config)
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{
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//reset i2s
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i2s_ll_reset_tx(hal->dev);
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i2s_ll_reset_rx(hal->dev);
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//reset dma
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i2s_ll_reset_dma_in(hal->dev);
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i2s_ll_reset_dma_out(hal->dev);
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i2s_ll_enable_dma(hal->dev);
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i2s_ll_set_lcd_en(hal->dev, 0);
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i2s_ll_set_camera_en(hal->dev, 0);
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i2s_ll_set_dscr_en(hal->dev, 0);
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i2s_ll_set_tx_chan_mod(hal->dev, i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ? i2s_config->channel_format : (i2s_config->channel_format >> 1)); // 0-two channel;1-right;2-left;3-righ;4-left
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i2s_ll_set_tx_fifo_mod(hal->dev, i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ? 0 : 1); // 0-right&left channel;1-one channel
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i2s_ll_set_tx_mono(hal->dev, 0);
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i2s_ll_set_rx_chan_mod(hal->dev, i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ? i2s_config->channel_format : (i2s_config->channel_format >> 1)); // 0-two channel;1-right;2-left;3-righ;4-left
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i2s_ll_set_rx_fifo_mod(hal->dev, i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ? 0 : 1); // 0-right&left channel;1-one channel
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i2s_ll_set_rx_mono(hal->dev, 0);
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i2s_ll_set_dscr_en(hal->dev, 1); //connect dma to fifo
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i2s_ll_stop_tx(hal->dev);
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i2s_ll_stop_rx(hal->dev);
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if (i2s_config->mode & I2S_MODE_TX) {
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i2s_ll_set_tx_msb_right(hal->dev, 0);
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i2s_ll_set_tx_right_first(hal->dev, 0);
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i2s_ll_set_tx_slave_mod(hal->dev, 0); // Master
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i2s_ll_set_tx_fifo_mod_force_en(hal->dev, 1);
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if (i2s_config->mode & I2S_MODE_SLAVE) {
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i2s_ll_set_tx_slave_mod(hal->dev, 1); //TX Slave
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}
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}
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if (i2s_config->mode & I2S_MODE_RX) {
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i2s_ll_set_rx_msb_right(hal->dev, 0);
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i2s_ll_set_rx_right_first(hal->dev, 0);
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i2s_ll_set_rx_slave_mod(hal->dev, 0); // Master
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i2s_ll_set_rx_fifo_mod_force_en(hal->dev, 1);
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if (i2s_config->mode & I2S_MODE_SLAVE) {
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i2s_ll_set_rx_slave_mod(hal->dev, 1); //RX Slave
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}
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}
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#if SOC_I2S_SUPPORTS_PDM
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if (!(i2s_config->mode & I2S_MODE_PDM)) {
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i2s_ll_set_rx_pdm_en(hal->dev, 0);
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i2s_ll_set_tx_pdm_en(hal->dev, 0);
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} else {
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if (i2s_config->mode & I2S_MODE_TX) {
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i2s_ll_tx_pdm_cfg(hal->dev, I2S_TX_PDM_FP_DEF, i2s_config->sample_rate/100);
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}
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if(i2s_config->mode & I2S_MODE_RX) {
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i2s_ll_rx_pdm_cfg(hal->dev, I2S_RX_PDM_DSR_DEF);
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}
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// PDM mode have nothing to do with communication format configuration.
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return;
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}
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#endif
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#if SOC_I2S_SUPPORTS_ADC_DAC
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if (i2s_config->mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN)) {
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if (i2s_config->mode & I2S_MODE_DAC_BUILT_IN) {
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i2s_ll_build_in_dac_ena(hal->dev);
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}
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if (i2s_config->mode & I2S_MODE_ADC_BUILT_IN) {
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i2s_ll_build_in_adc_ena(hal->dev);
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i2s_ll_set_rx_chan_mod(hal->dev, 1);
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i2s_ll_set_rx_fifo_mod(hal->dev, 1);
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i2s_ll_set_rx_mono(hal->dev, 0);
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}
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// Buildin ADC and DAC have nothing to do with communication format configuration.
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return;
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}
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#endif
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i2s_hal_format_config(hal, i2s_config);
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}
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void i2s_hal_enable_master_mode(i2s_hal_context_t *hal)
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{
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i2s_ll_set_tx_slave_mod(hal->dev, 0); //MASTER Slave
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i2s_ll_set_rx_slave_mod(hal->dev, 1); //RX Slave
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}
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void i2s_hal_enable_slave_mode(i2s_hal_context_t *hal)
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{
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i2s_ll_set_tx_slave_mod(hal->dev, 1); //TX Slave
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i2s_ll_set_rx_slave_mod(hal->dev, 1); //RX Slave
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}
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void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num)
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{
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//Get hardware instance.
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hal->dev = I2S_LL_GET_HW(i2s_num);
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}
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