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https://github.com/espressif/esp-idf.git
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75 lines
1.7 KiB
C
75 lines
1.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// TinyUSB Port selection
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//
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#if (CONFIG_IDF_TARGET_ESP32P4)
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#define CONFIG_TINYUSB_RHPORT_HS
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#endif // CONFIG_IDF_TARGET_ESP32P4
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//
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// TinyUSB Debug
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//
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#define CFG_TUSB_DEBUG CONFIG_TINYUSB_DEBUG_LEVEL
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//
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// TinyUSB Peripheral Port selection (build-time)
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//
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#ifdef CONFIG_TINYUSB_RHPORT_HS
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# define CFG_TUSB_RHPORT1_MODE OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED
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#else
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# define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED
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#endif
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//
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// TinyUSB OS
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//
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#define CFG_TUSB_OS OPT_OS_FREERTOS
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//
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// TinyUSB specific memory attributes
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//
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//
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// DCD DWC2 Mode
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//
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#define CFG_TUD_DWC2_SLAVE_ENABLE 0 // We don't use Slave/IRQ mode in this test
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//
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// DMA & Cache
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//
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// DMA Mode has a priority over Slave/IRQ mode and will be used if hardware supports it
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#define CFG_TUD_DWC2_DMA_ENABLE 1 // Enable DMA
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#if CONFIG_CACHE_L1_CACHE_LINE_SIZE
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// To enable the dcd_dcache clean/invalidate/clean_invalidate calls
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# define CFG_TUD_MEM_DCACHE_ENABLE 1
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#define CFG_TUD_MEM_DCACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE
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// NOTE: starting with esp-idf v5.3 there is specific attribute present: DRAM_DMA_ALIGNED_ATTR
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# define CFG_TUSB_MEM_SECTION __attribute__((aligned(CONFIG_CACHE_L1_CACHE_LINE_SIZE))) DRAM_ATTR
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#else
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# define CFG_TUD_MEM_CACHE_ENABLE 0
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# define CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) DRAM_ATTR
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#endif // CONFIG_CACHE_L1_CACHE_LINE_SIZE
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//
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// TinyUSB DEVICE CONFIGURATION
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//
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#define CFG_TUD_ENABLED 1 // Enable Device stack
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#ifdef __cplusplus
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}
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#endif
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