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d0ceef20f4
This commit renames all registers in xtensa/specreg.h to by adding the prefix XT_REG_. This is done to avoid naming collisions with similar variable names. A new register file, viz., xt_specreg.h is created. The previous names are still available to use but have been deprecated. Closes https://github.com/espressif/esp-idf/issues/12723 Merges https://github.com/espressif/esp-idf/pull/16040
754 lines
28 KiB
ArmAsm
754 lines
28 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
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*
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* SPDX-License-Identifier: MIT
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*
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* SPDX-FileContributor: 2016-2023 Espressif Systems (Shanghai) CO LTD
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*/
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/*
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* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "xtensa_rtos.h"
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#include "sdkconfig.h"
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#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */
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.extern pxCurrentTCBs
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#if XCHAL_CP_NUM > 0
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/* Offsets used to get a task's coprocessor save area (CPSA) from its TCB */
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.extern offset_pxEndOfStack
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.extern offset_cpsa
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#if configNUM_CORES > 1
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/* Offset to TCB_t.xCoreID member. Used to pin unpinned tasks that use the FPU. */
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.extern offset_xCoreID
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#endif /* configNUM_CORES > 1 */
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#endif /* XCHAL_CP_NUM > 0 */
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/*
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--------------------------------------------------------------------------------
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Macro get_cpsa_from_tcb - get the pointer to a task's CPSA form its TCB
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Entry:
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- "reg_A" contains a pointer to the task's TCB
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Exit:
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- "reg_A" contains pointer the the task's CPSA
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- "reg_B" clobbered
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The two arguments must be different AR registers.
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--------------------------------------------------------------------------------
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*/
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#if XCHAL_CP_NUM > 0
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.macro get_cpsa_from_tcb reg_A reg_B
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/* Get TCB.pxEndOfStack from reg_A */
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movi \reg_B, offset_pxEndOfStack /* Move &offset_pxEndOfStack into reg_B */
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l32i \reg_B, \reg_B, 0 /* Load offset_pxEndOfStack into reg_B */
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add \reg_A, \reg_A, \reg_B /* Calculate &pxEndOfStack to reg_A (&TCB + offset_pxEndOfStack) */
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l32i \reg_A, \reg_A, 0 /* Load TCB.pxEndOfStack into reg_A */
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/* Offset to start of CP save area */
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movi \reg_B, offset_cpsa /* Move &offset_cpsa into reg_B */
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l32i \reg_B, \reg_B, 0 /* Load offset_cpsa into reg_B */
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sub \reg_A, \reg_A, \reg_B /* Subtract offset_cpsa from pxEndOfStack to get to start of CP save area (unaligned) */
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/* Align down start of CP save area to 16 byte boundary */
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movi \reg_B, ~(0xF)
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and \reg_A, \reg_A, \reg_B /* Align CP save area pointer to 16 bytes */
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.endm
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#endif /* XCHAL_CP_NUM > 0 */
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.global port_IntStack
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.global port_switch_flag //Required by sysview_tracing build
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.text
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/*
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*******************************************************************************
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* _frxt_setup_switch
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* void _frxt_setup_switch(void);
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*
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* Sets an internal flag indicating that a task switch is required on return
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* from interrupt handling.
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*
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*******************************************************************************
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*/
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.global _frxt_setup_switch
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.type _frxt_setup_switch,@function
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.align 4
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_frxt_setup_switch:
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ENTRY(16)
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getcoreid a3
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movi a2, port_switch_flag
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addx4 a2, a3, a2
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movi a3, 1
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s32i a3, a2, 0
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RET(16)
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/*
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*******************************************************************************
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* _frxt_int_enter
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* void _frxt_int_enter(void)
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*
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* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
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* freeRTOS. Saves the rest of the interrupt context (not already saved).
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* May only be called from assembly code by the 'call0' instruction, with
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* interrupts disabled.
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* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
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*
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*******************************************************************************
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*/
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.globl _frxt_int_enter
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.type _frxt_int_enter,@function
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.align 4
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_frxt_int_enter:
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/* Save a12-13 in the stack frame as required by _xt_context_save. */
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s32i a12, a1, XT_STK_A12
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s32i a13, a1, XT_STK_A13
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/* Save return address in a safe place (free a0). */
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mov a12, a0
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/* Save the rest of the interrupted context (preserves A12-13). */
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call0 _xt_context_save
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/*
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Save interrupted task's SP in TCB only if not nesting.
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Manage nesting directly rather than call the generic IntEnter()
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(in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
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*/
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getcoreid a4
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movi a2, port_xSchedulerRunning
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addx4 a2, a4, a2
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movi a3, port_interruptNesting
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addx4 a3, a4, a3
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l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */
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beqz a2, 1f /* scheduler not running, no tasks */
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l32i a2, a3, 0 /* a2 = port_interruptNesting */
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addi a2, a2, 1 /* increment nesting count */
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s32i a2, a3, 0 /* save nesting count */
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bnei a2, 1, .Lnested /* !=0 before incr, so nested */
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movi a2, pxCurrentTCBs
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addx4 a2, a4, a2
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l32i a2, a2, 0 /* a2 = current TCB */
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beqz a2, 1f
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s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCBs->pxTopOfStack = SP */
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movi a1, port_IntStack+configISR_STACK_SIZE /* a1 = top of intr stack for CPU 0 */
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movi a2, configISR_STACK_SIZE /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */
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mull a2, a4, a2
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add a1, a1, a2 /* for current proc */
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#if CONFIG_FREERTOS_FPU_IN_ISR && XCHAL_CP_NUM > 0
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rsr a3, CPENABLE /* Restore thread scope CPENABLE */
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addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */
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s32i a3, a1, 0 /* its trigger */
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#endif
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.Lnested:
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1:
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#if CONFIG_FREERTOS_FPU_IN_ISR && XCHAL_CP_NUM > 0
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movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */
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wsr a3, CPENABLE
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rsync
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#endif
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mov a0, a12 /* restore return addr and return */
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ret
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/*
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*******************************************************************************
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* _frxt_int_exit
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* void _frxt_int_exit(void)
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*
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* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
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* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
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* switching, restore the (possibly) new task's context, and return to the
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* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
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* May only be called from assembly code by the 'call0' instruction. Does not
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* return to caller.
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* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
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*
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*******************************************************************************
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*/
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.globl _frxt_int_exit
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.type _frxt_int_exit,@function
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.align 4
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_frxt_int_exit:
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getcoreid a4
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movi a2, port_xSchedulerRunning
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addx4 a2, a4, a2
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movi a3, port_interruptNesting
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addx4 a3, a4, a3
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rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */
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l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */
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beqz a2, .Lnoswitch /* scheduler not running, no tasks */
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l32i a2, a3, 0 /* a2 = port_interruptNesting */
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addi a2, a2, -1 /* decrement nesting count */
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s32i a2, a3, 0 /* save nesting count */
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bnez a2, .Lnesting /* !=0 after decr so still nested */
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#if CONFIG_FREERTOS_FPU_IN_ISR && XCHAL_CP_NUM > 0
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l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */
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addi sp, sp, 4
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wsr a3, CPENABLE
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rsync /* ensure CPENABLE was modified */
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#endif
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movi a2, pxCurrentTCBs
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addx4 a2, a4, a2
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l32i a2, a2, 0 /* a2 = current TCB */
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beqz a2, 1f /* no task ? go to dispatcher */
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l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCBs->pxTopOfStack */
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movi a2, port_switch_flag /* address of switch flag */
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addx4 a2, a4, a2 /* point to flag for this cpu */
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l32i a3, a2, 0 /* a3 = port_switch_flag */
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beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */
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movi a3, 0
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s32i a3, a2, 0 /* zero out the flag for next time */
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1:
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/*
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Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
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However a12-13 were already saved by _frxt_int_enter().
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*/
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#ifdef __XTENSA_CALL0_ABI__
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s32i a14, a1, XT_STK_A14
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s32i a15, a1, XT_STK_A15
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#endif
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#ifdef __XTENSA_CALL0_ABI__
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call0 vPortYieldFromInt /* call dispatch inside the function; never returns */
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#else
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call4 vPortYieldFromInt /* this one returns */
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call0 _frxt_dispatch /* tail-call dispatcher */
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/* Never returns here. */
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#endif
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.Lnoswitch:
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/*
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If we came here then about to resume the interrupted task.
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*/
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.Lnesting:
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/*
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We come here only if there was no context switch, that is if this
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is a nested interrupt, or the interrupted task was not preempted.
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In either case there's no need to load the SP.
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*/
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/* Restore full context from interrupt stack frame */
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call0 _xt_context_restore
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/*
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Must return via the exit dispatcher corresponding to the entrypoint from which
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this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
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stack frame is deallocated in the exit dispatcher.
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*/
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l32i a0, a1, XT_STK_EXIT
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ret
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/*
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**********************************************************************************************************
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* _frxt_timer_int
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* void _frxt_timer_int(void)
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*
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* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
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* Called every timer interrupt.
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* Manages the tick timer and calls xPortSysTickHandler() every tick.
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* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
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*
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* Callable from C (obeys ABI conventions). Implemented in assembly code for performance.
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*
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**********************************************************************************************************
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*/
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#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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.globl _frxt_timer_int
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.type _frxt_timer_int,@function
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.align 4
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_frxt_timer_int:
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/*
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Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs
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an interrupt is generated, and the handler has to set a new cycle count into the comparator.
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To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
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not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
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than one tick late, it is necessary to process multiple ticks until the new cycle count is
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in the future, otherwise the next timer interrupt would not occur until after the cycle
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counter had wrapped (2^32 cycles later).
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do {
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ticks++;
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old_ccompare = read_ccompare_i();
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write_ccompare_i( old_ccompare + divisor );
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service one tick;
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diff = read_ccount() - old_ccompare;
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} while ( diff > divisor );
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*/
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ENTRY(16)
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#ifdef CONFIG_PM_TRACE
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movi a6, 1 /* = ESP_PM_TRACE_TICK */
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getcoreid a7
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call4 esp_pm_trace_enter
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#endif // CONFIG_PM_TRACE
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.L_xt_timer_int_catchup:
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/* Update the timer comparator for the next tick. */
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#ifdef XT_CLOCK_FREQ
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movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
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#else
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movi a3, _xt_tick_divisor
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l32i a2, a3, 0 /* a2 = comparator increment */
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#endif
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rsr a3, XT_CCOMPARE /* a3 = old comparator value */
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add a4, a3, a2 /* a4 = new comparator value */
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wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
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esync
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#ifdef __XTENSA_CALL0_ABI__
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/* Preserve a2 and a3 across C calls. */
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s32i a2, sp, 4
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s32i a3, sp, 8
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#endif
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/* Call the FreeRTOS tick handler (see port_systick.c). */
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#ifdef __XTENSA_CALL0_ABI__
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call0 xPortSysTickHandler
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#else
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call4 xPortSysTickHandler
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#endif
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#ifdef __XTENSA_CALL0_ABI__
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/* Restore a2 and a3. */
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l32i a2, sp, 4
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l32i a3, sp, 8
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#endif
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/* Check if we need to process more ticks to catch up. */
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esync /* ensure comparator update complete */
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rsr a4, XT_REG_CCOUNT /* a4 = cycle count */
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sub a4, a4, a3 /* diff = ccount - old comparator */
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blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */
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#ifdef CONFIG_PM_TRACE
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movi a6, 1 /* = ESP_PM_TRACE_TICK */
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getcoreid a7
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call4 esp_pm_trace_exit
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#endif // CONFIG_PM_TRACE
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RET(16)
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#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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/*
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**********************************************************************************************************
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* _frxt_tick_timer_init
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* void _frxt_tick_timer_init(void)
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*
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* Initialize timer and timer interrupt handler (_xt_tick_divisor_init() has already been been called).
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* Callable from C (obeys ABI conventions on entry).
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*
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**********************************************************************************************************
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*/
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#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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.globl _frxt_tick_timer_init
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.type _frxt_tick_timer_init,@function
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.align 4
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_frxt_tick_timer_init:
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ENTRY(16)
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/* Set up the periodic tick timer (assume enough time to complete init). */
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#ifdef XT_CLOCK_FREQ
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movi a3, XT_TICK_DIVISOR
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#else
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movi a2, _xt_tick_divisor
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l32i a3, a2, 0
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#endif
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rsr a2, XT_REG_CCOUNT /* current cycle count */
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add a2, a2, a3 /* time of first timer interrupt */
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wsr a2, XT_CCOMPARE /* set the comparator */
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/*
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Enable the timer interrupt at the device level. Don't write directly
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to the INTENABLE register because it may be virtualized.
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*/
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#ifdef __XTENSA_CALL0_ABI__
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movi a2, XT_TIMER_INTEN
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call0 xt_ints_on
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#else
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movi a6, XT_TIMER_INTEN
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movi a3, xt_ints_on
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callx4 a3
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#endif
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RET(16)
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#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
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/*
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**********************************************************************************************************
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* DISPATCH THE HIGH READY TASK
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* void _frxt_dispatch(void)
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*
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* Switch context to the highest priority ready task, restore its state and dispatch control to it.
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*
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* This is a common dispatcher that acts as a shared exit path for all the context switch functions
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* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
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* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
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*
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* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
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* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
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* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
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* If restoring a task that was preempted, restores all state including the task's CPENABLE.
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*
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* Entry:
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* pxCurrentTCBs points to the TCB of the task to suspend,
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* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
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*
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* Exit:
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* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
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* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
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*
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**********************************************************************************************************
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*/
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.globl _frxt_dispatch
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.type _frxt_dispatch,@function
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.align 4
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_frxt_dispatch:
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#ifdef __XTENSA_CALL0_ABI__
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call0 vTaskSwitchContext // Get next TCB to resume
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movi a2, pxCurrentTCBs
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getcoreid a3
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addx4 a2, a3, a2
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#else
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call4 vTaskSwitchContext // Get next TCB to resume
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movi a2, pxCurrentTCBs
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getcoreid a3
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addx4 a2, a3, a2
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#endif
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l32i a3, a2, 0
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l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */
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s32i a3, a2, 0
|
|
|
|
/* Determine the type of stack frame. */
|
|
l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */
|
|
bnez a2, .L_frxt_dispatch_stk
|
|
|
|
.L_frxt_dispatch_sol:
|
|
|
|
/* Solicited stack frame. Restore minimal context and return from vPortYield(). */
|
|
#if XCHAL_HAVE_THREADPTR
|
|
l32i a2, sp, XT_SOL_THREADPTR
|
|
wur.threadptr a2
|
|
#endif
|
|
l32i a3, sp, XT_SOL_PS
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
l32i a12, sp, XT_SOL_A12
|
|
l32i a13, sp, XT_SOL_A13
|
|
l32i a14, sp, XT_SOL_A14
|
|
l32i a15, sp, XT_SOL_A15
|
|
#endif
|
|
l32i a0, sp, XT_SOL_PC
|
|
#if XCHAL_CP_NUM > 0
|
|
/* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
|
|
rsync
|
|
#endif
|
|
/* As soons as PS is restored, interrupts can happen. No need to sync PS. */
|
|
wsr a3, XT_REG_PS
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
addi sp, sp, XT_SOL_FRMSZ
|
|
ret
|
|
#else
|
|
retw
|
|
#endif
|
|
|
|
.L_frxt_dispatch_stk:
|
|
|
|
#if XCHAL_CP_NUM > 0
|
|
/* Restore CPENABLE from task's co-processor save area. */
|
|
movi a2, pxCurrentTCBs /* cp_state = */
|
|
getcoreid a3
|
|
addx4 a2, a3, a2
|
|
l32i a2, a2, 0
|
|
get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */
|
|
l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */
|
|
wsr a3, XT_REG_CPENABLE
|
|
#endif
|
|
|
|
/* Interrupt stack frame. Restore full context and return to exit dispatcher. */
|
|
call0 _xt_context_restore
|
|
|
|
/* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
l32i a14, sp, XT_STK_A14
|
|
l32i a15, sp, XT_STK_A15
|
|
#endif
|
|
|
|
#if XCHAL_CP_NUM > 0
|
|
/* Ensure wsr.CPENABLE has completed. */
|
|
rsync
|
|
#endif
|
|
|
|
/*
|
|
Must return via the exit dispatcher corresponding to the entrypoint from which
|
|
this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
|
|
stack frame is deallocated in the exit dispatcher.
|
|
*/
|
|
l32i a0, sp, XT_STK_EXIT
|
|
ret
|
|
|
|
|
|
/*
|
|
**********************************************************************************************************
|
|
* PERFORM A SOLICTED CONTEXT SWITCH (from a task)
|
|
* void vPortYield(void)
|
|
*
|
|
* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
|
|
* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
|
|
*
|
|
* At Entry:
|
|
* pxCurrentTCBs points to the TCB of the task to suspend
|
|
* Callable from C (obeys ABI conventions on entry).
|
|
*
|
|
* Does not return to caller.
|
|
*
|
|
**********************************************************************************************************
|
|
*/
|
|
.globl vPortYield
|
|
.type vPortYield,@function
|
|
.align 4
|
|
vPortYield:
|
|
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
addi sp, sp, -XT_SOL_FRMSZ
|
|
#else
|
|
entry sp, XT_SOL_FRMSZ
|
|
#endif
|
|
|
|
rsr a2, XT_REG_PS
|
|
s32i a0, sp, XT_SOL_PC
|
|
s32i a2, sp, XT_SOL_PS
|
|
#if XCHAL_HAVE_THREADPTR
|
|
rur.threadptr a2
|
|
s32i a2, sp, XT_SOL_THREADPTR
|
|
#endif
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */
|
|
s32i a13, sp, XT_SOL_A13
|
|
s32i a14, sp, XT_SOL_A14
|
|
s32i a15, sp, XT_SOL_A15
|
|
#else
|
|
/* Spill register windows. Calling xthal_window_spill() causes extra */
|
|
/* spills and reloads, so we will set things up to call the _nw version */
|
|
/* instead to save cycles. */
|
|
movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */
|
|
and a2, a2, a6 /* clear WOE, INTLEVEL */
|
|
addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */
|
|
wsr a2, XT_REG_PS
|
|
rsync
|
|
call0 xthal_window_spill_nw
|
|
l32i a2, sp, XT_SOL_PS /* restore PS */
|
|
wsr a2, XT_REG_PS
|
|
#endif
|
|
|
|
rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */
|
|
|
|
#if XCHAL_CP_NUM > 0
|
|
/* Save coprocessor callee-saved state (if any). At this point CPENABLE */
|
|
/* should still reflect which CPs were in use (enabled). */
|
|
call0 _xt_coproc_savecs
|
|
#endif
|
|
|
|
movi a2, pxCurrentTCBs
|
|
getcoreid a3
|
|
addx4 a2, a3, a2
|
|
l32i a2, a2, 0 /* a2 = pxCurrentTCBs */
|
|
movi a3, 0
|
|
s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */
|
|
s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCBs->pxTopOfStack = SP */
|
|
|
|
#if XCHAL_CP_NUM > 0
|
|
/* Clear CPENABLE, also in task's co-processor state save area. */
|
|
get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */
|
|
movi a3, 0
|
|
wsr a3, XT_REG_CPENABLE
|
|
beqz a2, 1f
|
|
s16i a3, a2, XT_CPENABLE /* clear saved cpenable */
|
|
1:
|
|
#endif
|
|
|
|
/* Tail-call dispatcher. */
|
|
call0 _frxt_dispatch
|
|
/* Never reaches here. */
|
|
|
|
|
|
/*
|
|
**********************************************************************************************************
|
|
* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
|
|
* void vPortYieldFromInt(void)
|
|
*
|
|
* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
|
|
* _frxt_dispatch() to perform the actual context switch.
|
|
*
|
|
* At Entry:
|
|
* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCBs->pxTopOfStack.
|
|
* pxCurrentTCBs points to the TCB of the task to suspend,
|
|
* Callable from C (obeys ABI conventions on entry).
|
|
*
|
|
* At Exit:
|
|
* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
|
|
* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
|
|
*
|
|
**********************************************************************************************************
|
|
*/
|
|
.globl vPortYieldFromInt
|
|
.type vPortYieldFromInt,@function
|
|
.align 4
|
|
vPortYieldFromInt:
|
|
|
|
ENTRY(16)
|
|
|
|
#if XCHAL_CP_NUM > 0
|
|
/* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */
|
|
movi a2, pxCurrentTCBs /* cp_state = */
|
|
getcoreid a3
|
|
addx4 a2, a3, a2
|
|
l32i a2, a2, 0
|
|
|
|
get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */
|
|
|
|
rsr a3, XT_REG_CPENABLE
|
|
s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */
|
|
movi a3, 0
|
|
wsr a3, XT_REG_CPENABLE /* disable all co-processors */
|
|
#endif
|
|
|
|
#ifdef __XTENSA_CALL0_ABI__
|
|
/* Tail-call dispatcher. */
|
|
call0 _frxt_dispatch
|
|
/* Never reaches here. */
|
|
#else
|
|
RET(16)
|
|
#endif
|
|
|
|
/*
|
|
**********************************************************************************************************
|
|
* _frxt_task_coproc_state
|
|
* void _frxt_task_coproc_state(void)
|
|
*
|
|
* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
|
|
*
|
|
* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
|
|
* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
|
|
* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
|
|
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
|
|
*
|
|
**********************************************************************************************************
|
|
*/
|
|
#if XCHAL_CP_NUM > 0
|
|
|
|
.globl _frxt_task_coproc_state
|
|
.type _frxt_task_coproc_state,@function
|
|
.align 4
|
|
_frxt_task_coproc_state:
|
|
|
|
|
|
/* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */
|
|
getcoreid a3
|
|
movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */
|
|
addx4 a15, a3,a15
|
|
l32i a15, a15, 0
|
|
beqz a15, 1f
|
|
movi a15, port_interruptNesting /* && port_interruptNesting == 0 */
|
|
addx4 a15, a3, a15
|
|
l32i a15, a15, 0
|
|
bnez a15, 1f
|
|
|
|
movi a15, pxCurrentTCBs
|
|
addx4 a15, a3, a15
|
|
l32i a15, a15, 0 /* && pxCurrentTCBs != 0) { */
|
|
|
|
beqz a15, 2f
|
|
get_cpsa_from_tcb a15, a3 /* After this, pointer to CP save area is in a15, a3 is destroyed */
|
|
ret
|
|
|
|
1: movi a15, 0
|
|
2: ret
|
|
|
|
#endif /* XCHAL_CP_NUM > 0 */
|
|
|
|
/*
|
|
**********************************************************************************************************
|
|
* _frxt_coproc_exc_hook
|
|
* void _frxt_coproc_exc_hook(void)
|
|
*
|
|
* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_EXC_HOOK function for FreeRTOS.
|
|
*
|
|
* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
|
|
* May only only use a2-4, a15 (all other regs must be preserved).
|
|
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
|
|
*
|
|
**********************************************************************************************************
|
|
*/
|
|
#if XCHAL_CP_NUM > 0
|
|
|
|
.globl _frxt_coproc_exc_hook
|
|
.type _frxt_coproc_exc_hook,@function
|
|
.align 4
|
|
_frxt_coproc_exc_hook:
|
|
|
|
#if configNUM_CORES > 1
|
|
getcoreid a2 /* a2 = xCurCoreID */
|
|
/* if (port_xSchedulerRunning[xCurCoreID] == 0) */
|
|
movi a3, port_xSchedulerRunning
|
|
addx4 a3, a2, a3
|
|
l32i a3, a3, 0
|
|
beqz a3, 1f /* Scheduler hasn't started yet. Return. */
|
|
/* if (port_interruptNesting[xCurCoreID] != 0) */
|
|
movi a3, port_interruptNesting
|
|
addx4 a3, a2, a3
|
|
l32i a3, a3, 0
|
|
bnez a3, 1f /* We are in an interrupt. Return*/
|
|
/* CP operations are incompatible with unpinned tasks. Thus we pin the task
|
|
to the current running core. */
|
|
movi a3, pxCurrentTCBs
|
|
addx4 a3, a2, a3
|
|
l32i a3, a3, 0 /* a3 = pxCurrentTCBs[xCurCoreID] */
|
|
movi a4, offset_xCoreID
|
|
l32i a4, a4, 0 /* a4 = offset_xCoreID */
|
|
add a3, a3, a4 /* a3 = &TCB.xCoreID */
|
|
s32i a2, a3, 0 /* TCB.xCoreID = xCurCoreID */
|
|
1:
|
|
#endif /* configNUM_CORES > 1 */
|
|
|
|
ret
|
|
|
|
#endif /* XCHAL_CP_NUM > 0 */
|