morris cd1ce6164b Merge branch 'refactor/fine_tune_dphy_pll_v5.4' into 'release/v5.4' ...

feat(mipi): fine tune DPHY PLL clock (v5.4)

See merge request espressif/esp-idf!35291

2025-01-06 13:20:01 +08:00

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include/soc

fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL

2024-10-17 12:41:15 +08:00

private_include

fix(esp_hw_support): fix writeback cache to psram after vo2 powerdown

2024-11-04 14:08:28 +08:00

chip_info.c

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CMakeLists.txt

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cpu_region_protect.c

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esp_clk_tree.c

feat(mipi): fine tune DPHY PLL clock

2024-11-30 00:29:15 +08:00

esp_cpu_intr.c

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io_mux.c

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Kconfig.dcdc

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Kconfig.hw_support

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Kconfig.ldo

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Kconfig.mac

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Kconfig.rtc

fix(clk): add an inevitable kconfig option to be selected to use rc32k

2024-12-02 11:15:17 +08:00

Kconfig.xtal

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mspi_timing_config.c

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mspi_timing_tuning_configs.h

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pmu_init.c

feat(esp_hw_support): support power down PSRAM or Flash during sleep for esp32p4 v1.0

2024-10-23 19:10:42 +08:00

pmu_param.c

feat(esp_hw_support): support power down PSRAM or Flash during sleep for esp32p4 v1.0

2024-10-23 19:10:42 +08:00

pmu_sleep.c

fix(esp_hw_support): fix writeback cache to psram after vo2 powerdown

2024-11-04 14:08:28 +08:00

rtc_clk_init.c

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rtc_clk.c

fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL

2024-10-17 12:41:15 +08:00

rtc_time.c

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sar_periph_ctrl.c

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systimer.c

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