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4230acb971
This commit adds a new example which demonstrates how the ULP RISC-V co-processor handles interrupts.
11 lines
243 B
Plaintext
11 lines
243 B
Plaintext
menu "ULP RISC-V Interrupt Example Configuration"
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config EXAMPLE_GPIO_INT
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int "GPIO interrupt pin"
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range 0 21
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default 0
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help
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GPIO number to trigger an interrupt on the ULP RISC-V core.
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endmenu
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