mirror of
https://github.com/espressif/esp-idf.git
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114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_attr.h"
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#include "soc/cpu.h"
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#include "soc/soc.h"
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#include "soc/rtc_periph.h"
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#include "sdkconfig.h"
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#include "hal/cpu_hal.h"
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#include "esp_debug_helpers.h"
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#include "hal/cpu_types.h"
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#include "hal/mpu_hal.h"
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#include "hal/soc_hal.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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void IRAM_ATTR esp_cpu_stall(int cpu_id)
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{
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#if SOC_CPU_CORES_NUM > 1
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soc_hal_stall_core(cpu_id);
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#endif
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}
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void IRAM_ATTR esp_cpu_unstall(int cpu_id)
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{
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#if SOC_CPU_CORES_NUM > 1
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soc_hal_unstall_core(cpu_id);
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#endif
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}
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void IRAM_ATTR esp_cpu_reset(int cpu_id)
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{
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soc_hal_reset_core(cpu_id);
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}
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esp_err_t IRAM_ATTR esp_set_watchpoint(int no, void *adr, int size, int flags)
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{
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watchpoint_trigger_t trigger;
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switch (flags)
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{
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case ESP_WATCHPOINT_LOAD:
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trigger = WATCHPOINT_TRIGGER_ON_RO;
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break;
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case ESP_WATCHPOINT_STORE:
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trigger = WATCHPOINT_TRIGGER_ON_WO;
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break;
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case ESP_WATCHPOINT_ACCESS:
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trigger = WATCHPOINT_TRIGGER_ON_RW;
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break;
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default:
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return ESP_ERR_INVALID_ARG;
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}
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cpu_hal_set_watchpoint(no, adr, size, trigger);
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return ESP_OK;
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}
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void IRAM_ATTR esp_clear_watchpoint(int no)
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{
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cpu_hal_clear_watchpoint(no);
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}
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bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
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{
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#if CONFIG_ESP32_DEBUG_OCDAWARE || \
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CONFIG_ESP32S2_DEBUG_OCDAWARE || \
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CONFIG_ESP32S3_DEBUG_OCDAWARE || \
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CONFIG_ESP32C3_DEBUG_OCDAWARE
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return cpu_ll_is_debugger_attached();
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#else
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return false; // Always return false if "OCD aware" is disabled
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#endif
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}
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void IRAM_ATTR esp_set_breakpoint_if_jtag(void *fn)
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{
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if (esp_cpu_in_ocd_debug_mode()) {
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cpu_hal_set_breakpoint(0, fn);
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}
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}
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#if __XTENSA__
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void esp_cpu_configure_region_protection(void)
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{
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/* Note: currently this is configured the same on all Xtensa targets
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*
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* Both chips have the address space divided into 8 regions, 512MB each.
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*/
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const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
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for (size_t i = 0; i < sizeof(illegal_regions) / sizeof(illegal_regions[0]); ++i) {
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mpu_hal_set_region_access(illegal_regions[i], MPU_REGION_ILLEGAL);
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}
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mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
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}
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#endif
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