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https://github.com/espressif/esp-idf.git
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232 lines
8.0 KiB
C
232 lines
8.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/dport_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief enable a cache unit
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_enable_cache(uint32_t cache_id)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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if (cache_id == 0) {
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DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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} else {
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
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}
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}
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/**
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* @brief disable a cache unit
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_cache(uint32_t cache_id)
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{
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if (cache_id == 0) {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1){
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;
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}
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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} else {
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while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1){
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;
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}
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
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}
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}
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/**
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* @brief Get the status of cache if it is enabled or not
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param type see `cache_type_t`
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* @return enabled or not
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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(void) type; //On 32 it shares between I and D cache
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bool enabled;
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if (cache_id == 0) {
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enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
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} else {
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enabled = DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
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}
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return enabled;
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}
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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cache_bus_mask_t mask = 0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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if (vaddr_start >= IROM0_CACHE_ADDRESS_HIGH) {
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HAL_ASSERT(false); //out of range
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} else if (vaddr_start >= IROM0_CACHE_ADDRESS_LOW) {
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mask |= CACHE_BUS_IBUS2;
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} else if (vaddr_start >= IRAM1_CACHE_ADDRESS_LOW) {
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mask |= CACHE_BUS_IBUS1;
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mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
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} else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
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mask |= CACHE_BUS_IBUS0;
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mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
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mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
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} else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) {
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HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
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mask |= CACHE_BUS_DBUS1;
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} else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) {
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HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
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mask |= CACHE_BUS_DBUS0;
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} else {
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HAL_ASSERT(false);
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}
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return mask;
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}
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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/**
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* Returns enabled buses for a given core
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return State of enabled buses
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*/
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__attribute__((always_inline))
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static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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{
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cache_bus_mask_t mask = 0;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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if (cache_id == 0) {
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uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG);
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
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} else {
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uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
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}
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return mask;
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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