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https://github.com/espressif/esp-idf.git
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5b2e8f2b38
This change addresses a rare but critical issue observed on certain ESP32-C3 and ESP32-S3 devices, where secure boot verification intermittently fails due to improper cleanup of crypto peripherals during a restart. Background – Restart Behavior in IDF ------------------------------------ In ESP-IDF, when the device restarts (via `esp_restart()` or due to a panic/exception), a partial peripheral reset is performed followed by a CPU reset. However, until now, crypto-related peripherals were not included in this selective reset sequence. Problem Scenario ---------------- If a restart occurs while the application is in the middle of a bignum operation (i.e., using the MPI/Bignum peripheral), the ROM code may encounter an inconsistent peripheral state during the subsequent boot. This leads to transient RSA-PSS secure boot verification failures. Following such a failure, the ROM typically triggers a full-chip reset via the watchdog timer (WDT). This full reset clears the crypto peripheral state, allowing secure boot verification to succeed on the next boot. Risk with Aggressive Revocation ------------------------------- If secure boot aggressive revocation is enabled (disabled by default in IDF), this transient verification failure could mistakenly lead to revocation of the secure boot digest. If your product configuration has aggressive revocation enabled, applying this fix is strongly recommended. Frequency of Occurrence ----------------------- The issue is rare and only occurs in corner cases involving simultaneous use of the MPI peripheral and an immediate CPU reset. Fix --- This fix ensures that all crypto peripherals are explicitly reset prior to any software-triggered restart (including panic scenarios), guaranteeing a clean peripheral state for the next boot and preventing incorrect secure boot behavior.
165 lines
6.3 KiB
C
165 lines
6.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_system.h"
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#include "esp_private/system_internal.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "riscv/rv_utils.h"
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#include "esp_rom_uart.h"
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#include "soc/soc_caps.h"
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#include "soc/gpio_reg.h"
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#include "esp_cpu.h"
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#include "soc/rtc.h"
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#include "esp_private/rtc_clk.h"
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#include "soc/rtc_periph.h"
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#include "soc/uart_reg.h"
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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#include "hal/clk_tree_ll.h"
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#endif
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#include "hal/wdt_hal.h"
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#if SOC_MODEM_CLOCK_SUPPORTED
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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#endif
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#include "esp_private/cache_err_int.h"
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#include "esp32c5/rom/cache.h"
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#include "esp32c5/rom/rtc.h"
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#include "soc/pcr_reg.h"
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void IRAM_ATTR esp_system_reset_modules_on_exit(void)
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{
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// Flush any data left in UART FIFOs before reset the UART peripheral
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esp_rom_output_tx_wait_idle(0);
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esp_rom_output_tx_wait_idle(1);
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// TODO: IDF-8845
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#if SOC_MODEM_CLOCK_SUPPORTED
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modem_syscon_ll_reset_all(&MODEM_SYSCON);
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modem_lpcon_ll_reset_all(&MODEM_LPCON);
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#endif
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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// Set SPI Flash Freq to 40M
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clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
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clk_ll_mspi_fast_set_divider(1);
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// Set Peripheral clk rst
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SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
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#endif
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// Set Peripheral clk rst
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SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
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SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
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SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
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SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
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SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
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SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
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SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
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// Clear Peripheral clk rst
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CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
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#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
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SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
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#endif
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// Clear Peripheral clk rst
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CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
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#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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// CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
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#endif
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CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
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// Reset crypto peripherals. This ensures a clean state for the crypto peripherals after a CPU restart
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// and hence avoiding any possibility with crypto failure in ROM security workflows.
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SET_PERI_REG_MASK(PCR_AES_CONF_REG, PCR_AES_RST_EN);
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SET_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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SET_PERI_REG_MASK(PCR_ECC_CONF_REG, PCR_ECC_RST_EN);
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SET_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN);
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SET_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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SET_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_AES_CONF_REG, PCR_AES_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_ECC_CONF_REG, PCR_ECC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_ECDSA_CONF_REG, PCR_ECDSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
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CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
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}
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/* "inner" restart function for after RTOS, interrupts & anything else on this
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* core are already stopped. Stalls other core, resets hardware,
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* triggers restart.
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*/
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void IRAM_ATTR esp_restart_noos(void)
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{
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// Disable interrupts
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rv_utils_intr_global_disable();
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// Enable RTC watchdog for 1 second
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wdt_hal_context_t rtc_wdt_ctx;
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
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uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
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wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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// C5 is a single core SoC, no need to reset and stall the other CPU
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// Disable TG0/TG1 watchdogs
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wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
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wdt_hal_write_protect_disable(&wdt0_context);
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wdt_hal_disable(&wdt0_context);
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wdt_hal_write_protect_enable(&wdt0_context);
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wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
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wdt_hal_write_protect_disable(&wdt1_context);
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wdt_hal_disable(&wdt1_context);
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wdt_hal_write_protect_enable(&wdt1_context);
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// Disable cache
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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Cache_Disable_ICache();
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#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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Cache_Disable_Cache();
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#endif
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// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
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// Moved to module internal
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// SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
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// SYSTEM_SDIO_RST | // SDIO_HINF_HINF_SDIO_RST?
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// SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet)
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// REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
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esp_system_reset_modules_on_exit();
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// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
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#if !CONFIG_IDF_ENV_FPGA
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rtc_clk_cpu_set_to_default_config();
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#endif
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// Reset PRO CPU
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esp_rom_software_reset_cpu(0);
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while (true) {
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;
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}
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}
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