mirror of
https://github.com/espressif/esp-idf.git
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275 lines
8.6 KiB
C
275 lines
8.6 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** PAU_REGDMA_CONF_REG register
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* Peri backup control register
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*/
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#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
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/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
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* backup error type
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*/
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#define PAU_FLOW_ERR 0x00000007U
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#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
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#define PAU_FLOW_ERR_V 0x00000007U
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#define PAU_FLOW_ERR_S 0
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/** PAU_START : WT; bitpos: [3]; default: 0;
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* backup start signal
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*/
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#define PAU_START (BIT(3))
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#define PAU_START_M (PAU_START_V << PAU_START_S)
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#define PAU_START_V 0x00000001U
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#define PAU_START_S 3
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/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
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* backup direction(reg to mem / mem to reg)
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*/
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#define PAU_TO_MEM (BIT(4))
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#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
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#define PAU_TO_MEM_V 0x00000001U
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#define PAU_TO_MEM_S 4
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/** PAU_LINK_SEL : R/W; bitpos: [8:5]; default: 0;
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* Link select
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*/
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#define PAU_LINK_SEL 0x0000000FU
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#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
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#define PAU_LINK_SEL_V 0x0000000FU
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#define PAU_LINK_SEL_S 5
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/** PAU_START_MAC : WT; bitpos: [9]; default: 0;
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* mac sw backup start signal
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*/
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#define PAU_START_MAC (BIT(9))
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#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
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#define PAU_START_MAC_V 0x00000001U
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#define PAU_START_MAC_S 9
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/** PAU_TO_MEM_MAC : R/W; bitpos: [10]; default: 0;
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* mac sw backup direction(reg to mem / mem to reg)
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*/
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#define PAU_TO_MEM_MAC (BIT(10))
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#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
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#define PAU_TO_MEM_MAC_V 0x00000001U
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#define PAU_TO_MEM_MAC_S 10
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/** PAU_SEL_MAC : R/W; bitpos: [11]; default: 0;
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* mac hw/sw select
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*/
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#define PAU_SEL_MAC (BIT(11))
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#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
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#define PAU_SEL_MAC_V 0x00000001U
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#define PAU_SEL_MAC_S 11
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/** PAU_REGDMA_CLK_CONF_REG register
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* Clock control register
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*/
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#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
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/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
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* clock enable
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*/
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#define PAU_CLK_EN (BIT(0))
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#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
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#define PAU_CLK_EN_V 0x00000001U
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#define PAU_CLK_EN_S 0
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/** PAU_REGDMA_ETM_CTRL_REG register
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* ETM start ctrl reg
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*/
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#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
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/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
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* etm_start_0 reg
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*/
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#define PAU_ETM_START_0 (BIT(0))
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#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
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#define PAU_ETM_START_0_V 0x00000001U
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#define PAU_ETM_START_0_S 0
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/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
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* etm_start_1 reg
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*/
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#define PAU_ETM_START_1 (BIT(1))
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#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
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#define PAU_ETM_START_1_V 0x00000001U
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#define PAU_ETM_START_1_S 1
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/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
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* etm_start_2 reg
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*/
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#define PAU_ETM_START_2 (BIT(2))
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#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
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#define PAU_ETM_START_2_V 0x00000001U
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#define PAU_ETM_START_2_S 2
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/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
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* etm_start_3 reg
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*/
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#define PAU_ETM_START_3 (BIT(3))
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#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
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#define PAU_ETM_START_3_V 0x00000001U
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#define PAU_ETM_START_3_S 3
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/** PAU_ETM_LINK_SEL_0 : R/W; bitpos: [7:4]; default: 0;
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* etm_link sel
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*/
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#define PAU_ETM_LINK_SEL_0 0x0000000FU
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#define PAU_ETM_LINK_SEL_0_M (PAU_ETM_LINK_SEL_0_V << PAU_ETM_LINK_SEL_0_S)
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#define PAU_ETM_LINK_SEL_0_V 0x0000000FU
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#define PAU_ETM_LINK_SEL_0_S 4
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/** PAU_ETM_LINK_SEL_1 : R/W; bitpos: [11:8]; default: 0;
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* etm_link sel
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*/
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#define PAU_ETM_LINK_SEL_1 0x0000000FU
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#define PAU_ETM_LINK_SEL_1_M (PAU_ETM_LINK_SEL_1_V << PAU_ETM_LINK_SEL_1_S)
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#define PAU_ETM_LINK_SEL_1_V 0x0000000FU
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#define PAU_ETM_LINK_SEL_1_S 8
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/** PAU_ETM_LINK_SEL_2 : R/W; bitpos: [15:12]; default: 0;
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* etm_link sel
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*/
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#define PAU_ETM_LINK_SEL_2 0x0000000FU
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#define PAU_ETM_LINK_SEL_2_M (PAU_ETM_LINK_SEL_2_V << PAU_ETM_LINK_SEL_2_S)
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#define PAU_ETM_LINK_SEL_2_V 0x0000000FU
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#define PAU_ETM_LINK_SEL_2_S 12
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/** PAU_ETM_LINK_SEL_3 : R/W; bitpos: [19:16]; default: 0;
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* etm_link sel
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*/
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#define PAU_ETM_LINK_SEL_3 0x0000000FU
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#define PAU_ETM_LINK_SEL_3_M (PAU_ETM_LINK_SEL_3_V << PAU_ETM_LINK_SEL_3_S)
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#define PAU_ETM_LINK_SEL_3_V 0x0000000FU
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#define PAU_ETM_LINK_SEL_3_S 16
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/** PAU_ETM_BUSY_CAUSE : RO; bitpos: [23:20]; default: 0;
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* debug
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*/
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#define PAU_ETM_BUSY_CAUSE 0x0000000FU
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#define PAU_ETM_BUSY_CAUSE_M (PAU_ETM_BUSY_CAUSE_V << PAU_ETM_BUSY_CAUSE_S)
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#define PAU_ETM_BUSY_CAUSE_V 0x0000000FU
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#define PAU_ETM_BUSY_CAUSE_S 20
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/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
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* current link addr
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*/
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#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0xc)
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/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
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* current link addr reg
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*/
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#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
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#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
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#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU
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#define PAU_CURRENT_LINK_ADDR_S 0
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/** PAU_REGDMA_PERI_ADDR_REG register
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* Backup addr
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*/
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#define PAU_REGDMA_PERI_ADDR_REG (DR_REG_PAU_BASE + 0x10)
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/** PAU_PERI_ADDR : RO; bitpos: [31:0]; default: 0;
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* peri addr reg
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*/
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#define PAU_PERI_ADDR 0xFFFFFFFFU
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#define PAU_PERI_ADDR_M (PAU_PERI_ADDR_V << PAU_PERI_ADDR_S)
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#define PAU_PERI_ADDR_V 0xFFFFFFFFU
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#define PAU_PERI_ADDR_S 0
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/** PAU_REGDMA_MEM_ADDR_REG register
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* mem addr
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*/
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#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x14)
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/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
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* mem addr reg
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*/
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#define PAU_MEM_ADDR 0xFFFFFFFFU
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#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
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#define PAU_MEM_ADDR_V 0xFFFFFFFFU
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#define PAU_MEM_ADDR_S 0
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/** PAU_INT_ENA_REG register
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* Read only register for error and done
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*/
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#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x18)
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/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* backup done flag
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*/
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#define PAU_DONE_INT_ENA (BIT(0))
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#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
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#define PAU_DONE_INT_ENA_V 0x00000001U
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#define PAU_DONE_INT_ENA_S 0
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/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
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* error flag
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*/
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#define PAU_ERROR_INT_ENA (BIT(1))
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#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
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#define PAU_ERROR_INT_ENA_V 0x00000001U
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#define PAU_ERROR_INT_ENA_S 1
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/** PAU_INT_RAW_REG register
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* Read only register for error and done
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*/
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#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x1c)
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/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
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* backup done flag
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*/
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#define PAU_DONE_INT_RAW (BIT(0))
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#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
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#define PAU_DONE_INT_RAW_V 0x00000001U
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#define PAU_DONE_INT_RAW_S 0
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/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
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* error flag
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*/
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#define PAU_ERROR_INT_RAW (BIT(1))
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#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
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#define PAU_ERROR_INT_RAW_V 0x00000001U
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#define PAU_ERROR_INT_RAW_S 1
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/** PAU_INT_CLR_REG register
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* Read only register for error and done
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*/
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#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x20)
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/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* backup done flag
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*/
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#define PAU_DONE_INT_CLR (BIT(0))
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#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
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#define PAU_DONE_INT_CLR_V 0x00000001U
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#define PAU_DONE_INT_CLR_S 0
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/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
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* error flag
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*/
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#define PAU_ERROR_INT_CLR (BIT(1))
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#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
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#define PAU_ERROR_INT_CLR_V 0x00000001U
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#define PAU_ERROR_INT_CLR_S 1
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/** PAU_INT_ST_REG register
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* Read only register for error and done
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*/
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#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x24)
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/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* backup done flag
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*/
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#define PAU_DONE_INT_ST (BIT(0))
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#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
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#define PAU_DONE_INT_ST_V 0x00000001U
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#define PAU_DONE_INT_ST_S 0
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/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
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* error flag
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*/
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#define PAU_ERROR_INT_ST (BIT(1))
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#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
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#define PAU_ERROR_INT_ST_V 0x00000001U
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#define PAU_ERROR_INT_ST_S 1
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/** PAU_DATE_REG register
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* Date register.
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*/
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#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
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/** PAU_DATE : R/W; bitpos: [27:0]; default: 36737360;
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* REGDMA date information/ REGDMA version information.
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*/
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#define PAU_DATE 0x0FFFFFFFU
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#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
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#define PAU_DATE_V 0x0FFFFFFFU
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#define PAU_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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