cjin e44f1373a0 feat(ble): add sm count reserve cnt setting on ESP32-H2

2025-06-26 14:54:53 +08:00

..

esp32

refactor(xtensa): Rename specreg.h register macros

2025-06-17 15:37:33 +02:00

esp32c2

fix(ble): change the default ble cca thresh on ESP32-C2

2025-06-06 17:57:35 +08:00

esp32c3

feat(ble/controller): Reduce bin size and IRAM for BLE rom code

2025-05-21 10:22:37 +08:00

esp32c5

feat(ble): add sm count reserve cnt setting on ESP32-C5

2025-06-26 14:54:53 +08:00

esp32c6

feat(ble): add sm count reserve cnt setting on ESP32-C6 and ESP32-C61

2025-06-26 14:54:53 +08:00

esp32c61

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esp32h2

feat(ble): add sm count reserve cnt setting on ESP32-H2

2025-06-26 14:54:53 +08:00

esp32h4

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esp32h21

…

esp32p4

…

esp32s2

…

esp32s3

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lib_esp32 @ b0ebfcf639

fix(bt/controller): Fixed bugs on LMP legacy and secure authentication collision

2025-06-19 20:30:35 +08:00

lib_esp32c2

change(ble): [AUTO_MR] Update lib_esp32c2 to e865b4f9

2025-06-25 18:11:18 +08:00

lib_esp32c3_family @ 3ff529142f

fix(bt): Update bt lib for ESP32-C3 and ESP32-S3(4713a69)

2025-06-05 11:10:25 +08:00

lib_esp32c5

change(ble): update lib_esp32c5 to ea6c58c7

2025-06-25 18:11:18 +08:00

lib_esp32c6

change(ble): update lib_esp32c6 and esp32c61 to ea6c58c7

2025-06-25 18:11:18 +08:00

lib_esp32h2

change(ble): update lib_esp32h2 to ea6c58c7

2025-06-25 18:11:18 +08:00