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https://github.com/espressif/esp-idf.git
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157 lines
6.1 KiB
Plaintext
157 lines
6.1 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* ESP32-P4 Linker Script Memory Layout
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* This file describes the memory layout (memory blocks) by virtual memory addresses.
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* This linker script is passed through the C preprocessor to include configuration options.
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* Please use preprocessor features sparingly!
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* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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#include "ld.common"
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#define SRAM_LOW_START 0x4FF00000
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#define SRAM_LOW_END 0x4FF2CBD0 /* 2nd stage bootloader iram_loader_seg start address */
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#define SRAM_LOW_SIZE SRAM_LOW_END - SRAM_LOW_START
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/* If the cache size is less than 512KB, then there is a region of RAM
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* above the ROM-reserved region and below the start of the cache.
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*/
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#define SRAM_HIGH_START 0x4FF40000
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#define SRAM_HIGH_SIZE 0x80000 - CONFIG_CACHE_L2_CACHE_SIZE
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#define SRAM_HIGH_END SRAM_HIGH_START + SRAM_HIGH_SIZE
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#define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 10)
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#define LP_ROM_DRAM_START 0x5010fa80 // Value taken from ROM elf, includes LP ROM stack
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#define LP_RAM_END 0x50110000
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#define LP_ROM_DRAM_SIZE (LP_RAM_END - LP_ROM_DRAM_START)
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MEMORY
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{
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/**
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* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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* are connected to the data port of the CPU and eg allow byte-wise access.
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*/
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/* TCM */
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tcm_idram_seg (RX) : org = 0x30100000, len = 0x2000
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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/* PSRAM mapped instruction data */
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irom_seg (RX) : org = 0x48000020, len = IDROM_SEG_SIZE - 0x20
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#else
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/* Flash mapped instruction data */
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irom_seg (RX) : org = 0x40000020, len = IDROM_SEG_SIZE - 0x20
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/**
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* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
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*/
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sram_low (RWX) : org = SRAM_LOW_START, len = SRAM_LOW_SIZE
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sram_high (RW) : org = SRAM_HIGH_START, len = SRAM_HIGH_SIZE
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_RODATA
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/* PSRAM mapped constant data */
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drom_seg (R) : org = 0x48000020, len = IDROM_SEG_SIZE - 0x20
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#else
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/* Flash mapped constant data */
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drom_seg (R) : org = 0x40000020, len = IDROM_SEG_SIZE - 0x20
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#endif // CONFIG_SPIRAM_RODATA
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/* (See irom_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
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*/
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#if CONFIG_ULP_COPROC_ENABLED
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lp_ram_seg(RW) : org = 0x50108000 + RESERVE_RTC_MEM + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x8000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM - LP_ROM_DRAM_SIZE
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#else
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lp_ram_seg(RW) : org = 0x50108000 + RESERVE_RTC_MEM, len = 0x8000 - RESERVE_RTC_MEM
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#endif // CONFIG_ULP_COPROC_ENABLED
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/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
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It reserves the amount of LP memory that we use for this memory segment.
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This segment is intended for keeping:
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- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
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The aim of this is to keep data that will not be moved around and have a fixed address.
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This segment is placed at the beginning of LP RAM, as the end of LP RAM is occupied by LP ROM stack/data
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*/
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lp_reserved_seg(RW) : org = 0x50108000, len = RESERVE_RTC_MEM
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/* PSRAM seg */
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extern_ram_seg(RWX) : org = 0x48000000, len = IDROM_SEG_SIZE
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}
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x50000000;
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_data_seg_org = ORIGIN(rtc_data_seg);
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/**
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* The lines below define location alias for .rtc.data section
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* P4 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
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* Thus, the following region segments are not configurable like on other targets
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*/
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REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
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REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
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REGION_ALIAS("rtc_data_location", rtc_iram_seg );
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REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("text_seg_low", irom_seg);
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#else
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REGION_ALIAS("text_seg_low", sram_low);
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REGION_ALIAS("text_seg_high", sram_high);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("rodata_seg_low", drom_seg);
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#else
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REGION_ALIAS("rodata_seg_low", sram_low);
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REGION_ALIAS("rodata_seg_high", sram_high);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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REGION_ALIAS("ext_ram_seg", drom_seg);
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#else
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REGION_ALIAS("ext_ram_seg", extern_ram_seg);
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#endif //#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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/**
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* If rodata default segment is placed in `drom_seg`, then flash's first rodata section must
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* also be first in the segment.
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*/
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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ASSERT(_flash_rodata_dummy_start == ORIGIN(rodata_seg_low),
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".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
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#endif
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#if CONFIG_ESP_SYSTEM_USE_EH_FRAME
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ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
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ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
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#endif
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