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https://github.com/espressif/esp-idf.git
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e8de5b5a95
- Remove GPTIMER and TIMG related definitions from soc_caps_full.h files - Move timer peripheral definitions to appropriate HAL layer files - Update references across components to use proper HAL abstractions - Consolidate timer group and GPTIMER capabilities organization - Ensure consistent timer configuration across all ESP32 variants This refactoring improves the separation of concerns between SOC capabilities and HAL implementations for timer-related functionality.
347 lines
11 KiB
C
347 lines
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "hal/timer_types.h"
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#include "hal/timg_ll.h"
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#include "soc/timer_group_struct.h"
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#include "soc/pcr_struct.h"
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#include "soc/soc_etm_source.h"
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// Get timer group register base address with giving group number
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// Total number of general purpose timers
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#define TIMER_LL_GPTIMERS_TOTAL (TIMG_LL_INST_NUM * TIMG_LL_GPTIMERS_PER_INST)
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#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
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// Bit width of GPTIMER counter
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#define TIMER_LL_COUNTER_BIT_WIDTH 54
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// Get alarm interrupt mask with the given timer ID
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#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
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// Support RC_FAST as function clock
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#define TIMER_LL_FUNC_CLOCK_SUPPORT_RC_FAST 1
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \
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(uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \
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[GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \
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[GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER0, \
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[GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER0, \
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[GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER0, \
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[GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER0, \
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}}, \
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{{ \
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[GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER0, \
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[GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER0, \
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[GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER0, \
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[GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER0, \
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[GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER0, \
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}}, \
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}[group][timer][task]
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#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event) \
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(uint32_t [2][1][GPTIMER_ETM_EVENT_MAX]){{{ \
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[GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER0, \
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}}, \
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{{ \
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[GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER0, \
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}}, \
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}[group][timer][event]
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/**
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* @brief Set clock source for timer
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*
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* @param group_id Group ID
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* @param timer_num Timer number in the group
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* @param clk_src Clock source
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*/
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static inline void timer_ll_set_clock_source(int group_id, uint32_t timer_num, gptimer_clock_source_t clk_src)
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{
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(void)timer_num; // only one timer in each group
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uint8_t clk_id = 0;
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switch (clk_src) {
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case GPTIMER_CLK_SRC_XTAL:
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clk_id = 0;
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break;
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case GPTIMER_CLK_SRC_RC_FAST:
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clk_id = 1;
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break;
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case GPTIMER_CLK_SRC_PLL_F48M:
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clk_id = 2;
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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if (group_id == 0) {
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PCR.timergroup0_timer_clk_conf.tg0_timer_clk_sel = clk_id;
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} else {
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PCR.timergroup1_timer_clk_conf.tg1_timer_clk_sel = clk_id;
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}
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}
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/**
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* @brief Enable Timer Group (GPTimer) module clock
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*
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* @param group_id Group ID
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* @param timer_num Timer index in the group
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* @param en true to enable, false to disable
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*/
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static inline void timer_ll_enable_clock(int group_id, uint32_t timer_num, bool en)
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{
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(void)timer_num; // only one timer in each group
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if (group_id == 0) {
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PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = en;
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} else {
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PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = en;
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}
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}
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/**
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* @brief Enable alarm event
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable alarm
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* False: disable alarm
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_alarm_en = en;
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}
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/**
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* @brief Set clock prescale for timer
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param divider Prescale value (0 and 1 are not valid)
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*/
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static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
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{
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HAL_ASSERT(divider >= 2 && divider <= 65536);
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if (divider >= 65536) {
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divider = 0;
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}
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
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hw->hw_timer[timer_num].config.tx_divcnt_rst = 1;
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}
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/**
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* @brief Enable auto-reload mode
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable auto reload mode
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* False: disable auto reload mode
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_autoreload = en;
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}
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/**
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* @brief Set count direction
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*
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* @param hw Timer peripheral register base address
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* @param timer_num Timer number in the group
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* @param direction Count direction
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*/
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static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
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{
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hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP);
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}
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/**
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* @brief Enable timer, start counting
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param en True: enable the counter
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* False: disable the counter
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
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{
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hw->hw_timer[timer_num].config.tx_en = en;
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}
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/**
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* @brief Trigger software capture event
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*/
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__attribute__((always_inline))
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static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].update.tx_update = 1;
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// Timer register is in a different clock domain from Timer hardware logic
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// We need to wait for the update to take effect before fetching the count value
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while (hw->hw_timer[timer_num].update.tx_update) {
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}
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}
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/**
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* @brief Get counter value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*
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* @return counter value
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*/
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__attribute__((always_inline))
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static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
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{
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return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
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}
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/**
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* @brief Set alarm value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param alarm_value When counter reaches alarm value, alarm event will be triggered
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*/
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__attribute__((always_inline))
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static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
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{
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hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32);
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hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value;
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}
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/**
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* @brief Set reload value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @param reload_val Reload counter value
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*/
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__attribute__((always_inline))
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static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val)
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{
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hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32);
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hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val;
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}
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/**
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* @brief Get reload value
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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* @return reload count value
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*/
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__attribute__((always_inline))
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static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
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{
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return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
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}
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/**
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* @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
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*
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* @param hw Timer Group register base address
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* @param timer_num Timer number in the group
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*/
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__attribute__((always_inline))
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static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
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{
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hw->hw_timer[timer_num].load.tx_load = 1;
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}
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/**
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* @brief Enable ETM module
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*
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* @param hw Timer Group register base address
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* @param en True: enable ETM module, False: disable ETM module
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*/
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static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en)
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{
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hw->regclk.etm_en = en;
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}
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/**
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* @brief Enable timer interrupt by mask
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*
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* @param hw Timer Group register base address
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* @param mask Mask of interrupt events
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* @param en True: enable interrupt
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* False: disable interrupt
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*/
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__attribute__((always_inline))
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static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
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{
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if (en) {
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hw->int_ena_timers.val |= mask;
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} else {
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hw->int_ena_timers.val &= ~mask;
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}
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}
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/**
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* @brief Get interrupt status
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*
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* @param hw Timer Group register base address
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*
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* @return Interrupt status
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*/
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__attribute__((always_inline))
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static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
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{
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return hw->int_st_timers.val & 0x01;
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}
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/**
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* @brief Clear interrupt status by mask
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*
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* @param hw Timer Group register base address
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* @param mask Interrupt events mask
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*/
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__attribute__((always_inline))
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static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
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{
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hw->int_clr_timers.val = mask;
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}
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/**
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* @brief Enable the register clock forever
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*
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* @param hw Timer Group register base address
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* @param en True: Enable the register clock forever
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* False: Register clock is enabled only when register operation happens
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*/
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static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
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{
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hw->regclk.clk_en = en;
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}
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/**
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* @brief Get interrupt status register address
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*
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* @param hw Timer Group register base address
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*
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* @return Interrupt status register address
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*/
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static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
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{
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return &hw->int_st_timers;
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}
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#ifdef __cplusplus
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}
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#endif
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