songruojing b3d8db3ae2 bootloader, esp_system: esp32c2 console uart to support 26MHz xtal ...

Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h

2022-07-11 12:24:58 +08:00

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adc_channel.h

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apb_saradc_reg.h

esp32c2: Add support for RNG

2022-06-02 11:36:23 +08:00

apb_saradc_struct.h

temperature_sensor: Add temperature sensor support for ESP32-C2

2022-06-23 15:36:43 +08:00

assist_debug_reg.h

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bb_reg.h

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boot_mode.h

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clk_tree_defs.h

rtc: esp32c2 support 26MHz xtal in startup code and rtc_clk.c

2022-07-11 12:24:58 +08:00

clkout_channel.h

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dport_access.h

dport: Move DPORT workaround to G0

2022-05-31 13:44:18 +08:00

dport_reg.h

dport: Move DPORT workaround to G0

2022-05-31 13:44:18 +08:00

ecc_mult_reg.h

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efuse_reg.h

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efuse_struct.h

efuse: Adds major and minor versions and others

2022-07-05 14:38:27 +08:00

ext_mem_defs.h

ext_mem: make memory region check strict

2022-06-28 14:17:44 +08:00

extmem_reg.h

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fe_reg.h

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gdma_channel.h

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gdma_reg.h

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gdma_struct.h

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gpio_pins.h

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gpio_reg.h

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gpio_sig_map.h

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gpio_struct.h

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hwcrypto_reg.h

hal(ecp32c2): Adds spi_flash_encrypted_ll

2022-05-31 11:12:21 +00:00

i2c_reg.h

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i2c_struct.h

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interrupt_core0_reg.h

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interrupt_reg.h

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io_mux_reg.h

clk_tree: Refactor rtc_clk.c by adding HAL layer for clock subsystem

2022-06-13 17:47:50 +08:00

Kconfig.soc_caps.in

esp_timer, hal: add support for non-integer systimer frequency

2022-07-11 12:24:37 +08:00

ledc_reg.h

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ledc_struct.h

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mmu.h

soc: remove unused MMU related macros

2022-05-20 16:46:28 +08:00

modem_clkrst_reg.h

Fix soc caps for BT

2022-06-03 21:45:40 +08:00

nrx_reg.h

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periph_defs.h

temperature_sensor: Add temperature sensor support for ESP32-C2

2022-06-23 15:36:43 +08:00

reg_base.h

Fix soc caps for BT

2022-06-03 21:45:40 +08:00

regi2c_bbpll.h

Refactor: move regi2c_*.h header files from esp_hw_support to soc component

2022-06-30 09:40:44 +00:00

regi2c_bias.h

Refactor: move regi2c_*.h header files from esp_hw_support to soc component

2022-06-30 09:40:44 +00:00

regi2c_brownout.h

G0: RISC-V targets have now an independent G0 layer

2022-06-14 15:00:53 +08:00

regi2c_defs.h

C2 rtc code

2022-05-09 17:50:54 +08:00

regi2c_dig_reg.h

Refactor: move regi2c_*.h header files from esp_hw_support to soc component

2022-06-30 09:40:44 +00:00

regi2c_lp_bias.h

Refactor: move regi2c_*.h header files from esp_hw_support to soc component

2022-06-30 09:40:44 +00:00

regi2c_saradc.h

G0: RISC-V targets have now an independent G0 layer

2022-06-14 15:00:53 +08:00

reset_reasons.h

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rtc_cntl_reg.h

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rtc_cntl_struct.h

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rtc.h

support c2 26M/32M xtal for bbpll

2022-07-05 17:45:03 +08:00

sensitive_reg.h

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sensitive_struct.h

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soc_caps.h

esp_timer, hal: add support for non-integer systimer frequency

2022-07-11 12:24:37 +08:00

soc_pins.h

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soc.h

bootloader, esp_system: esp32c2 console uart to support 26MHz xtal

2022-07-11 12:24:58 +08:00

spi_mem_reg.h

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spi_mem_struct.h

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spi_pins.h

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spi_reg.h

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spi_struct.h

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syscon_reg.h

Fix soc caps for BT

2022-06-03 21:45:40 +08:00

syscon_struct.h

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system_reg.h

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system_struct.h

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systimer_reg.h

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systimer_struct.h

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timer_group_reg.h

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timer_group_struct.h

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uart_channel.h

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uart_pins.h

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uart_reg.h

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uart_struct.h

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wdev_reg.h

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