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b71a6ce55a
Disable peripheral powerdown lightsleep if PSRAM if enabled on P4 v3 Force powerdown Flash if peripheral power down lightsleep is enabled
243 lines
14 KiB
Plaintext
243 lines
14 KiB
Plaintext
menu "Power Management"
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config PM_SLEEP_FUNC_IN_IRAM
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bool "Place Power Management module functions in IRAM" if IDF_TARGET_ESP32C2
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default y
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select PM_SLP_IRAM_OPT if SOC_LIGHT_SLEEP_SUPPORTED
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select PM_RTOS_IDLE_OPT if FREERTOS_USE_TICKLESS_IDLE
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select ESP_PERIPH_CTRL_FUNC_IN_IRAM
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select ESP_REGI2C_CTRL_FUNC_IN_IRAM
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config PM_ENABLE
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bool "Support for power management"
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# SMP FreeRTOS currently does not support power management IDF-4997
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depends on (!FREERTOS_SMP && SOC_PM_SUPPORTED) || __DOXYGEN__
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default n
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help
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If enabled, application is compiled with support for power management.
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This option has run-time overhead (increased interrupt latency,
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longer time to enter idle state), and it also reduces accuracy of
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RTOS ticks and timers used for timekeeping.
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Enable this option if application uses power management APIs.
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config PM_DFS_INIT_AUTO
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bool "Enable dynamic frequency scaling (DFS) at startup"
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depends on PM_ENABLE
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default n
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help
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If enabled, startup code configures dynamic frequency scaling.
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Max CPU frequency is set to DEFAULT_CPU_FREQ_MHZ setting,
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min frequency is set to XTAL frequency.
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If disabled, DFS will not be active until the application
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configures it using esp_pm_configure function.
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config PM_PROFILING
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bool "Enable profiling counters for PM locks"
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depends on PM_ENABLE
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default n
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help
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If enabled, esp_pm_* functions will keep track of the amount of time
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each of the power management locks has been held, and esp_pm_dump_locks
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function will print this information.
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This feature can be used to analyze which locks are preventing the chip
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from going into a lower power state, and see what time the chip spends
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in each power saving mode. This feature does incur some run-time
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overhead, so should typically be disabled in production builds.
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config PM_TRACE
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bool "Enable debug tracing of PM using GPIOs"
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depends on PM_ENABLE
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default n
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help
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If enabled, some GPIOs will be used to signal events such as RTOS ticks,
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frequency switching, entry/exit from idle state. Refer to pm_trace.c
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file for the list of GPIOs.
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This feature is intended to be used when analyzing/debugging behavior
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of power management implementation, and should be kept disabled in
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applications.
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config PM_SLP_IRAM_OPT
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bool "Put lightsleep related codes in internal RAM"
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depends on SOC_LIGHT_SLEEP_SUPPORTED
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select ESP_TIMER_IN_IRAM
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help
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If enabled, about 2.1KB of lightsleep related source code would be in IRAM and chip would sleep
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longer for 310us at 160MHz CPU frequency most each time.
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This feature is intended to be used when lower power consumption is needed
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while there is enough place in IRAM to place source code.
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config PM_RTOS_IDLE_OPT
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bool "Put RTOS IDLE related codes in internal RAM"
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depends on FREERTOS_USE_TICKLESS_IDLE
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help
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If enabled, about 180Bytes of RTOS_IDLE related source code would be in IRAM and chip would sleep
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longer for 20us at 160MHz CPU frequency most each time.
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This feature is intended to be used when lower power consumption is needed
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while there is enough place in IRAM to place source code.
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config PM_SLP_DISABLE_GPIO
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bool "Disable all GPIO when chip at sleep"
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depends on FREERTOS_USE_TICKLESS_IDLE
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help
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This feature is intended to disable all GPIO pins at automantic sleep to get a lower power mode.
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If enabled, chips will disable all GPIO pins at automantic sleep to reduce about 200~300 uA current.
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If you want to specifically use some pins normally as chip wakes when chip sleeps,
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you can call 'gpio_sleep_sel_dis' to disable this feature on those pins.
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You can also keep this feature on and call 'gpio_sleep_set_direction' and 'gpio_sleep_set_pull_mode'
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to have a different GPIO configuration at sleep.
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config PM_SLP_DEFAULT_PARAMS_OPT
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bool
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default n
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config PM_CHECK_SLEEP_RETENTION_FRAME
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bool
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depends on (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || \
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(ESP32P4_SELECTS_REV_LESS_V3 && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
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default y if IDF_CI_BUILD
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default n
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help
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This option is invisible to users, and it is only used for ci testing,
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enabling it in the application will increase the sleep and wake-up time overhead
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config PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL
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int "Calibrate the RTC_FAST/SLOW clock every N times of light sleep"
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default 1
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depends on PM_ENABLE
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range 1 128
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help
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The value of this option determines the calibration interval of the RTC_FAST/SLOW clock during sleep when
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power management is enabled. When it is configured as N, the RTC_FAST/SLOW clock will be calibrated
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every N times of lightsleep.
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Decreasing this value will increase the time the chip is in the active state, thereby increasing the
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average power consumption of the chip.
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Increasing this value can reduce the average power consumption, but when the external environment changes
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drastically and the chip RTC_FAST/SLOW oscillator frequency drifts, it may cause system instability.
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config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
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bool "Power down CPU in light sleep"
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depends on SOC_PM_SUPPORT_CPU_PD && !ESP32P4_SELECTS_REV_LESS_V3
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select PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
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default y
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help
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If enabled, the CPU will be powered down in light sleep,
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ESP chips supports saving and restoring CPU's running context before and after light sleep,
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the feature provides applications with seamless CPU powerdowned lightsleep without user awareness.
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But this will takes up some internal memory.
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On esp32c3 soc, enabling this option will consume 1.68 KB of internal RAM
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and will reduce sleep current consumption by about 100 uA.
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On esp32s3 soc, enabling this option will consume 8.58 KB of internal RAM
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and will reduce sleep current consumption by about 650 uA.
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choice
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bool "Retentive memory alloaction strategy for light sleep"
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depends on SOC_PM_CPU_RETENTION_BY_SW
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depends on PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || \
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(PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && ESP32P4_SELECTS_REV_LESS_V3)
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default PM_CPU_RETENTION_DYNAMIC
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help
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In light sleep mode, certain CPU states and data need to be preserved in memory while cpu domain
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is powered down. This configuration determines how the required memory resources are allocated.
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The PM_CPU_RETENTION_DYNAMIC option allows more flexible runtime memory management by
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supporting access to larger memory. However, it carries the risk of insufficient memory
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when the chip enters the light-sleep mode, even resulting in retention failure.
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In contrast, the PM_CPU_RETENTION_STATIC option ensures reliable sleep CPU retention during the
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system initialization, but reduces the memory available during runtime.
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config PM_CPU_RETENTION_DYNAMIC
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bool "Dynamically allocate memory"
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help
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Allocate memory for retention data only when preparing to enter light sleep.
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config PM_CPU_RETENTION_STATIC
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bool "Statically allocate memory"
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help
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Pre-allocate all required retention memory during system initialization.
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endchoice
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config PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP
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bool "Restore I/D-cache tag memory after power down CPU light sleep"
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depends on IDF_TARGET_ESP32S3 && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
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default y
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help
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Cache tag memory and CPU both belong to the CPU power domain.
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ESP chips supports saving and restoring Cache tag memory before and after sleep,
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this feature supports accesses to the external memory that was cached before sleep still
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be cached when the CPU wakes up from a powerdowned CPU lightsleep.
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This option controls the restore method for Cache tag memory in lightsleep.
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If this option is enabled, the I/D-cache tag memory will be backuped to the internal RAM
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before sleep and restored upon wakeup.
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Depending on the the cache configuration, if this option is enabled,
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it will consume up to 9 KB of internal RAM.
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If this option is disabled, all cached data won't be kept after sleep,
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the DCache will be writeback before sleep and invalid all cached data after sleep,
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all accesses to external memory(Flash/PSRAM) will be cache missed after waking up,
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resulting in performance degradation due to increased memory accesses latency.
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config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
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bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)"
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depends on SOC_PM_SUPPORT_TOP_PD && SOC_PAU_SUPPORTED
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depends on !(IDF_TARGET_ESP32P4 && (ESP_REV_MIN_FULL = 300) && SPIRAM)
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select PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP if !ESP32P4_SELECTS_REV_LESS_V3
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select ESP_SLEEP_POWER_DOWN_FLASH if (IDF_TARGET_ESP32P4 && (ESP_REV_MIN_FULL = 300))
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default n #TODO: enable by default if periph init/deinit management supported (WIFI-5252)
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help
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If enabled, digital peripherals will try to powered down in light sleep, then all related peripherals will
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not be available during sleep, including wake-up sources from the peripherals (For detailed availability
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information, see the note of the corresponding wakeup source enable function).
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The chip will automatically save/restore register context during sleep/wakeup to make the upper layer
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user unaware of the peripheral powerdown during sleep. Enabling this option will increase static RAM and
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heap usage but will also significantly reduce power.
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consumption during lightsleep, the actual memory cost depends on the peripherals you have initialized,
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for specific power consumption data in this mode, please refer to Electrical Characteristics section
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in the chip datasheet.
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(In order to save/restore the context of the necessary hardware for FreeRTOS to run, it will need
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at least 4.55 KB free heap at sleep time. Otherwise sleep will not power down the peripherals.)
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Note1: Please use this option with caution, the current IDF does not support the retention of
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all peripherals. When the digital peripherals are powered off and a sleep and wake-up is completed,
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the peripherals that have not saved the running context are equivalent to performing a reset.
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!!! Please confirm the peripherals used in your application and their sleep retention support status
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before enabling this option, peripherals sleep retention driver support status is tracked in
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power_management.rst
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Note2: When this option is enabled simultaneously with FREERTOS_USE_TICKLESS_IDLE, since the UART will
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be powered down, the uart FIFO will be flushed before sleep to avoid data loss, however, this has the
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potential to block the sleep process and cause the wakeup time to be skipped, which will cause the tick
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of freertos to not be compensated correctly when returning from sleep and cause the system to crash.
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To avoid this, you can increase FREERTOS_IDLE_TIME_BEFORE_SLEEP threshold in menuconfig.
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Note3: Enabling this option does not necessarily mean that the peripheral power domain will be
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turned down during sleep. The control priority of `esp_sleep_pd_config` is higher than this option,
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user code can still prevent the peripheral power domain from powering down during sleep by
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`esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON)`. In addition, whether the peripheral power
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domain is powered down during sleep also depends on the sleep working strategy selected by the driver.
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If any module belonging to the peripheral power domain chooses not to be powered down during sleep,
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then the peripheral power domain will not be powered off either.
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config PM_ESP_SLEEP_POWER_DOWN_CPU
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bool
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default y if (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && !ESP32P4_SELECTS_REV_LESS_V3)
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default y if (PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && ESP32P4_SELECTS_REV_LESS_V3)
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config PM_UPDATE_CCOMPARE_HLI_WORKAROUND
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bool
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default y if PM_ENABLE && BTDM_CTRL_HLI
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config PM_LIGHT_SLEEP_CALLBACKS
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bool "Enable registration of pm light sleep callbacks"
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depends on FREERTOS_USE_TICKLESS_IDLE
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default n
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help
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If enabled, it allows user to register entry and exit callbacks which are called before and after
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entering auto light sleep.
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NOTE: These callbacks are executed from the IDLE task context hence you cannot have any blocking calls
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in your callbacks.
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NOTE: Enabling these callbacks may change sleep duration calculations based on time spent in callback and
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hence it is highly recommended to keep them as short as possible
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endmenu # "Power Management"
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