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132 lines
6.3 KiB
C
132 lines
6.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "esp_attr.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "heap_memory_layout.h"
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#include "esp_heap_caps.h"
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/**
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* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
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* Each type of memory map consists of one or more regions in the address space.
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* Each type contains an array of prioritized capabilities.
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* Types with later entries are only taken if earlier ones can't fulfill the memory request.
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*
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* - For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions, finally eat into the application memory.
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* - For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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* - Most other malloc caps only fit in one region anyway.
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*
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*/
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/* Index of memory in `soc_memory_types[]` */
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enum {
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SOC_MEMORY_TYPE_L2MEM = 0,
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SOC_MEMORY_TYPE_SPIRAM = 1,
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SOC_MEMORY_TYPE_TCM = 2,
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SOC_MEMORY_TYPE_RTCRAM = 3,
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SOC_MEMORY_TYPE_NUM,
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};
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/* COMMON_CAPS is the set of attributes common to all types of memory on this chip */
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#define ESP32P4_MEM_COMMON_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_32BIT | MALLOC_CAP_8BIT)
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#ifdef CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT
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#define MALLOC_L2MEM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA
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#define MALLOC_RTCRAM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL
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#else
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#define MALLOC_L2MEM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_EXEC
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#define MALLOC_RTCRAM_BASE_CAPS ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL | MALLOC_CAP_EXEC
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#endif
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// The memory used for SIMD instructions requires the bus of its memory regions be able to transfer the data in 128-bit
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// TCM and RTCRAM memory regions cannot satisfy 128-bit data access
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/**
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* Defined the attributes and allocation priority of each memory on the chip,
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* The heap allocator will traverse all types of memory types in column High Priority Matching and match the specified caps at first,
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* if no memory caps matched or the allocation is failed, it will go to columns Medium Priority Matching and Low Priority Matching
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* in turn to continue matching.
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*/
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const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
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/* Mem Type Name | High Priority Matching | Medium Priority Matching | Low Priority Matching */
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[SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_SIMD, 0, 0 }},
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[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, 0, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_SIMD }},
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[SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }},
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[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}},
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};
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const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
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/**
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* @brief Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
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*
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* @note Because of requirements in the coalescing code which merges adjacent regions,
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* this list should always be sorted from low to high by start address.
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*
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*/
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/**
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* Register the shared buffer area of the last memory block into the heap during heap initialization
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*/
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#define APP_USABLE_DIRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
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#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
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#if CONFIG_ULP_COPROC_ENABLED
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#define APP_USABLE_LP_RAM_SIZE 0x8000 - LP_ROM_DRAM_SIZE
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#else
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#define APP_USABLE_LP_RAM_SIZE 0x8000
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#endif //CONFIG_ULP_COPROC_ENABLED
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const soc_memory_region_t soc_memory_regions[] = {
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#ifdef CONFIG_SPIRAM
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{ SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available
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#endif
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{ SOC_DRAM_LOW, APP_USABLE_DIRAM_END - SOC_DRAM_LOW, SOC_MEMORY_TYPE_L2MEM, SOC_IRAM_LOW, false},
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{ APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE, SOC_MEMORY_TYPE_L2MEM, APP_USABLE_DIRAM_END, true},
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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{ 0x50108000, APP_USABLE_LP_RAM_SIZE, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
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#endif
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{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false},
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};
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const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
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extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end;
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extern int _tcm_text_start, _tcm_data_end;
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extern int _rtc_reserved_start, _rtc_reserved_end;
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extern int _rtc_ulp_memory_start;
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/**
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* Reserved memory regions.
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* These are removed from the soc_memory_regions array when heaps are created.
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*
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*/
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// Static data region. DRAM used by data+bss and possibly rodata
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_low, (intptr_t)&_heap_start_low, dram_data_low);
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_high, (intptr_t)&_heap_start_high, dram_data_high);
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// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_tcm_text_start, (intptr_t)&_tcm_data_end, tcm_code_data);
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#ifdef CONFIG_SPIRAM
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SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region);
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#endif
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#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
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/* This includes any memory reserved for ULP RAM */
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SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_end, (intptr_t)&_rtc_force_slow_end, rtcram_data);
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#endif
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