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refactor(i3c): Move i3c hal to seperate folder

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This commit is contained in:
C.S.M
2026-01-04 18:08:22 +08:00
committed by BOT
parent d52166acb5
commit 060283f782
17 changed files with 75 additions and 61 deletions
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2
components/esp_driver_i3c/CMakeLists.txt
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@@ -13,10 +13,12 @@ if(${target} STREQUAL "linux")
set(priv_requires "")
else()
set(priv_requires esp_driver_gpio esp_pm esp_mm)
set(requires esp_hal_i3c)
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${include}
PRIV_REQUIRES "${priv_requires}"
REQUIRES "${requires}"
LDFRAGMENTS "linker.lf"
)

12
components/esp_driver_i3c/i3c_master.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -39,13 +39,13 @@
#include "hal/i3c_master_ll.h"
#include "i3c_master_private.h"
#include "soc/clk_tree_defs.h"
#include "soc/i3c_master_periph.h"
#include "hal/i3c_master_periph.h"
static const char *TAG = "i3c.master";
typedef struct i3c_master_platform_t {
portMUX_TYPE spinlock; // platform level spinlock.
i3c_master_bus_handle_t buses[SOC_I3C_MASTER_PERIPH_NUM]; // array of I3C master bus instances.
i3c_master_bus_handle_t buses[I3C_MASTER_LL_PERIPH_NUM]; // array of I3C master bus instances.
} i3c_master_platform_t;
static i3c_master_platform_t s_i3c_master_platform = {}; // singleton platform
@@ -333,10 +333,10 @@ static esp_err_t i3c_master_async_transaction_preparation(i3c_master_bus_t *i3c_
ESP_RETURN_ON_FALSE(xQueueSend(i3c_master_handle->trans_queues[I3C_TRANS_QUEUE_READY], &p_trans_desc, 0) == pdTRUE,
ESP_ERR_INVALID_STATE, TAG, "ready queue full");
}
i3c_master_handle->i3c_async_addr_table = (i3c_master_ll_device_address_descriptor_t(*)[SOC_I3C_MASTER_ADDRESS_TABLE_NUM])heap_caps_calloc(i3c_master_handle->queue_depth, sizeof(*i3c_master_handle->i3c_async_addr_table), I3C_MASTER_MEM_ALLOC_CAPS);
i3c_master_handle->i3c_async_addr_table = (i3c_master_ll_device_address_descriptor_t(*)[I3C_MASTER_LL_ADDRESS_TABLE_NUM])heap_caps_calloc(i3c_master_handle->queue_depth, sizeof(*i3c_master_handle->i3c_async_addr_table), I3C_MASTER_MEM_ALLOC_CAPS);
ESP_RETURN_ON_FALSE(i3c_master_handle->i3c_async_addr_table, ESP_ERR_NO_MEM, TAG, "no mem for address table");
i3c_master_handle->i3c_async_command_table = (i3c_master_ll_command_descriptor_t(*)[SOC_I3C_MASTER_COMMAND_TABLE_NUM])heap_caps_calloc(i3c_master_handle->queue_depth, sizeof(*i3c_master_handle->i3c_async_command_table), I3C_MASTER_MEM_ALLOC_CAPS);
i3c_master_handle->i3c_async_command_table = (i3c_master_ll_command_descriptor_t(*)[I3C_MASTER_LL_COMMAND_TABLE_NUM])heap_caps_calloc(i3c_master_handle->queue_depth, sizeof(*i3c_master_handle->i3c_async_command_table), I3C_MASTER_MEM_ALLOC_CAPS);
ESP_RETURN_ON_FALSE(i3c_master_handle->i3c_async_command_table, ESP_ERR_NO_MEM, TAG, "no mem for command table");
i3c_master_handle->ops_prepare_idx = 0;
@@ -714,7 +714,7 @@ esp_err_t i3c_new_master_bus(const i3c_master_bus_config_t *bus_config, i3c_mast
s_i3c_master_platform.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
portENTER_CRITICAL_SAFE(&s_i3c_master_platform.spinlock);
bool bus_found = false;
for (int i = 0; i < SOC_I3C_MASTER_PERIPH_NUM; i++) {
for (int i = 0; i < I3C_MASTER_LL_PERIPH_NUM; i++) {
if (i3c_master_bus_occupied(i) == false) {
s_i3c_master_platform.buses[i] = i3c_master_handle;
bus_found = true;

4
components/esp_driver_i3c/i3c_master_private.h
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@@ -170,8 +170,8 @@ struct i3c_master_bus_t {
i3c_transaction_desc_t *trans_desc_pool; /**< Pool of pre-allocated transaction descriptors. */
uint32_t ops_prepare_idx; /**< Index for preparing operations. */
bool async_memory_allocated; /**< The async transaction is allocated or not */
i3c_master_ll_device_address_descriptor_t (*i3c_async_addr_table)[SOC_I3C_MASTER_ADDRESS_TABLE_NUM]; /**< Address table for asynchronous transactions. */
i3c_master_ll_command_descriptor_t (*i3c_async_command_table)[SOC_I3C_MASTER_COMMAND_TABLE_NUM]; /**< Command table for asynchronous transactions. */
i3c_master_ll_device_address_descriptor_t (*i3c_async_addr_table)[I3C_MASTER_LL_ADDRESS_TABLE_NUM]; /**< Address table for asynchronous transactions. */
i3c_master_ll_command_descriptor_t (*i3c_async_command_table)[I3C_MASTER_LL_COMMAND_TABLE_NUM]; /**< Command table for asynchronous transactions. */
QueueHandle_t trans_queues[I3C_TRANS_QUEUE_MAX]; /**< Array of transaction queues for different states. */
intr_handle_t intr_handle; /**< Interrupt handle for I3C interrupts. */
_Atomic i3c_fsm_t fsm; /**< Current state of the I3C finite state machine. */

9
components/esp_driver_i3c/test_apps/i3c_test_apps/CMakeLists.txt
View File

@@ -13,9 +13,16 @@ project(i3c_master_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
set(I3C_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i3c
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_i3c
)
string(JOIN "," I3C_RTL_DIRS_JOINED ${I3C_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i3c/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${I3C_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/i3c_master_test.elf
find-refs
--from-sections=.iram0.text

22
components/esp_hal_i3c/CMakeLists.txt Normal file
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@@ -0,0 +1,22 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(includes)
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
list(APPEND includes "include")
set(srcs)
# I3C related source files
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "i3c_master_hal.c" "${target}/i3c_master_periph.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal)

9
components/esp_hal_i3c/README.md Normal file
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@@ -0,0 +1,9 @@
# `esp_hal_i3c`
⚠️ This HAL component is still under heavy development at the moment, so we don't guarantee the stability and backward-compatibility among versions.
The `esp_hal_i3c` component provides a **Hardware Abstraction Layer** of I3C for all targets supported by ESP-IDF.
In a broad sense, the HAL layer consists of two sub-layers: HAL (upper) and Low-Level(bottom). The HAL layer defines the steps and data that is required to operate a peripheral (e.g. initialization, parameter settings). The low-level is a translation layer above the register files under the `soc` component, it only covers general conceptions to register configurations.
The functions in this file mainly provide hardware abstraction for IDF peripheral drivers. For advanced developers, the HAL layer functions can also be directly used to assist in implementing their own drivers. However, it needs to be mentioned again that the interfaces here do not guarantee stability.

6
components/soc/esp32p4/i3c_master_periph.c → components/esp_hal_i3c/esp32p4/i3c_master_periph.c
View File

@@ -1,17 +1,17 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i3c_master_periph.h"
#include "hal/i3c_master_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/interrupts.h"
/*
Bunch of constants for every I3C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i3c_master_signal_conn_t i3c_master_periph_signal[SOC_I3C_MASTER_PERIPH_NUM] = {
const i3c_master_signal_conn_t i3c_master_periph_signal[I3C_MASTER_LL_PERIPH_NUM] = {
{
.module_name = "I3C_MASTER",
.sda_out_sig = I3C_MST_SDA_PAD_OUT_IDX,

34
components/hal/esp32p4/include/hal/i3c_master_ll.h → components/esp_hal_i3c/esp32p4/include/hal/i3c_master_ll.h
View File

@@ -33,6 +33,9 @@ extern "C" {
#define I3C_LL_MASTER_TRANSMIT_INTR (I3C_MST_TX_DATA_BUF_THLD_INT_ENA_M)
#define I3C_LL_MASTER_RECEIVE_INTR (I3C_MST_RX_DATA_BUF_THLD_INT_ENA_M)
#define I3C_LL_MASTER_INTERNAL_PULLUP_IO_PINS_MASK (BIT64(32) | BIT64(33))
#define I3C_MASTER_LL_PERIPH_NUM (1)
#define I3C_MASTER_LL_ADDRESS_TABLE_NUM (12)
#define I3C_MASTER_LL_COMMAND_TABLE_NUM (12)
#define I3C_MASTER_LL_DEFAULT_SETUP_TIME (600)
@@ -308,7 +311,6 @@ typedef struct {
uint8_t dynamic_addr; ///< 7-bit dynamic address assigned via DATA/SETDASA
} i3c_master_ll_device_char_descriptor_t;
/**
* @brief IBI response status
*
@@ -1065,21 +1067,21 @@ static inline void i3c_master_ll_set_internal_pullup_value(int io, i3c_master_in
{
HAL_ASSERT(io == 32 || io == 33);
switch (value) {
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_0_3K:
IO_MUX.gpio[io].i3c_ru = 0;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_0_6K:
IO_MUX.gpio[io].i3c_ru = 1;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_1_2K:
IO_MUX.gpio[io].i3c_ru = 2;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_2_4K:
IO_MUX.gpio[io].i3c_ru = 3;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_DISABLED:
HAL_ASSERT(false);
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_0_3K:
IO_MUX.gpio[io].i3c_ru = 0;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_0_6K:
IO_MUX.gpio[io].i3c_ru = 1;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_1_2K:
IO_MUX.gpio[io].i3c_ru = 2;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_2_4K:
IO_MUX.gpio[io].i3c_ru = 3;
break;
case I3C_MASTER_INTERNAL_PULLUP_RESISTOR_DISABLED:
HAL_ASSERT(false);
break;
}
}

5
components/soc/include/soc/i3c_master_periph.h → components/esp_hal_i3c/esp32p4/include/hal/i3c_master_periph.h
View File

@@ -1,13 +1,14 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdlib.h>
#include "soc/soc_caps.h"
#include "hal/i3c_master_ll.h"
#ifdef __cplusplus
extern "C" {
@@ -24,7 +25,7 @@ typedef struct {
const uint8_t irq;
} i3c_master_signal_conn_t;
extern const i3c_master_signal_conn_t i3c_master_periph_signal[SOC_I3C_MASTER_PERIPH_NUM];
extern const i3c_master_signal_conn_t i3c_master_periph_signal[I3C_MASTER_LL_PERIPH_NUM];
#endif

3
components/hal/esp32p4/include/hal/i3c_slave_ll.h → components/esp_hal_i3c/esp32p4/include/hal/i3c_slave_ll.h
View File

@@ -24,7 +24,6 @@ extern "C" {
#define I3C_SLAVE_LL_EVENT_INTR (I3C_SLV_RXPEND_ENA_M | I3C_SLV_TXSEND_ENA_M)
/**
* @brief Enable or disable I3C slave bus clock
*
@@ -70,7 +69,6 @@ static inline void i3c_slave_ll_config_static_address(i3c_slv_dev_t *hw, uint8_t
hw->config.saddr = address;
}
/**
* @brief Get pointer to I3C slave interrupt status register
*
@@ -82,7 +80,6 @@ static inline volatile void *i3c_slave_ll_get_interrupt_status_reg(i3c_slv_dev_t
return &dev->intmasked;
}
/**
* @brief Clear I3C slave interrupt flags
*

0
components/hal/i3c_master_hal.c → components/esp_hal_i3c/i3c_master_hal.c
View File

0
components/hal/include/hal/i3c_master_hal.h → components/esp_hal_i3c/include/hal/i3c_master_hal.h
View File

3
components/hal/include/hal/i3c_master_types.h → components/esp_hal_i3c/include/hal/i3c_master_types.h
View File

@@ -29,13 +29,12 @@ typedef soc_periph_i3c_master_clk_src_t i3c_master_clock_source_t;
typedef int i3c_master_clock_source_t;
#endif
/**
* @brief I3C Common Command Code (CCC) enumeration
*
* This enumeration defines all I3C CCC command codes as per MIPI I3C specification.
*/
typedef enum {
typedef enum {
I3C_CCC_ENEC = 0x00, ///< Enable Events Command
I3C_CCC_DISEC = 0x01, ///< Disable Events Command
I3C_CCC_ENTAS0 = 0x02, ///< Enable Target Activity State 0

4
components/hal/CMakeLists.txt
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@@ -75,10 +75,6 @@ elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "systimer_hal.c")
endif()
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "i3c_master_hal.c")
endif()
if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
list(APPEND srcs "sdmmc_hal.c")
endif()

4
components/soc/CMakeLists.txt
View File

@@ -66,10 +66,6 @@ if(CONFIG_SOC_DEBUG_PROBE_SUPPORTED)
list(APPEND srcs "${target_folder}/debug_probe_periph.c")
endif()
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "${target_folder}/i3c_master_periph.c")
endif()
if(CONFIG_SOC_MPI_SUPPORTED)
list(APPEND srcs "${target_folder}/mpi_periph.c")
endif()

12
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1939,18 +1939,6 @@ config SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV
bool
default y
config SOC_I3C_MASTER_PERIPH_NUM
bool
default y
config SOC_I3C_MASTER_ADDRESS_TABLE_NUM
int
default 12
config SOC_I3C_MASTER_COMMAND_TABLE_NUM
int
default 12
config SOC_LP_CORE_SUPPORT_ETM
bool
default y

7
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -740,11 +740,6 @@
/*--------------------------- CAM ---------------------------------*/
#define SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV (1)
/*--------------------------- I3C ---------------------------------*/
#define SOC_I3C_MASTER_PERIPH_NUM (1)
#define SOC_I3C_MASTER_ADDRESS_TABLE_NUM (12)
#define SOC_I3C_MASTER_COMMAND_TABLE_NUM (12)
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */