alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-01-19 17:55:43 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/fix_esp32_phy_init_bb_clock_issue_v6.0' into 'release/v6.0'

Browse Source 
bugfix(wifi): fix incomplete phy initialization due to absence of bb clocks at...

See merge request espressif/esp-idf!44649
This commit is contained in:
Jiang Jiang Jian
2026-01-10 13:09:17 +08:00
parent 6d53193eb3 f8994c268a
commit 21d2788468
44 changed files with 444 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
components/esp_hw_support/include/esp_private/esp_modem_clock.h
View File

@@ -62,6 +62,27 @@ void modem_clock_module_enable(shared_periph_module_t module);
*/
void modem_clock_module_disable(shared_periph_module_t module);
/**
* @brief Gets the clock bitmask associated with the specified modem module.
*
* This function returns the complete set of clock-enable bits that correspond
* to @p module.
*
* @param module Target shared peripheral clock module.
*
* @return Bitmask of clock-enable bits for the given module.
*/
uint32_t modem_clock_module_bits_get(shared_periph_module_t module);
#if SOC_WIFI_SUPPORTED
/**
* @brief Set Wi-Fi initialization status.
*
* @param inited Wi-Fi initialization status.
*/
void modem_clock_configure_wifi_status(bool inited);
#endif
/**
* @brief Reset the mac of modem module
*

21
components/esp_hw_support/include/esp_private/periph_ctrl.h
View File

@@ -153,6 +153,27 @@ void wifi_module_enable(void);
*/
void wifi_module_disable(void);
/**
* @brief Enable phy module by un-gating related clock and de-asserting the reset signal.
*
* @note This function acquires clocks required during the PHY enable sequence.
*/
void phy_module_enable(void);
/**
* @brief Disable phy module by gating related clock and asserting the reset signal.
*
* @note This function releases clocks required during the PHY enable sequence.
*/
void phy_module_disable(void);
/**
* @brief Checks whether phy module has all bits in @p mask set.
*
* @return true if all bits in @p mask are set; false otherwise.
*/
bool phy_module_has_clock_bits(uint32_t mask);
#undef __PERIPH_CTRL_DEPRECATE_ATTR
#ifdef __cplusplus

69
components/esp_hw_support/modem_clock.c
View File

@@ -54,6 +54,8 @@ typedef enum {
MODEM_CLOCK_DEVICE_MAX
} modem_clock_device_t;
#define MODEM_STATUS_IDLE (0)
#define MODEM_STATUS_WIFI_INITED (0x1UL)
typedef struct modem_clock_context {
modem_clock_hal_context_t *hal;
@@ -65,13 +67,16 @@ typedef struct modem_clock_context {
} dev[MODEM_CLOCK_DEVICE_MAX];
/* the low-power clock source for each module */
modem_clock_lpclk_src_t lpclk_src[PERIPH_MODEM_MODULE_NUM];
#if SOC_WIFI_SUPPORTED
uint32_t modem_status;
#endif
} modem_clock_context_t;
#if SOC_WIFI_SUPPORTED
static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx, bool enable)
{
if (enable) {
if (enable || !(ctx->modem_status & MODEM_STATUS_WIFI_INITED)) {
#if !SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
#endif
@@ -81,7 +86,7 @@ static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx,
static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx, bool enable)
{
if (enable) {
if (enable || !(ctx->modem_status & MODEM_STATUS_WIFI_INITED)) {
modem_syscon_ll_clk_wifibb_configure(ctx->hal->syscon_dev, enable);
}
}
@@ -99,14 +104,14 @@ static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx,
#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
static void IRAM_ATTR modem_clock_wifi_apb_configure(modem_clock_context_t *ctx, bool enable)
{
if (enable) {
if (enable || !(ctx->modem_status & MODEM_STATUS_WIFI_INITED)) {
modem_syscon_ll_enable_wifi_apb_clock(ctx->hal->syscon_dev, enable);
}
}
static void IRAM_ATTR modem_clock_wifi_bb_44m_configure(modem_clock_context_t *ctx, bool enable)
{
if (enable) {
if (enable || !(ctx->modem_status & MODEM_STATUS_WIFI_INITED)) {
modem_syscon_ll_enable_wifibb_44m_clock(ctx->hal->syscon_dev, enable);
}
}
@@ -196,6 +201,10 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi
[MODEM_CLOCK_DATADUMP] = { .refs = 0, .configure = modem_clock_data_dump_configure }
},
.lpclk_src = { [0 ... PERIPH_MODEM_MODULE_NUM - 1] = MODEM_CLOCK_LPCLK_SRC_INVALID }
#if SOC_WIFI_SUPPORTED
,
.modem_status = MODEM_STATUS_IDLE
#endif
};
if (modem_clock_hal.syscon_dev == NULL || modem_clock_hal.lpcon_dev == NULL) {
modem_clock_hal.syscon_dev = &MODEM_SYSCON;
@@ -312,8 +321,21 @@ void IRAM_ATTR modem_clock_module_mac_reset(shared_periph_module_t module)
#define MODEM_ETM_CLOCK_DEPS (BIT(MODEM_CLOCK_ETM))
#define MODEM_ADC_COMMON_FE_CLOCK_DEPS (BIT(MODEM_CLOCK_MODEM_ADC_COMMON_FE))
#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
#define PHY_CALIBRATION_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_APB) | BIT(MODEM_CLOCK_WIFI_BB_44M))
#define PHY_CALIBRATION_WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_APB) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_WIFI_BB_44M))
#define PHY_CALIBRATION_BT_I154_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_APB) | BIT(MODEM_CLOCK_WIFI_BB_44M) | BIT(MODEM_CLOCK_BT_I154_COMMON_BB))
#else
#define PHY_CALIBRATION_WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_WIFI_BB))
#define PHY_CALIBRATION_BT_I154_CLOCK_DEPS (BIT(MODEM_CLOCK_BT_I154_COMMON_BB))
#endif
#ifndef SOC_WIFI_SUPPORTED
#undef PHY_CALIBRATION_WIFI_CLOCK_DEPS
#define PHY_CALIBRATION_WIFI_CLOCK_DEPS 0
#endif
#if !defined(SOC_BT_SUPPORTED) && !defined(SOC_IEEE802154_SUPPORTED)
#undef PHY_CALIBRATION_BT_I154_CLOCK_DEPS
#define PHY_CALIBRATION_BT_I154_CLOCK_DEPS 0
#endif
#define PHY_CALIBRATION_CLOCK_DEPS (PHY_CALIBRATION_WIFI_CLOCK_DEPS | PHY_CALIBRATION_BT_I154_CLOCK_DEPS)
static IRAM_ATTR uint32_t modem_clock_get_module_deps(shared_periph_module_t module)
{
@@ -331,9 +353,7 @@ static IRAM_ATTR uint32_t modem_clock_get_module_deps(shared_periph_module_t mod
#if SOC_BT_SUPPORTED
case PERIPH_BT_MODULE: deps = BLE_CLOCK_DEPS; break;
#endif
#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
case PERIPH_PHY_CALIBRATION_MODULE: deps = PHY_CALIBRATION_CLOCK_DEPS; break;
#endif
#if SOC_IEEE802154_SUPPORTED
case PERIPH_IEEE802154_MODULE: deps = IEEE802154_CLOCK_DEPS; break;
#endif
@@ -396,6 +416,41 @@ void IRAM_ATTR modem_clock_module_disable(shared_periph_module_t module)
modem_clock_device_disable(MODEM_CLOCK_instance(), deps);
}
uint32_t IRAM_ATTR modem_clock_module_bits_get(shared_periph_module_t module)
{
assert(IS_MODEM_MODULE(module));
uint32_t val = 0;
switch (module)
{
#if SOC_WIFI_SUPPORTED
case PERIPH_WIFI_MODULE:
#endif
#if SOC_BT_SUPPORTED
case PERIPH_BT_MODULE:
#endif
#if SOC_IEEE802154_SUPPORTED
case PERIPH_IEEE802154_MODULE:
#endif
case PERIPH_PHY_MODULE:
val = modem_syscon_ll_clk_conf1_get(MODEM_CLOCK_instance()->hal->syscon_dev);
default:
break;
}
return val;
}
#if SOC_WIFI_SUPPORTED
void modem_clock_configure_wifi_status(bool inited)
{
esp_os_enter_critical_safe(&MODEM_CLOCK_instance()->lock);
if (inited)
MODEM_CLOCK_instance()->modem_status |= MODEM_STATUS_WIFI_INITED;
else
MODEM_CLOCK_instance()->modem_status &= ~MODEM_STATUS_WIFI_INITED;
esp_os_exit_critical_safe(&MODEM_CLOCK_instance()->lock);
}
#endif
void modem_clock_deselect_all_module_lp_clock_source(void)
{
#if SOC_WIFI_SUPPORTED

89
components/esp_hw_support/periph_ctrl.c
View File

@@ -11,6 +11,7 @@
#ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
#include "hal/clk_gate_ll.h"
#endif
#include "esp_log.h"
#if SOC_MODEM_CLOCK_IS_INDEPENDENT && SOC_MODEM_CLOCK_SUPPORTED
#include "esp_private/esp_modem_clock.h"
@@ -131,7 +132,10 @@ void wifi_module_enable(void)
modem_clock_module_enable(PERIPH_WIFI_MODULE);
#else
esp_os_enter_critical_safe(&periph_spinlock);
periph_ll_wifi_module_enable_clk_clear_rst();
if (ref_counts[PERIPH_WIFI_MODULE] == 0) {
periph_ll_wifi_module_enable_clk_clear_rst();
}
ref_counts[PERIPH_WIFI_MODULE]++;
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
@@ -142,8 +146,89 @@ void wifi_module_disable(void)
modem_clock_module_disable(PERIPH_WIFI_MODULE);
#else
esp_os_enter_critical_safe(&periph_spinlock);
periph_ll_wifi_module_disable_clk_set_rst();
ref_counts[PERIPH_WIFI_MODULE]--;
if (ref_counts[PERIPH_WIFI_MODULE] == 0) {
periph_ll_wifi_module_disable_clk_set_rst();
}
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
#endif // CONFIG_ESP_WIFI_ENABLED
#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED
// PERIPH_WIFI_BT_COMMON_MODULE is enabled outside
IRAM_ATTR void phy_module_enable(void)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_PHY_CALIBRATION_MODULE);
#else
esp_os_enter_critical_safe(&periph_spinlock);
#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED
periph_ll_phy_calibration_module_enable_clk_clear_rst();
if (ref_counts[PERIPH_RNG_MODULE] == 0) {
periph_ll_enable_clk_clear_rst(PERIPH_RNG_MODULE);
}
ref_counts[PERIPH_RNG_MODULE]++;
#endif
#if SOC_WIFI_SUPPORTED
if (ref_counts[PERIPH_WIFI_MODULE] == 0) {
periph_ll_wifi_module_enable_clk_clear_rst();
}
ref_counts[PERIPH_WIFI_MODULE]++;
#endif
#if SOC_BT_SUPPORTED
if (ref_counts[PERIPH_BT_MODULE] == 0) {
periph_ll_enable_clk_clear_rst(PERIPH_BT_MODULE);
}
ref_counts[PERIPH_BT_MODULE]++;
#endif
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
// PERIPH_WIFI_BT_COMMON_MODULE is disabled outside
IRAM_ATTR void phy_module_disable(void)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_PHY_CALIBRATION_MODULE);
#else
esp_os_enter_critical_safe(&periph_spinlock);
#if SOC_BT_SUPPORTED
ref_counts[PERIPH_BT_MODULE]--;
if (ref_counts[PERIPH_BT_MODULE] == 0) {
periph_ll_disable_clk_set_rst(PERIPH_BT_MODULE);
}
#endif
#if SOC_WIFI_SUPPORTED
ref_counts[PERIPH_WIFI_MODULE]--;
if (ref_counts[PERIPH_WIFI_MODULE] == 0) {
periph_ll_wifi_module_disable_clk_set_rst();
}
#endif
#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED
// Do not disable PHY clock and RNG clock
ref_counts[PERIPH_RNG_MODULE]--;
#endif
esp_os_exit_critical_safe(&periph_spinlock);
#endif
}
IRAM_ATTR bool phy_module_has_clock_bits(uint32_t mask)
{
uint32_t val = 0;
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
val = modem_clock_module_bits_get(PERIPH_PHY_MODULE);
#else
#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED
val = DPORT_REG_READ(periph_ll_get_clk_en_reg(PERIPH_WIFI_BT_COMMON_MODULE));
#else
return true;
#endif
#endif
if ((val & mask) != mask) {
ESP_LOGW("periph_ctrl", "phy module clock bits 0x%x, required 0x%x", val, mask);
return false;
}
return true;
}
#endif //#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED

9
components/esp_phy/esp32/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x8FCF

9
components/esp_phy/esp32c2/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0xE0788FCF

9
components/esp_phy/esp32c3/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x788FCF

9
components/esp_phy/esp32c5/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x3BE7FF

9
components/esp_phy/esp32c6/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x7E7FF

9
components/esp_phy/esp32c61/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x3BE7FF

9
components/esp_phy/esp32h2/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x7f000

9
components/esp_phy/esp32h21/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x0 //TODO

9
components/esp_phy/esp32h4/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x0 //TODO

9
components/esp_phy/esp32s2/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x7887CF

9
components/esp_phy/esp32s3/include/phy_init_deps.h Normal file
View File

@@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0x788FCF

31
components/esp_phy/src/phy_init.c
View File

@@ -53,6 +53,12 @@
#include "esp_private/esp_modem_clock.h"
#include "soc/periph_defs.h"
#endif
#include "phy_init_deps.h"
#ifndef PHY_INIT_MODEM_CLOCK_REQUIRED_BITS
#warning "PHY_INIT_MODEM_CLOCK_REQUIRED_BITS not defined; using default value 0"
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0
#endif
#if CONFIG_IDF_TARGET_ESP32
extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
@@ -272,22 +278,6 @@ IRAM_ATTR void esp_phy_common_clock_disable(void)
wifi_bt_common_module_disable();
}
#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
IRAM_ATTR void esp_phy_calibration_clock_enable(esp_phy_modem_t modem)
{
if (modem == PHY_MODEM_BT || modem == PHY_MODEM_IEEE802154) {
modem_clock_module_enable(PERIPH_PHY_CALIBRATION_MODULE);
}
}
IRAM_ATTR void esp_phy_calibration_clock_disable(esp_phy_modem_t modem)
{
if (modem == PHY_MODEM_BT || modem == PHY_MODEM_IEEE802154) {
modem_clock_module_disable(PERIPH_PHY_CALIBRATION_MODULE);
}
}
#endif
#if SOC_PM_MODEM_RETENTION_BY_BACKUPDMA
static inline void phy_digital_regs_store(void)
{
@@ -316,9 +306,8 @@ void esp_phy_enable(esp_phy_modem_t modem)
phy_update_wifi_mac_time(false, s_phy_rf_en_ts);
#endif
esp_phy_common_clock_enable();
#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
esp_phy_calibration_clock_enable(modem);
#endif
phy_module_enable();
assert(phy_module_has_clock_bits(PHY_INIT_MODEM_CLOCK_REQUIRED_BITS));
if (s_is_phy_calibrated == false) {
esp_phy_load_cal_and_init();
s_is_phy_calibrated = true;
@@ -360,9 +349,7 @@ void esp_phy_enable(esp_phy_modem_t modem)
phy_ant_update();
phy_ant_clr_update_flag();
}
#if SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
esp_phy_calibration_clock_disable(modem);
#endif
phy_module_disable();
}
phy_set_modem_flag(modem);
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_ESP_PHY_DISABLE_PLL_TRACK

10
components/esp_phy/src/phy_init_esp32hxx.c
View File

@@ -9,10 +9,17 @@
#include "esp_phy_init.h"
#include "esp_private/phy.h"
#include "esp_timer.h"
#include "esp_private/periph_ctrl.h"
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#include "phy_init_deps.h"
#ifndef PHY_INIT_MODEM_CLOCK_REQUIRED_BITS
#warning "PHY_INIT_MODEM_CLOCK_REQUIRED_BITS not defined; using default value 0"
#define PHY_INIT_MODEM_CLOCK_REQUIRED_BITS 0
#endif
#define PHY_ENABLE_VERSION_PRINT 1
@@ -106,6 +113,8 @@ void esp_phy_enable(esp_phy_modem_t modem)
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_PHY_MODULE);
#endif
phy_module_enable();
assert(phy_module_has_clock_bits(PHY_INIT_MODEM_CLOCK_REQUIRED_BITS));
if (!s_phy_is_enabled) {
register_chipv7_phy(NULL, NULL, PHY_RF_CAL_FULL);
phy_version_print();
@@ -116,6 +125,7 @@ void esp_phy_enable(esp_phy_modem_t modem)
#if !CONFIG_ESP_PHY_DISABLE_PLL_TRACK
phy_track_pll_init();
#endif
phy_module_disable();
}
phy_set_modem_flag(modem);
// Immediately track pll when phy enabled.

12
components/esp_wifi/src/wifi_init.c
View File

@@ -42,6 +42,10 @@
#include "esp_roaming.h"
#endif
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
static bool s_wifi_inited = false;
#if (CONFIG_ESP_WIFI_RX_BA_WIN > CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM)
@@ -255,6 +259,10 @@ static esp_err_t wifi_deinit_internal(void)
#endif
s_wifi_inited = false;
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_configure_wifi_status(s_wifi_inited);
#endif
return err;
}
@@ -491,6 +499,10 @@ esp_err_t esp_wifi_init(const wifi_init_config_t *config)
s_wifi_inited = true;
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_configure_wifi_status(s_wifi_inited);
#endif
return result;
_deinit:

10
components/hal/esp32/include/hal/clk_gate_ll.h
View File

@@ -158,6 +158,16 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_enable_clk_clear_rst(void)
{
// No clock bit only for phy calibration on ESP32
}
static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
{
// No clock bit only for phy calibration on ESP32
}
#ifdef __cplusplus
}
#endif

12
components/hal/esp32c2/include/hal/clk_gate_ll.h
View File

@@ -131,6 +131,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_PHY_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_PHY_EN_M);
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
#ifdef __cplusplus
}
#endif

12
components/hal/esp32c3/include/hal/clk_gate_ll.h
View File

@@ -144,6 +144,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_PHY_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_PHY_EN_M);
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
#ifdef __cplusplus
}
#endif

6
components/hal/esp32c5/include/hal/modem_syscon_ll.h
View File

@@ -324,6 +324,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
}
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
{
return hw->clk_conf1.val;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
{

8
components/hal/esp32c6/include/hal/modem_syscon_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -293,6 +293,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
}
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
{
return hw->clk_conf1.val;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
{

6
components/hal/esp32c61/include/hal/modem_syscon_ll.h
View File

@@ -324,6 +324,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
}
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
{
return hw->clk_conf1.val;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_clk_wifibb_configure(modem_syscon_dev_t *hw, bool en)
{

6
components/hal/esp32h2/include/hal/modem_syscon_ll.h
View File

@@ -197,6 +197,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
}
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
{
return hw->clk_conf1.val;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
{

6
components/hal/esp32h21/include/hal/modem_syscon_ll.h
View File

@@ -198,6 +198,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
}
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
{
return hw->clk_conf1.val;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
{

6
components/hal/esp32h4/include/hal/modem_syscon_ll.h
View File

@@ -298,6 +298,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
}
}
__attribute__((always_inline))
static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
{
return hw->clk_conf1.val;
}
__attribute__((always_inline))
static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
{

12
components/hal/esp32s2/include/hal/clk_gate_ll.h
View File

@@ -140,6 +140,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_PHY_EN_M);
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_PHY_EN_M);
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
}
#ifdef __cplusplus
}
#endif

13
components/hal/esp32s3/include/hal/clk_gate_ll.h
View File

@@ -83,6 +83,7 @@ static inline uint32_t periph_ll_get_clk_en_reg(shared_periph_module_t periph)
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
case PERIPH_WIFI_BT_COMMON_MODULE:
return SYSTEM_WIFI_CLK_EN_REG;
case PERIPH_UART2_MODULE:
case PERIPH_LCD_CAM_MODULE:
return SYSTEM_PERIP_CLK_EN1_REG;
@@ -153,6 +154,18 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_PHY_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_PHY_EN_M);
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
#ifdef __cplusplus
}
#endif

6
components/hal/include/hal/ieee802154_common_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -470,8 +470,8 @@ static inline void ieee802154_ll_set_security_key(uint8_t *security_key)
static inline void ieee802154_ll_disable_coex(void)
{
IEEE802154.pti.pti = 1;
IEEE802154.pti.hw_ack_pti = 1;
IEEE802154.pti.pti = 3;
IEEE802154.pti.hw_ack_pti = 3;
}
static inline void ieee802154_ll_clear_debug_cnt(uint32_t clear_bits)

2
components/ieee802154/driver/esp_ieee802154_dev.c
View File

@@ -1068,6 +1068,7 @@ esp_err_t ieee802154_energy_detect(uint32_t duration)
stop_current_operation();
ieee802154_pib_update();
IEEE802154_SET_TXRX_PTI(IEEE802154_SCENE_RX);
start_ed(duration);
ieee802154_set_state(IEEE802154_STATE_ED);
@@ -1084,6 +1085,7 @@ esp_err_t ieee802154_cca(void)
stop_current_operation();
ieee802154_pib_update();
IEEE802154_SET_TXRX_PTI(IEEE802154_SCENE_RX);
start_ed(CCA_DETECTION_TIME);
ieee802154_set_state(IEEE802154_STATE_CCA);

1
components/soc/esp32/include/soc/periph_defs.h
View File

@@ -25,6 +25,7 @@ typedef enum {
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_BT_BASEBAND_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
} shared_periph_module_t;

1
components/soc/esp32c2/include/soc/periph_defs.h
View File

@@ -20,6 +20,7 @@ typedef enum {
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
} shared_periph_module_t;

2
components/soc/esp32c2/register/soc/syscon_reg.h
View File

@@ -178,6 +178,8 @@ extern "C" {
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Mask for clock bits used by phy calibration, bit 22, 29, 30, 31 */
#define SYSTEM_WIFI_CLK_PHY_EN_M 0xE0400000
/* Digital team to check */
//bluetooth baseband bit11

1
components/soc/esp32c3/include/soc/periph_defs.h
View File

@@ -22,6 +22,7 @@ typedef enum {
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
} shared_periph_module_t;

2
components/soc/esp32c3/register/soc/syscon_reg.h
View File

@@ -177,6 +177,8 @@ extern "C" {
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Mask for clock bits used by phy calibration, bit 22 */
#define SYSTEM_WIFI_CLK_PHY_EN_M 0x400000
/* Digital team to check */
//bluetooth baseband bit11

3
components/soc/esp32c6/include/soc/periph_defs.h
View File

@@ -36,12 +36,13 @@ typedef enum {
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} shared_periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_CALIBRATION_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))

3
components/soc/esp32h2/include/soc/periph_defs.h
View File

@@ -34,12 +34,13 @@ typedef enum {
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} shared_periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_CALIBRATION_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))

3
components/soc/esp32h21/include/soc/periph_defs.h
View File

@@ -26,12 +26,13 @@ typedef enum {
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} shared_periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_CALIBRATION_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))

3
components/soc/esp32h4/include/soc/periph_defs.h
View File

@@ -26,12 +26,13 @@ typedef enum {
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} shared_periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_CALIBRATION_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))

1
components/soc/esp32s2/include/soc/periph_defs.h
View File

@@ -22,6 +22,7 @@ typedef enum {
PERIPH_WIFI_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
} shared_periph_module_t;

3
components/soc/esp32s2/register/soc/syscon_reg.h
View File

@@ -445,6 +445,9 @@ extern "C" {
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M
/* Mask for clock bits used by phy calibration, bit 22 */
#define SYSTEM_WIFI_CLK_PHY_EN_M 0x400000
#define DPORT_WIFI_CLK_PHY_EN_M SYSTEM_WIFI_CLK_PHY_EN_M
/* Digital team to check */
//bluetooth baseband bit11

1
components/soc/esp32s3/include/soc/periph_defs.h
View File

@@ -24,6 +24,7 @@ typedef enum {
PERIPH_BT_MODULE,
PERIPH_WIFI_BT_COMMON_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_MODULE_MAX
} shared_periph_module_t;

2
components/soc/esp32s3/register/soc/syscon_reg.h
View File

@@ -178,6 +178,8 @@ extern "C" {
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Mask for clock bits used by phy calibration, bit 22 */
#define SYSTEM_WIFI_CLK_PHY_EN_M 0x400000
//bluetooth baseband bit11
#define SYSTEM_BT_BASEBAND_EN BIT(11)