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Merge branch 'feat/update_reg_files_for_aes_and_sha_p4_eco5' into 'master'
feat: updated reg files for aes and sha for ESP32P4 ECO5 Closes IDF-12237 and IDF-13437 See merge request espressif/esp-idf!43723
This commit is contained in:
Aditya Patwardhan
@@ -1,462 +0,0 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** AES_KEY_0_REG register
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* AES key data register 0
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*/
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#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_1_REG register
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* AES key data register 1
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*/
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#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_2_REG register
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* AES key data register 2
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*/
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#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_3_REG register
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* AES key data register 3
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*/
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#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_4_REG register
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* AES key data register 4
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*/
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#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_5_REG register
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* AES key data register 5
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*/
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#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_6_REG register
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* AES key data register 6
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*/
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#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_7_REG register
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* AES key data register 7
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*/
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#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_TEXT_IN_0_REG register
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* Source text data register 0
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*/
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#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_1_REG register
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* Source text data register 1
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*/
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#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_2_REG register
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* Source text data register 2
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*/
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#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_3_REG register
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* Source text data register 3
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*/
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#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_OUT_0_REG register
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* Result text data register 0
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*/
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#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_1_REG register
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* Result text data register 1
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*/
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#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_2_REG register
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* Result text data register 2
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*/
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#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_3_REG register
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* Result text data register 3
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*/
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#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_MODE_REG register
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* Defines key length and encryption / decryption
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*/
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#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
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/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
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* Configures the key length and encryption / decryption of the AES accelerator.
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* 0: AES-128 encryption
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* 1: AES-192 encryption
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* 2: AES-256 encryption
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* 3: Reserved
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* 4: AES-128 decryption
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* 5: AES-192 decryption
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* 6: AES-256 decryption
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* 7: Reserved
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*/
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#define AES_MODE 0x00000007U
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#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
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#define AES_MODE_V 0x00000007U
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#define AES_MODE_S 0
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/** AES_TRIGGER_REG register
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* Operation start controlling register
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*/
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#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
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/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
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* Configures whether or not to start AES operation.
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* 0: No effect
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* 1: Start
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*/
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#define AES_TRIGGER (BIT(0))
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#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
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#define AES_TRIGGER_V 0x00000001U
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#define AES_TRIGGER_S 0
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/** AES_STATE_REG register
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* Operation status register
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*/
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#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
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/** AES_STATE : RO; bitpos: [1:0]; default: 0;
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* Represents the working status of the AES accelerator.
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* In Typical AES working mode:
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* 0: IDLE
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* 1: WORK
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* 2: No effect
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* 3: No effect
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* In DMA-AES working mode:
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* 0: IDLE
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* 1: WORK
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* 2: DONE
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* 3: No effect
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*/
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#define AES_STATE 0x00000003U
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#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
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#define AES_STATE_V 0x00000003U
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#define AES_STATE_S 0
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/** AES_IV_MEM register
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* The memory that stores initialization vector
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*/
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#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
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#define AES_IV_MEM_SIZE_BYTES 16
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/** AES_H_MEM register
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* The memory that stores GCM hash subkey
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*/
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#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
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#define AES_H_MEM_SIZE_BYTES 16
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/** AES_J0_MEM register
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* The memory that stores J0
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*/
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#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
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#define AES_J0_MEM_SIZE_BYTES 16
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/** AES_T0_MEM register
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* The memory that stores T0
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*/
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#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
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#define AES_T0_MEM_SIZE_BYTES 16
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/** AES_DMA_ENABLE_REG register
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* Selects the working mode of the AES accelerator
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*/
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#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
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/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
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* Configures the working mode of the AES accelerator.
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* 0: Typical AES
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* 1: DMA-AES
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*/
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#define AES_DMA_ENABLE (BIT(0))
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#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
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#define AES_DMA_ENABLE_V 0x00000001U
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#define AES_DMA_ENABLE_S 0
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/** AES_BLOCK_MODE_REG register
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* Defines the block cipher mode
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*/
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#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
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/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
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* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
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* working mode.
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* 0: ECB (Electronic Code Block)
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* 1: CBC (Cipher Block Chaining)
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* 2: OFB (Output FeedBack)
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* 3: CTR (Counter)
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* 4: CFB8 (8-bit Cipher FeedBack)
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* 5: CFB128 (128-bit Cipher FeedBack)
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* 6: GCM
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* 7: Reserved
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*/
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#define AES_BLOCK_MODE 0x00000007U
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#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
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#define AES_BLOCK_MODE_V 0x00000007U
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#define AES_BLOCK_MODE_S 0
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/** AES_BLOCK_NUM_REG register
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* Block number configuration register
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*/
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#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
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/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
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* Represents the Block Number of plaintext or ciphertext when the AES accelerator
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* operates under the DMA-AES working mode. For details, see Section . "
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*/
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#define AES_BLOCK_NUM 0xFFFFFFFFU
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#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
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#define AES_BLOCK_NUM_V 0xFFFFFFFFU
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#define AES_BLOCK_NUM_S 0
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/** AES_INC_SEL_REG register
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* Standard incrementing function register
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*/
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#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
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/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
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* Configures the Standard Incrementing Function for CTR block operation.
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* 0: INC_32
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* 1: INC_128
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*/
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#define AES_INC_SEL (BIT(0))
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#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
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#define AES_INC_SEL_V 0x00000001U
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#define AES_INC_SEL_S 0
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/** AES_INT_CLEAR_REG register
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* DMA-AES interrupt clear register
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*/
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#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
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/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
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* Configures whether or not to clear AES interrupt.
|
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* 0: No effect
|
||||
* 1: Clear
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*/
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#define AES_INT_CLEAR (BIT(0))
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#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
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#define AES_INT_CLEAR_V 0x00000001U
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#define AES_INT_CLEAR_S 0
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/** AES_INT_ENA_REG register
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* DMA-AES interrupt enable register
|
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*/
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#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
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/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable AES interrupt.
|
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* 0: Disable
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* 1: Enable
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*/
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#define AES_INT_ENA (BIT(0))
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#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
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#define AES_INT_ENA_V 0x00000001U
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#define AES_INT_ENA_S 0
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||||
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/** AES_DATE_REG register
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* AES version control register
|
||||
*/
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#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
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/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
|
||||
* This bits stores the version information of AES.
|
||||
*/
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#define AES_DATE 0x0FFFFFFFU
|
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#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
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#define AES_DATE_V 0x0FFFFFFFU
|
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#define AES_DATE_S 0
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||||
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/** AES_DMA_EXIT_REG register
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* Operation exit controlling register
|
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*/
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#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
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/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to exit AES operation.
|
||||
* 0: No effect
|
||||
* 1: Exit
|
||||
* Only valid for DMA-AES operation.
|
||||
*/
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#define AES_DMA_EXIT (BIT(0))
|
||||
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
|
||||
#define AES_DMA_EXIT_V 0x00000001U
|
||||
#define AES_DMA_EXIT_S 0
|
||||
|
||||
/** AES_RX_RESET_REG register
|
||||
* AES-DMA reset rx-fifo register
|
||||
*/
|
||||
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
|
||||
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to reset rx_fifo under dma_aes working mode.
|
||||
*/
|
||||
#define AES_RX_RESET (BIT(0))
|
||||
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
|
||||
#define AES_RX_RESET_V 0x00000001U
|
||||
#define AES_RX_RESET_S 0
|
||||
|
||||
/** AES_TX_RESET_REG register
|
||||
* AES-DMA reset tx-fifo register
|
||||
*/
|
||||
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
|
||||
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to reset tx_fifo under dma_aes working mode.
|
||||
*/
|
||||
#define AES_TX_RESET (BIT(0))
|
||||
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
|
||||
#define AES_TX_RESET_V 0x00000001U
|
||||
#define AES_TX_RESET_S 0
|
||||
|
||||
/** AES_PSEUDO_REG register
|
||||
* AES PSEUDO function configure register
|
||||
*/
|
||||
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
|
||||
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
|
||||
* This bit decides whether the pseudo round function is enable or not.
|
||||
*/
|
||||
#define AES_PSEUDO_EN (BIT(0))
|
||||
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
|
||||
#define AES_PSEUDO_EN_V 0x00000001U
|
||||
#define AES_PSEUDO_EN_S 0
|
||||
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
|
||||
* Those bits decides the basic number of pseudo round number.
|
||||
*/
|
||||
#define AES_PSEUDO_BASE 0x0000000FU
|
||||
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
|
||||
#define AES_PSEUDO_BASE_V 0x0000000FU
|
||||
#define AES_PSEUDO_BASE_S 1
|
||||
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
|
||||
* Those bits decides the increment number of pseudo round number
|
||||
*/
|
||||
#define AES_PSEUDO_INC 0x00000003U
|
||||
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
|
||||
#define AES_PSEUDO_INC_V 0x00000003U
|
||||
#define AES_PSEUDO_INC_S 5
|
||||
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
|
||||
* Those bits decides the update frequency of the pseudo-key.
|
||||
*/
|
||||
#define AES_PSEUDO_RNG_CNT 0x00000007U
|
||||
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
|
||||
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
|
||||
#define AES_PSEUDO_RNG_CNT_S 7
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,170 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SHA_MODE_REG register
|
||||
* Configures SHA algorithm
|
||||
*/
|
||||
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
|
||||
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures the SHA algorithm.
|
||||
* 0: SHA-1
|
||||
* 1: SHA-224
|
||||
* 2: SHA-256
|
||||
* 3: SHA2-384
|
||||
* 4: SHA2-512
|
||||
* 5: SHA2-512/224
|
||||
* 6: SHA2-512/256
|
||||
* 7: SHA2-512/t
|
||||
*/
|
||||
#define SHA_MODE 0x00000007U
|
||||
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
|
||||
#define SHA_MODE_V 0x00000007U
|
||||
#define SHA_MODE_S 0
|
||||
|
||||
/** SHA_DMA_BLOCK_NUM_REG register
|
||||
* Block number register (only effective for DMA-SHA)
|
||||
*/
|
||||
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
|
||||
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0;
|
||||
* Configures the DMA-SHA block number.
|
||||
*/
|
||||
#define SHA_DMA_BLOCK_NUM 0x0000FFFFU
|
||||
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
|
||||
#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU
|
||||
#define SHA_DMA_BLOCK_NUM_S 0
|
||||
|
||||
/** SHA_START_REG register
|
||||
* Starts the SHA accelerator for Typical SHA operation
|
||||
*/
|
||||
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
|
||||
/** SHA_START : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to start Typical SHA calculation.
|
||||
*/
|
||||
#define SHA_START (BIT(0))
|
||||
#define SHA_START_M (SHA_START_V << SHA_START_S)
|
||||
#define SHA_START_V 0x00000001U
|
||||
#define SHA_START_S 0
|
||||
|
||||
/** SHA_CONTINUE_REG register
|
||||
* Continues SHA operation (only effective in Typical SHA mode)
|
||||
*/
|
||||
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
|
||||
/** SHA_CONTINUE : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to continue Typical SHA calculation.
|
||||
*/
|
||||
#define SHA_CONTINUE (BIT(0))
|
||||
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
|
||||
#define SHA_CONTINUE_V 0x00000001U
|
||||
#define SHA_CONTINUE_S 0
|
||||
|
||||
/** SHA_BUSY_REG register
|
||||
* Represents if SHA Accelerator is busy or not
|
||||
*/
|
||||
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
|
||||
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
|
||||
* Represents the states of SHA accelerator.
|
||||
* 0: idle
|
||||
* 1: busy
|
||||
*/
|
||||
#define SHA_BUSY_STATE (BIT(0))
|
||||
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
|
||||
#define SHA_BUSY_STATE_V 0x00000001U
|
||||
#define SHA_BUSY_STATE_S 0
|
||||
|
||||
/** SHA_DMA_START_REG register
|
||||
* Starts the SHA accelerator for DMA-SHA operation
|
||||
*/
|
||||
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
|
||||
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to start DMA-SHA calculation.
|
||||
*/
|
||||
#define SHA_DMA_START (BIT(0))
|
||||
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
|
||||
#define SHA_DMA_START_V 0x00000001U
|
||||
#define SHA_DMA_START_S 0
|
||||
|
||||
/** SHA_DMA_CONTINUE_REG register
|
||||
* Continues SHA operation (only effective in DMA-SHA mode)
|
||||
*/
|
||||
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
|
||||
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to continue DMA-SHA calculation.
|
||||
*/
|
||||
#define SHA_DMA_CONTINUE (BIT(0))
|
||||
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
|
||||
#define SHA_DMA_CONTINUE_V 0x00000001U
|
||||
#define SHA_DMA_CONTINUE_S 0
|
||||
|
||||
/** SHA_CLEAR_IRQ_REG register
|
||||
* DMA-SHA interrupt clear register
|
||||
*/
|
||||
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
|
||||
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear DMA-SHA interrupt.
|
||||
*/
|
||||
#define SHA_CLEAR_INTERRUPT (BIT(0))
|
||||
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
|
||||
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
|
||||
#define SHA_CLEAR_INTERRUPT_S 0
|
||||
|
||||
/** SHA_IRQ_ENA_REG register
|
||||
* DMA-SHA interrupt enable register
|
||||
*/
|
||||
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
|
||||
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable DMA-SHA interrupt.
|
||||
*/
|
||||
#define SHA_INTERRUPT_ENA (BIT(0))
|
||||
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
|
||||
#define SHA_INTERRUPT_ENA_V 0x00000001U
|
||||
#define SHA_INTERRUPT_ENA_S 0
|
||||
|
||||
/** SHA_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
|
||||
/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291;
|
||||
* Version control register.
|
||||
*/
|
||||
#define SHA_DATE 0x3FFFFFFFU
|
||||
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
|
||||
#define SHA_DATE_V 0x3FFFFFFFU
|
||||
#define SHA_DATE_S 0
|
||||
|
||||
/** SHA_DMA_RX_RESET_REG register
|
||||
* DMA RX FIFO Reset Signal
|
||||
*/
|
||||
#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30)
|
||||
/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to reset DMA RX FIFO
|
||||
*/
|
||||
#define SHA_DMA_RX_RESET (BIT(0))
|
||||
#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S)
|
||||
#define SHA_DMA_RX_RESET_V 0x00000001U
|
||||
#define SHA_DMA_RX_RESET_S 0
|
||||
|
||||
/** SHA_H_MEM register
|
||||
* Sha H memory which contains intermediate hash or final hash.
|
||||
*/
|
||||
#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
|
||||
#define SHA_H_MEM_SIZE_BYTES 64
|
||||
|
||||
/** SHA_M_MEM register
|
||||
* Sha M memory which contains message.
|
||||
*/
|
||||
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
|
||||
#define SHA_M_MEM_SIZE_BYTES 128
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -12,11 +12,19 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/** SHA_MODE_REG register
|
||||
* Initial configuration register.
|
||||
* Configures SHA algorithm
|
||||
*/
|
||||
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
|
||||
/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* Sha mode.
|
||||
* Configures the SHA algorithm.
|
||||
* 0: SHA-1
|
||||
* 1: SHA-224
|
||||
* 2: SHA-256
|
||||
* 3: SHA2-384
|
||||
* 4: SHA2-512
|
||||
* 5: SHA2-512/224
|
||||
* 6: SHA2-512/256
|
||||
* 7: SHA2-512/t
|
||||
*/
|
||||
#define SHA_MODE 0x00000007U
|
||||
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
|
||||
@@ -39,56 +47,58 @@ extern "C" {
|
||||
* SHA 512/t configuration register 1.
|
||||
*/
|
||||
#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
|
||||
/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
|
||||
/** SHA_T_LENGTH : R/W; bitpos: [6:0]; default: 0;
|
||||
* Sha t_length (used if and only if mode == SHA_512/t).
|
||||
*/
|
||||
#define SHA_T_LENGTH 0x0000003FU
|
||||
#define SHA_T_LENGTH 0x0000007FU
|
||||
#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
|
||||
#define SHA_T_LENGTH_V 0x0000003FU
|
||||
#define SHA_T_LENGTH_V 0x0000007FU
|
||||
#define SHA_T_LENGTH_S 0
|
||||
|
||||
/** SHA_DMA_BLOCK_NUM_REG register
|
||||
* DMA configuration register 0.
|
||||
* Block number register (only effective for DMA-SHA)
|
||||
*/
|
||||
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
|
||||
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
|
||||
* Dma-sha block number.
|
||||
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0;
|
||||
* Configures the DMA-SHA block number.
|
||||
*/
|
||||
#define SHA_DMA_BLOCK_NUM 0x0000003FU
|
||||
#define SHA_DMA_BLOCK_NUM 0x0000FFFFU
|
||||
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
|
||||
#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
|
||||
#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU
|
||||
#define SHA_DMA_BLOCK_NUM_S 0
|
||||
|
||||
/** SHA_START_REG register
|
||||
* Typical SHA configuration register 0.
|
||||
* Starts the SHA accelerator for Typical SHA operation
|
||||
*/
|
||||
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
|
||||
/** SHA_START : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
/** SHA_START : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to start Typical SHA calculation.
|
||||
*/
|
||||
#define SHA_START 0x7FFFFFFFU
|
||||
#define SHA_START (BIT(0))
|
||||
#define SHA_START_M (SHA_START_V << SHA_START_S)
|
||||
#define SHA_START_V 0x7FFFFFFFU
|
||||
#define SHA_START_S 1
|
||||
#define SHA_START_V 0x00000001U
|
||||
#define SHA_START_S 0
|
||||
|
||||
/** SHA_CONTINUE_REG register
|
||||
* Typical SHA configuration register 1.
|
||||
* Continues SHA operation (only effective in Typical SHA mode)
|
||||
*/
|
||||
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
|
||||
/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
|
||||
* Reserved.
|
||||
/** SHA_CONTINUE : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to continue Typical SHA calculation.
|
||||
*/
|
||||
#define SHA_CONTINUE 0x7FFFFFFFU
|
||||
#define SHA_CONTINUE (BIT(0))
|
||||
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
|
||||
#define SHA_CONTINUE_V 0x7FFFFFFFU
|
||||
#define SHA_CONTINUE_S 1
|
||||
#define SHA_CONTINUE_V 0x00000001U
|
||||
#define SHA_CONTINUE_S 0
|
||||
|
||||
/** SHA_BUSY_REG register
|
||||
* Busy register.
|
||||
* Represents if SHA Accelerator is busy or not
|
||||
*/
|
||||
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
|
||||
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
|
||||
* Sha busy state. 1'b0: idle. 1'b1: busy.
|
||||
* Represents the states of SHA accelerator.
|
||||
* 0: idle
|
||||
* 1: busy
|
||||
*/
|
||||
#define SHA_BUSY_STATE (BIT(0))
|
||||
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
|
||||
@@ -96,11 +106,11 @@ extern "C" {
|
||||
#define SHA_BUSY_STATE_S 0
|
||||
|
||||
/** SHA_DMA_START_REG register
|
||||
* DMA configuration register 1.
|
||||
* Starts the SHA accelerator for DMA-SHA operation
|
||||
*/
|
||||
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
|
||||
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
|
||||
* Start dma-sha.
|
||||
* Write 1 to start DMA-SHA calculation.
|
||||
*/
|
||||
#define SHA_DMA_START (BIT(0))
|
||||
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
|
||||
@@ -108,11 +118,11 @@ extern "C" {
|
||||
#define SHA_DMA_START_S 0
|
||||
|
||||
/** SHA_DMA_CONTINUE_REG register
|
||||
* DMA configuration register 2.
|
||||
* Continues SHA operation (only effective in DMA-SHA mode)
|
||||
*/
|
||||
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
|
||||
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
|
||||
* Continue dma-sha.
|
||||
* Write 1 to continue DMA-SHA calculation.
|
||||
*/
|
||||
#define SHA_DMA_CONTINUE (BIT(0))
|
||||
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
|
||||
@@ -120,11 +130,11 @@ extern "C" {
|
||||
#define SHA_DMA_CONTINUE_S 0
|
||||
|
||||
/** SHA_CLEAR_IRQ_REG register
|
||||
* Interrupt clear register.
|
||||
* DMA-SHA interrupt clear register
|
||||
*/
|
||||
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
|
||||
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
|
||||
* Clear sha interrupt.
|
||||
* Write 1 to clear DMA-SHA interrupt.
|
||||
*/
|
||||
#define SHA_CLEAR_INTERRUPT (BIT(0))
|
||||
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
|
||||
@@ -132,11 +142,11 @@ extern "C" {
|
||||
#define SHA_CLEAR_INTERRUPT_S 0
|
||||
|
||||
/** SHA_IRQ_ENA_REG register
|
||||
* Interrupt enable register.
|
||||
* DMA-SHA interrupt enable register
|
||||
*/
|
||||
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
|
||||
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
|
||||
* Write 1 to enable DMA-SHA interrupt.
|
||||
*/
|
||||
#define SHA_INTERRUPT_ENA (BIT(0))
|
||||
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
|
||||
@@ -144,17 +154,29 @@ extern "C" {
|
||||
#define SHA_INTERRUPT_ENA_S 0
|
||||
|
||||
/** SHA_DATE_REG register
|
||||
* Date register.
|
||||
* Version control register
|
||||
*/
|
||||
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
|
||||
/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
|
||||
* Sha date information/ sha version information.
|
||||
/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291;
|
||||
* Version control register.
|
||||
*/
|
||||
#define SHA_DATE 0x3FFFFFFFU
|
||||
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
|
||||
#define SHA_DATE_V 0x3FFFFFFFU
|
||||
#define SHA_DATE_S 0
|
||||
|
||||
/** SHA_DMA_RX_RESET_REG register
|
||||
* DMA RX FIFO Reset Signal
|
||||
*/
|
||||
#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30)
|
||||
/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0;
|
||||
* Write 1 to reset DMA RX FIFO
|
||||
*/
|
||||
#define SHA_DMA_RX_RESET (BIT(0))
|
||||
#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S)
|
||||
#define SHA_DMA_RX_RESET_V 0x00000001U
|
||||
#define SHA_DMA_RX_RESET_S 0
|
||||
|
||||
/** SHA_H_MEM register
|
||||
* Sha H memory which contains intermediate hash or final hash.
|
||||
*/
|
||||
@@ -165,7 +187,7 @@ extern "C" {
|
||||
* Sha M memory which contains message.
|
||||
*/
|
||||
#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
|
||||
#define SHA_M_MEM_SIZE_BYTES 64
|
||||
#define SHA_M_MEM_SIZE_BYTES 128
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user