Merge branch 'ci/enable_esp_timer_eco5' into 'master'

ci(esp_timer): re-enable ci tests for esp-timer on p4 eco5

See merge request espressif/esp-idf!43575

components/esp_timer/test_apps/.build-test-rules.yml

@@ -4,7 +4,3 @@ components/esp_timer/test_apps:
   disable:
     - if: CONFIG_NAME == "dfs" and SOC_CLK_XTAL32K_SUPPORTED != 1
       reason: The test requires the XTAL32K clock to measure the esp_timer timing accuracy
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14420

components/esp_timer/test_apps/pytest_esp_timer_ut.py

@@ -22,7 +22,6 @@ from pytest_embedded_idf.utils import idf_parametrize
     ],
     indirect=['config', 'target'],
 )
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
 def test_esp_timer(dut: Dut) -> None:
     dut.run_all_single_board_cases(timeout=120)
 
@@ -37,7 +36,6 @@ def test_esp_timer(dut: Dut) -> None:
     indirect=True,
 )
 @idf_parametrize('target', ['esp32'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
 def test_esp_timer_psram(dut: Dut) -> None:
     dut.run_all_single_board_cases(timeout=120)