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Merge branch 'ci/enable_esp_event_tests' into 'master'

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ci(core): fixed esp_event and psram freertos not running properly in CI

See merge request espressif/esp-idf!44711
This commit is contained in:
Marius Vikhammer
2026-01-04 10:11:02 +08:00
parent b15334600d 8ce6bd349b
commit 7dfc2f0343
9 changed files with 68 additions and 28 deletions
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17
components/esp_event/test_apps/main/test_event_main.c
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@@ -27,26 +27,32 @@ void setUp(void)
unity_utils_set_leak_level(0);
unity_utils_record_free_mem();
#if SOC_WDT_SUPPORTED
esp_task_wdt_add(NULL);
esp_task_wdt_reset();
#endif
}
void tearDown(void)
{
#ifdef CONFIG_HEAP_TRACING
heap_trace_stop();
heap_trace_dump();
#if SOC_WDT_SUPPORTED
esp_task_wdt_reset();
esp_task_wdt_delete(NULL);
#endif
unity_utils_evaluate_leaks();
esp_task_wdt_reset();
esp_task_wdt_delete(NULL);
#ifdef CONFIG_HEAP_TRACING
heap_trace_stop();
heap_trace_dump();
#endif
}
void app_main(void)
{
#if SOC_WDT_SUPPORTED
// Configure the task watchdog timer to catch any tests that hang
esp_task_wdt_config_t config = {
.timeout_ms = 25 * 1000, // 25 seconds, smaller than the default pytest timeout
@@ -55,6 +61,7 @@ void app_main(void)
};
esp_task_wdt_init(&config);
#endif // SOC_WDT_SUPPORTED
ESP_LOGI(TAG, "Running esp-event test app");
// rand() seems to do a one-time allocation. Call it here so that the memory it allocates

10
components/esp_event/test_apps/main/test_event_target.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@@ -236,7 +236,7 @@ TEST_CASE("can exit running loop at approximately the set amount of time", "[eve
TEST_CASE("can register/unregister handlers simultaneously", "[event]")
{
/* this test aims to verify that the event handlers list remains consistent despite
* simultaneous access by differenct tasks */
* simultaneous access by different tasks */
const char* base = "base";
int32_t id = 0;
@@ -358,7 +358,7 @@ TEST_CASE("can post and run events simultaneously", "[event]")
{
/* this test aims to verify that:
* - multiple tasks can post to the queue simultaneously
* - handlers recieve the appropriate handler arg and associated event data */
* - handlers receive the appropriate handler arg and associated event data */
esp_event_loop_handle_t loop;
@@ -433,7 +433,7 @@ TEST_CASE("can post and run events simultaneously with instances", "[event]")
{
/* this test aims to verify that:
* - multiple tasks can post to the queue simultaneously
* - handlers recieve the appropriate handler arg and associated event data */
* - handlers receive the appropriate handler arg and associated event data */
esp_event_loop_handle_t loop;
@@ -685,7 +685,7 @@ TEST_CASE("data posted from ISR is correctly set internally", "[event][intr]")
TEST_ASSERT_EQUAL(pdTRUE, xQueueReceive(loop_def->queue, &post, portMAX_DELAY));
TEST_ASSERT_EQUAL(true, post.data_set);
TEST_ASSERT_EQUAL(false, post.data_allocated);
TEST_ASSERT_EQUAL(false, post.data.val);
TEST_ASSERT_EQUAL(0, *(int*)post.data.val);
TEST_ESP_OK(esp_event_loop_delete(loop));

29
components/esp_event/test_apps/pytest_esp_event.py
View File

@@ -7,6 +7,14 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize('target', ['esp32', 'esp32s2', 'esp32c3'], indirect=['target'])
@pytest.mark.parametrize(
'config',
[
'defaults',
'no_isr_post',
],
indirect=True,
)
def test_esp_event(dut: Dut) -> None:
dut.run_all_single_board_cases()
@@ -14,6 +22,13 @@ def test_esp_event(dut: Dut) -> None:
@pytest.mark.host_test
@pytest.mark.qemu
@pytest.mark.xfail('config.getvalue("target") == "esp32c3"', reason='Unstable on QEMU, needs investigation')
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
@idf_parametrize('target', ['esp32', 'esp32c3'], indirect=['target'])
def test_esp_event_qemu(dut: Dut) -> None:
for case in dut.test_menu:
@@ -23,6 +38,13 @@ def test_esp_event_qemu(dut: Dut) -> None:
@pytest.mark.host_test
@idf_parametrize('target', ['linux'], indirect=['target'])
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
def test_esp_event_posix_simulator(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests.')
dut.write('*')
@@ -31,6 +53,13 @@ def test_esp_event_posix_simulator(dut: Dut) -> None:
@pytest.mark.generic
@idf_parametrize('target', ['esp32'], indirect=['target'])
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
def test_esp_event_profiling(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests.')
dut.write('"profiling reports valid values"')

0
components/esp_event/test_apps/sdkconfig.ci.defaults Normal file
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3
components/esp_event/test_apps/sdkconfig.ci.no_isr_post
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@@ -1,3 +1,2 @@
# This configuration checks the event loop if posting from ISR is disabled
CONFIG_ESP_TASK_WDT_INIT=n
CONFIG_POST_EVENTS_FROM_ISR=n
CONFIG_ESP_EVENT_POST_FROM_ISR=n

14
components/esp_libc/test_apps/newlib/main/test_app_main.c
View File

@@ -1,7 +1,7 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: CC0-1.0
* SPDX-License-Identifier: Apache-2.0
*/
#include "freertos/FreeRTOS.h"
@@ -29,26 +29,31 @@ void setUp(void)
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
#if SOC_WDT_SUPPORTED
esp_task_wdt_add(NULL);
esp_task_wdt_reset();
#endif
}
void tearDown(void)
{
#if SOC_WDT_SUPPORTED
esp_task_wdt_reset();
esp_task_wdt_delete(NULL);
#endif
// Add a short delay of 10ms to allow the idle task to free an remaining memory
vTaskDelay(pdMS_TO_TICKS(10));
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
esp_task_wdt_reset();
esp_task_wdt_delete(NULL);
}
void app_main(void)
{
#if SOC_WDT_SUPPORTED
// Configure the task watchdog timer to catch any tests that hang
esp_task_wdt_config_t config = {
.timeout_ms = 25 * 1000, // 25 seconds, smaller than the default pytest timeout
@@ -57,6 +62,7 @@ void app_main(void)
};
esp_task_wdt_init(&config);
#endif // SOC_WDT_SUPPORTED
// Raise priority to main task as some tests depend on the test task being at priority UNITY_FREERTOS_PRIORITY
vTaskPrioritySet(NULL, UNITY_FREERTOS_PRIORITY);

1
components/freertos/test_apps/.build-test-rules.yml
View File

@@ -20,3 +20,4 @@ components/freertos/test_apps/freertos:
- if: IDF_TARGET in ["esp32s31"]
temporary: true
reason: not support yet # TODO: [ESP32S31] IDF-14685
- if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1

12
components/freertos/test_apps/freertos/main/test_freertos_main.c
View File

@@ -29,27 +29,32 @@ void setUp(void)
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
#if SOC_WDT_SUPPORTED
esp_task_wdt_add(NULL);
esp_task_wdt_reset();
#endif
}
void tearDown(void)
{
#if SOC_WDT_SUPPORTED
esp_task_wdt_reset();
esp_task_wdt_delete(NULL);
#endif
// Add a short delay of 10ms to allow the idle task to free an remaining memory
vTaskDelay(pdMS_TO_TICKS(10));
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
esp_task_wdt_reset();
esp_task_wdt_delete(NULL);
}
void app_main(void)
{
#if SOC_WDT_SUPPORTED
// Configure the task watchdog timer to catch any tests that hang
esp_task_wdt_config_t config = {
.timeout_ms = 25 * 1000, // 25 seconds, smaller than the default pytest timeout
@@ -58,6 +63,7 @@ void app_main(void)
};
esp_task_wdt_init(&config);
#endif // SOC_WDT_SUPPORTED
/*
Some FreeRTOS tests are reliant on the main task being at priority UNITY_FREERTOS_PRIORITY to test scheduling

10
components/freertos/test_apps/freertos/sdkconfig.ci.psram
View File

@@ -1,13 +1,5 @@
# Test configuration for using FreeRTOS with PSRAM enabled. Only tested on the ESP32
CONFIG_IDF_TARGET="esp32"
# Test configuration for using FreeRTOS with PSRAM enabled.
# Enable SPIRAM
CONFIG_SPIRAM=y
CONFIG_SPIRAM_OCCUPY_NO_HOST=y
CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
# Disable encrypted flash reads/writes to save IRAM in this build configuration
CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=n
CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y