feat(esp_hw_support): update pmu support for esp32p4 v3.0

components/esp_hw_support/port/esp32p4/pmu_init.c

@@ -132,6 +132,7 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
         PMU_HP_PD_TOP,
         PMU_HP_PD_CNNT,
         PMU_HP_PD_HPMEM,
+        PMU_HP_PD_CPU
     };
 
     for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -159,7 +159,9 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
     )
 {
     pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
-
+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+    power_default.hp_sys.dig_power.cpu_pd_en = (sleep_flags & PMU_SLEEP_PD_CPU) ? 1 : 0;
+#endif
     if (dslp) {
         config->param.lp_sys.analog_wait_target_cycle  = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
 

components/esp_hw_support/port/esp32p4/private_include/pmu_param.h

@@ -34,7 +34,7 @@ extern "C" {
 // FOR LIGHTSLEEP
 #define PMU_HP_DRVB_LIGHTSLEEP      0
 #define PMU_LP_DRVB_LIGHTSLEEP      0
-#define PMU_HP_XPD_LIGHTSLEEP       1
+#define PMU_HP_XPD_LIGHTSLEEP       0 // Always use DCDC power supply in lightsleep
 
 #define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT    0
 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1
@@ -118,7 +118,12 @@ typedef union {
         uint32_t dcdc_switch_pd_en: 1;
         uint32_t mem_dslp     : 1;
         uint32_t mem_pd_en    : 1;
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
         uint32_t reserved1    : 6;
+#else
+        uint32_t reserved1    : 5;
+        uint32_t cpu_pd_en    : 1;
+#endif
         uint32_t cnnt_pd_en   : 1;
         uint32_t top_pd_en    : 1;
     };

components/hal/esp32p4/include/hal/pmu_ll.h

@@ -379,32 +379,68 @@ FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_a
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
 {
-    hw->power.hp_pd[domain].force_reset = rst;
+    if (domain == PMU_HP_PD_CPU) {
+#if SOC_PMU_STRUCT_HW_VER >= 3
+        hw->power_pd_hp_cpu_cntl.force_hp_cpu_reset = rst;
+#endif
+    } else {
+        hw->power.hp_pd[domain].force_reset = rst;
+    }
 }
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
 {
-    hw->power.hp_pd[domain].force_iso = iso;
+    if (domain == PMU_HP_PD_CPU) {
+#if SOC_PMU_STRUCT_HW_VER >= 3
+        hw->power_pd_hp_cpu_cntl.force_hp_cpu_iso = iso;
+#endif
+    } else {
+        hw->power.hp_pd[domain].force_iso = iso;
+    }
 }
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
 {
-    hw->power.hp_pd[domain].force_pu = fpu;
+    if (domain == PMU_HP_PD_CPU) {
+#if SOC_PMU_STRUCT_HW_VER >= 3
+        hw->power_pd_hp_cpu_cntl.force_hp_cpu_pu = fpu;
+#endif
+    } else {
+        hw->power.hp_pd[domain].force_pu = fpu;
+    }
 }
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
 {
-    hw->power.hp_pd[domain].force_no_reset = no_rst;
+    if (domain == PMU_HP_PD_CPU) {
+#if SOC_PMU_STRUCT_HW_VER >= 3
+        hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_reset = no_rst;
+#endif
+    } else {
+        hw->power.hp_pd[domain].force_no_reset = no_rst;
+    }
 }
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
 {
-    hw->power.hp_pd[domain].force_no_iso = no_iso;
+    if (domain == PMU_HP_PD_CPU) {
+#if SOC_PMU_STRUCT_HW_VER >= 3
+        hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_iso = no_iso;
+#endif
+    } else {
+        hw->power.hp_pd[domain].force_no_iso = no_iso;
+    }
 }
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
 {
-    hw->power.hp_pd[domain].force_pd = fpd;
+    if (domain == PMU_HP_PD_CPU) {
+#if SOC_PMU_STRUCT_HW_VER >= 3
+        hw->power_pd_hp_cpu_cntl.force_hp_cpu_pd = fpd;
+#endif
+    } else {
+        hw->power.hp_pd[domain].force_pd = fpd;
+    }
 }
 
 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)

components/hal/include/hal/pmu_types.h

@@ -41,6 +41,7 @@ typedef enum {
     PMU_HP_PD_TOP = 0,      /*!< Power domain of digital top */
     PMU_HP_PD_CNNT = 1,     /*!< Power domain of high-speed IO peripherals such as USB/SDIO/Ethernet etc.*/
     PMU_HP_PD_HPMEM = 2,
+    PMU_HP_PD_CPU = 3,
 } pmu_hp_power_domain_t;
 #else
 typedef enum {

components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h

@@ -6,7 +6,7 @@
 #pragma once
 
 #include <stdint.h>
-#include "soc/pmu_reg.h"
+#include "pmu_reg.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h

@@ -6,7 +6,7 @@
 #pragma once
 
 #include <stdint.h>
-#include "soc/pmu_reg.h"
+#include "pmu_reg.h"
 #ifdef __cplusplus
 extern "C" {
 #endif