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Merge branch 'feat/esp_hal_isp' into 'master'

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isp: move isp hal to cam hal

Closes IDF-14107

See merge request espressif/esp-idf!43907
This commit is contained in:
Armando (Dou Yiwen)
2025-12-11 07:41:58 +00:00
parent 1315eeb98b 39e2bfe334
commit 90187ea057
29 changed files with 161 additions and 168 deletions
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30
components/esp_driver_cam/isp_dvp/include/esp_cam_ctlr_isp_dvp.h
View File

@@ -16,26 +16,28 @@
extern "C" {
#endif
#define ESP_CAM_CTLR_ISP_DVP_DATA_SIG_NUM_MAX 16
/**
* @brief ESP CAM ISP DVP controller configurations.
*/
typedef struct {
cam_ctlr_data_width_t data_width; /*!< Number of data lines. */
int data_io[ISP_DVP_DATA_SIG_NUM]; /*!< ISP DVP data-in IO numbers. */
int pclk_io; /*!< ISP DVP pclk IO number. */
int hsync_io; /*!< ISP DVP hsync IO number. */
int vsync_io; /*!< ISP DVP vsync IO number. */
int de_io; /*!< ISP DVP de IO number. */
cam_ctlr_data_width_t data_width; /*!< Number of data lines. */
int data_io[ESP_CAM_CTLR_ISP_DVP_DATA_SIG_NUM_MAX]; /*!< ISP DVP data-in IO numbers. */
int pclk_io; /*!< ISP DVP pclk IO number. */
int hsync_io; /*!< ISP DVP hsync IO number. */
int vsync_io; /*!< ISP DVP vsync IO number. */
int de_io; /*!< ISP DVP de IO number. */
struct {
uint32_t pclk_invert: 1; /*!< Set to 1 to invert the pclk signal. */
uint32_t hsync_invert: 1; /*!< Set to 1 to invert the hsync signal (i.e., active low). */
uint32_t vsync_invert: 1; /*!< Set to 1 to invert the vsync signal (i.e., active high). */
uint32_t de_invert: 1; /*!< Set to 1 to invert the de signal (i.e., active low). */
} io_flags; /*!< ISP DVP IO flags. */
int queue_items; /*!< Queue items. */
uint32_t pclk_invert: 1; /*!< Set to 1 to invert the pclk signal. */
uint32_t hsync_invert: 1; /*!< Set to 1 to invert the hsync signal (i.e., active low). */
uint32_t vsync_invert: 1; /*!< Set to 1 to invert the vsync signal (i.e., active high). */
uint32_t de_invert: 1; /*!< Set to 1 to invert the de signal (i.e., active low). */
} io_flags; /*!< ISP DVP IO flags. */
int queue_items; /*!< Queue items. */
struct {
uint32_t byte_swap_en : 1; /*!< Set to 1 to enable byte swap. */
uint32_t bk_buffer_dis : 1; /*!< Set to 1 to disable backup buffer. */
uint32_t byte_swap_en : 1; /*!< Set to 1 to enable byte swap. */
uint32_t bk_buffer_dis : 1; /*!< Set to 1 to disable backup buffer. */
};
} esp_cam_ctlr_isp_dvp_cfg_t;

4
components/esp_driver_cam/isp_dvp/src/esp_cam_ctlr_isp_dvp.c
View File

@@ -66,7 +66,7 @@ typedef struct isp_dvp_controller_t {
typedef struct isp_dvp_ctx_t {
_lock_t mutex;
isp_dvp_controller_t *dvp_ctlr[SOC_ISP_DVP_CTLR_NUMS];
isp_dvp_controller_t *dvp_ctlr[ISP_LL_DVP_CTLR_NUMS];
} isp_dvp_ctx_t;
static const char *TAG = "ISP_DVP";
@@ -572,7 +572,7 @@ static esp_err_t s_isp_claim_dvp_controller(isp_proc_handle_t isp_proc, isp_dvp_
_lock_acquire(&s_ctx.mutex);
bool found = false;
for (int i = 0; i < SOC_ISP_DVP_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_DVP_CTLR_NUMS; i++) {
found = !s_ctx.dvp_ctlr[i];
if (found) {
s_ctx.dvp_ctlr[i] = dvp_ctlr;

9
components/esp_driver_cam/test_apps/isp_dvp/main/test_isp_dvp_driver.c
View File

@@ -9,6 +9,7 @@
#include "esp_cam_ctlr_isp_dvp.h"
#include "esp_cam_ctlr.h"
#include "driver/isp.h"
#include "hal/isp_ll.h"
TEST_CASE("ISP DVP controller exhausted allocation", "[isp]")
{
@@ -35,14 +36,14 @@ TEST_CASE("ISP DVP controller exhausted allocation", "[isp]")
.io_flags.vsync_invert = 1,
.queue_items = 10,
};
esp_cam_ctlr_handle_t dvp_ctrlr[SOC_ISP_DVP_CTLR_NUMS + 1] = {};
for (int i = 0; i < SOC_ISP_DVP_CTLR_NUMS; i++) {
esp_cam_ctlr_handle_t dvp_ctrlr[ISP_LL_DVP_CTLR_NUMS + 1] = {};
for (int i = 0; i < ISP_LL_DVP_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_cam_new_isp_dvp_ctlr(isp_proc, &dvp_ctlr_config, &dvp_ctrlr[i]));
}
TEST_ASSERT(esp_cam_new_isp_dvp_ctlr(isp_proc, &dvp_ctlr_config, &dvp_ctrlr[SOC_ISP_DVP_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
TEST_ASSERT(esp_cam_new_isp_dvp_ctlr(isp_proc, &dvp_ctlr_config, &dvp_ctrlr[ISP_LL_DVP_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
for (int i = 0; i < SOC_ISP_DVP_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_DVP_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_cam_ctlr_del(dvp_ctrlr[i]));
}
TEST_ESP_OK(esp_isp_del_processor(isp_proc));

2
components/esp_driver_isp/CMakeLists.txt
View File

@@ -6,7 +6,7 @@ set(public_include "include")
set(priv_requires "esp_driver_gpio")
set(requires)
set(requires "esp_hal_cam")
if(CONFIG_SOC_ISP_SUPPORTED)
list(APPEND srcs "src/isp_core.c"

3
components/esp_driver_isp/include/driver/isp_ccm.h
View File

@@ -26,6 +26,9 @@ typedef struct {
* When saturation is true, and final value will be limited to 4.0, and won't rise error
* When saturation is false, `esp_isp_ccm_configure` will rise ESP_ERR_INVALID_ARG error
*/
struct {
uint32_t update_once_configured : 1; ///< If set, apply configuration to hardware immediately; otherwise defer to frame boundary
} flags; ///< Driver behaviour flags
} esp_isp_ccm_config_t;
/**

4
components/esp_driver_isp/include/esp_private/isp_private.h
View File

@@ -23,7 +23,7 @@
#include "hal/isp_hal.h"
#include "hal/isp_ll.h"
#include "hal/isp_types.h"
#include "soc/isp_periph.h"
#include "hal/isp_periph.h"
#endif
// Helper macros for atomic operations to ensure Clang compatibility
@@ -75,7 +75,7 @@ typedef struct isp_processor_t {
color_raw_element_order_t bayer_order;
bool bypass_isp;
/* sub module contexts */
isp_af_ctlr_t af_ctlr[SOC_ISP_AF_CTLR_NUMS];
isp_af_ctlr_t af_ctlr[ISP_LL_AF_CTLR_NUMS];
isp_awb_ctlr_t awb_ctlr;
isp_ae_ctlr_t ae_ctlr;
isp_hist_ctlr_t hist_ctlr;

4
components/esp_driver_isp/src/isp_af.c
View File

@@ -38,7 +38,7 @@ static esp_err_t s_isp_claim_af_controller(isp_proc_handle_t isp_proc, isp_af_ct
bool found = false;
esp_os_enter_critical(&isp_proc->spinlock);
for (int i = 0; i < SOC_ISP_AF_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_AF_CTLR_NUMS; i++) {
found = !isp_proc->af_ctlr[i];
if (found) {
isp_proc->af_ctlr[i] = af_ctlr;
@@ -145,7 +145,7 @@ esp_err_t esp_isp_del_af_controller(isp_af_ctlr_t af_ctlr)
ESP_RETURN_ON_FALSE(af_ctlr && af_ctlr->isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
ESP_RETURN_ON_FALSE(atomic_load(&af_ctlr->fsm) == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "controller not in init state");
bool exist = false;
for (int i = 0; i < SOC_ISP_AF_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_AF_CTLR_NUMS; i++) {
if (af_ctlr->isp_proc->af_ctlr[i] == af_ctlr) {
exist = true;
break;

2
components/esp_driver_isp/src/isp_ccm.c
View File

@@ -37,7 +37,7 @@ esp_err_t esp_isp_ccm_configure(isp_proc_handle_t proc, const esp_isp_ccm_config
esp_os_enter_critical(&proc->spinlock);
isp_ll_ccm_set_clk_ctrl_mode(proc->hal.hw, ISP_LL_PIPELINE_CLK_CTRL_AUTO);
ret = isp_hal_ccm_set_matrix(&proc->hal, ccm_cfg->saturation, ccm_cfg->matrix);
valid = isp_ll_shadow_update_ccm(proc->hal.hw);
valid = isp_ll_shadow_update_ccm(proc->hal.hw, ccm_cfg->flags.update_once_configured);
esp_os_exit_critical(&proc->spinlock);
ESP_RETURN_ON_FALSE(ret, ESP_ERR_INVALID_ARG, TAG, "invalid argument: ccm matrix contain NaN or out of range");
ESP_RETURN_ON_FALSE(valid, ESP_ERR_INVALID_STATE, TAG, "failed to update ccm shadow register");

2
components/esp_driver_isp/src/isp_color.c
View File

@@ -12,7 +12,7 @@
#include "freertos/FreeRTOS.h"
#include "driver/isp_core.h"
#include "driver/isp_color.h"
#include "soc/isp_periph.h"
#include "hal/isp_periph.h"
#include "esp_private/isp_private.h"
static const char *TAG = "ISP_COLOR";

6
components/esp_driver_isp/src/isp_core.c
View File

@@ -19,7 +19,7 @@
#include "hal/hal_utils.h"
#include "hal/color_hal.h"
#include "soc/mipi_csi_bridge_struct.h"
#include "soc/isp_periph.h"
#include "hal/isp_periph.h"
#include "soc/soc_caps.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/isp_private.h"
@@ -28,7 +28,7 @@
typedef struct isp_platform_t {
_lock_t mutex;
isp_processor_t *processors[SOC_ISP_NUMS];
isp_processor_t *processors[ISP_LL_PERIPH_NUMS];
} isp_platform_t;
static const char *TAG = "ISP";
@@ -40,7 +40,7 @@ static esp_err_t s_isp_claim_processor(isp_processor_t *proc)
_lock_acquire(&s_platform.mutex);
bool found = false;
for (int i = 0; i < SOC_ISP_NUMS; i ++) {
for (int i = 0; i < ISP_LL_PERIPH_NUMS; i ++) {
found = !s_platform.processors[i];
if (found) {
s_platform.processors[i] = proc;

2
components/esp_driver_isp/src/isp_demosaic.c
View File

@@ -12,7 +12,7 @@
#include "freertos/FreeRTOS.h"
#include "driver/isp_core.h"
#include "driver/isp_demosaic.h"
#include "soc/isp_periph.h"
#include "hal/isp_periph.h"
#include "esp_private/isp_private.h"
static const char *TAG = "ISP_DEMOSAIC";

2
components/esp_driver_isp/src/isp_sharpen.c
View File

@@ -12,7 +12,7 @@
#include "freertos/FreeRTOS.h"
#include "driver/isp_core.h"
#include "driver/isp_sharpen.h"
#include "soc/isp_periph.h"
#include "hal/isp_periph.h"
#include "esp_private/isp_private.h"
static const char *TAG = "ISP_SHARPEN";

42
components/esp_driver_isp/test_apps/isp/main/test_isp_driver.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include "unity.h"
#include "driver/isp.h"
#include "soc/soc_caps.h"
#include "hal/isp_ll.h"
/*---------------------------------------------------------------
ISP
@@ -21,15 +22,15 @@ TEST_CASE("ISP processor exhausted allocation", "[isp]")
.input_data_color_type = ISP_COLOR_RAW8,
.output_data_color_type = ISP_COLOR_RGB565,
};
isp_proc_handle_t isp_proc[SOC_ISP_NUMS + 1] = {};
isp_proc_handle_t isp_proc[ISP_LL_PERIPH_NUMS + 1] = {};
for (int i = 0; i < SOC_ISP_NUMS; i++) {
for (int i = 0; i < ISP_LL_PERIPH_NUMS; i++) {
TEST_ESP_OK(esp_isp_new_processor(&isp_config, &isp_proc[i]));
}
TEST_ASSERT(esp_isp_new_processor(&isp_config, &isp_proc[SOC_ISP_NUMS]) == ESP_ERR_NOT_FOUND);
TEST_ASSERT(esp_isp_new_processor(&isp_config, &isp_proc[ISP_LL_PERIPH_NUMS]) == ESP_ERR_NOT_FOUND);
for (int i = 0; i < SOC_ISP_NUMS; i++) {
for (int i = 0; i < ISP_LL_PERIPH_NUMS; i++) {
TEST_ESP_OK(esp_isp_del_processor(isp_proc[i]));
}
}
@@ -117,14 +118,14 @@ TEST_CASE("ISP AF controller exhausted allocation", "[isp]")
esp_isp_af_config_t af_config = {
.edge_thresh = 128,
};
isp_af_ctlr_t af_ctrlr[SOC_ISP_AF_CTLR_NUMS + 1] = {};
for (int i = 0; i < SOC_ISP_AF_CTLR_NUMS; i++) {
isp_af_ctlr_t af_ctrlr[ISP_LL_AF_CTLR_NUMS + 1] = {};
for (int i = 0; i < ISP_LL_AF_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr[i]));
}
TEST_ASSERT(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr[SOC_ISP_AF_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
TEST_ASSERT(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr[ISP_LL_AF_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
for (int i = 0; i < SOC_ISP_AF_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_AF_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_isp_del_af_controller(af_ctrlr[i]));
}
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
@@ -210,15 +211,20 @@ TEST_CASE("ISP CCM basic function", "[isp]")
esp_isp_ccm_config_t ccm_cfg = {
.matrix = {
{5.0, 0.0, 0.0},
{16.0, 0.0, 0.0},
{0.0, 1.0, 0.0},
{0.0, 0.0, 1.0}
},
.saturation = false,
.flags = {
.update_once_configured = true,
},
};
// Out of range case
TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_isp_ccm_configure(isp_proc, &ccm_cfg));
// saturation case
ccm_cfg.matrix[0][0] = 5.0;
ccm_cfg.saturation = true;
TEST_ESP_OK(esp_isp_ccm_configure(isp_proc, &ccm_cfg));
TEST_ESP_OK(esp_isp_ccm_enable(isp_proc));
@@ -315,14 +321,14 @@ TEST_CASE("ISP AE controller exhausted allocation", "[isp]")
esp_isp_ae_config_t ae_config = {
.sample_point = ISP_AE_SAMPLE_POINT_AFTER_DEMOSAIC,
};
isp_ae_ctlr_t ae_ctrlr[SOC_ISP_AE_CTLR_NUMS + 1] = {};
for (int i = 0; i < SOC_ISP_AE_CTLR_NUMS; i++) {
isp_ae_ctlr_t ae_ctrlr[ISP_LL_AE_CTLR_NUMS + 1] = {};
for (int i = 0; i < ISP_LL_AE_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctrlr[i]));
}
TEST_ASSERT(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctrlr[SOC_ISP_AE_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
TEST_ASSERT(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctrlr[ISP_LL_AE_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
for (int i = 0; i < SOC_ISP_AE_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_AE_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_isp_del_ae_controller(ae_ctrlr[i]));
}
TEST_ESP_OK(esp_isp_del_processor(isp_proc));
@@ -436,14 +442,14 @@ TEST_CASE("ISP HIST controller exhausted allocation", "[isp]")
},
};
isp_hist_ctlr_t hist_ctlr[SOC_ISP_HIST_CTLR_NUMS + 1] = {};
for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) {
isp_hist_ctlr_t hist_ctlr[ISP_LL_HIST_CTLR_NUMS + 1] = {};
for (int i = 0; i < ISP_LL_HIST_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[i]));
}
TEST_ASSERT(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[SOC_ISP_HIST_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
TEST_ASSERT(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr[ISP_LL_HIST_CTLR_NUMS]) == ESP_ERR_NOT_FOUND);
for (int i = 0; i < SOC_ISP_HIST_CTLR_NUMS; i++) {
for (int i = 0; i < ISP_LL_HIST_CTLR_NUMS; i++) {
TEST_ESP_OK(esp_isp_del_hist_controller(hist_ctlr[i]));
}
TEST_ESP_OK(esp_isp_del_processor(isp_proc));

12
components/esp_driver_isp/test_apps/isp/pytest_isp.py
View File

@@ -1,7 +1,13 @@
# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
from pytest_embedded_idf import IdfDut
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
def test_isp(dut: IdfDut) -> None:
@pytest.mark.camera
@pytest.mark.ov5647
@idf_parametrize('target', soc_filtered_targets('SOC_ISP_SUPPORTED == 1'), indirect=['target'])
def test_isp(dut: Dut) -> None:
dut.run_all_single_board_cases()

6
components/esp_hal_cam/CMakeLists.txt
View File

@@ -22,6 +22,12 @@ if(CONFIG_SOC_MIPI_CSI_SUPPORTED)
list(APPEND srcs "${target}/mipi_csi_periph.c")
endif()
# ISP related source files
if(CONFIG_SOC_ISP_SUPPORTED)
list(APPEND srcs "isp_hal.c")
list(APPEND srcs "${target}/isp_periph.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include}
REQUIRES soc hal)

5
components/esp_hal_cam/README.md
View File

@@ -2,7 +2,10 @@
⚠️ This HAL component is still under heavy development at the moment, so we don't guarantee the stability and backward-compatibility among versions.
The `esp_hal_cam` component provides a **Hardware Abstraction Layer** of Camera Controller for all targets supported by ESP-IDF.
The `esp_hal_cam` component provides a **Hardware Abstraction Layer** for
- Camera Controller
- Image Signal Processor (ISP)
for all targets supported by ESP-IDF.
In a broad sense, the HAL layer consists of two sub-layers: HAL (upper) and Low-Level(bottom). The HAL layer defines the steps and data that is required to operate a peripheral (e.g. initialization, parameter settings). The low-level is a translation layer above the register files under the `soc` component, it only covers general conceptions to register configurations.

63
components/hal/esp32p4/include/hal/isp_ll.h → components/esp_hal_cam/esp32p4/include/hal/isp_ll.h
View File

@@ -24,8 +24,8 @@
extern "C" {
#endif
#define ISP_LL_GET_HW(num) (((num) == 0) ? (&ISP) : NULL)
#define ISP_LL_PERIPH_NUMS 1U
#define ISP_LL_HSIZE_MAX 1920
#define ISP_LL_VSIZE_MAX 1080
@@ -35,7 +35,6 @@ extern "C" {
---------------------------------------------------------------*/
#define ISP_LL_TX_MAX_CLK_INT_DIV 0x100
/*---------------------------------------------------------------
INTR
---------------------------------------------------------------*/
@@ -87,11 +86,13 @@ extern "C" {
/*---------------------------------------------------------------
AF
---------------------------------------------------------------*/
#define ISP_LL_AF_CTLR_NUMS 1U
#define ISP_LL_AF_WINDOW_MAX_RANGE ((1<<12) - 1)
/*---------------------------------------------------------------
AE
---------------------------------------------------------------*/
#define ISP_LL_AE_CTLR_NUMS 1U
#define ISP_LL_AE_WINDOW_MAX_RANGE ((1<<12) - 1)
/*---------------------------------------------------------------
@@ -110,6 +111,8 @@ extern "C" {
/*---------------------------------------------------------------
DVP
---------------------------------------------------------------*/
#define ISP_LL_DVP_CTLR_NUMS 1U
#define ISP_LL_DVP_DATA_WIDTH_MAX 16
#define ISP_LL_DVP_DATA_TYPE_RAW8 0x2A
#define ISP_LL_DVP_DATA_TYPE_RAW10 0x2B
#define ISP_LL_DVP_DATA_TYPE_RAW12 0x2C
@@ -141,6 +144,11 @@ extern "C" {
#endif
#define ISP_LL_CCM_MATRIX_TOT_BITS (ISP_LL_CCM_MATRIX_INT_BITS + ISP_LL_CCM_MATRIX_FRAC_BITS + 1) // including one sign bit
/*---------------------------------------------------------------
CCM
---------------------------------------------------------------*/
#define ISP_LL_HIST_CTLR_NUMS 1U
typedef union {
struct {
uint32_t fraction: ISP_LL_AWB_RGB_RATIO_FRAC_BITS;
@@ -226,7 +234,6 @@ typedef enum {
ISP_LL_CROP_ERR_Y_START_ODD = (1 << 5), /*!< Y start coordinate is odd (should be even) */
} isp_ll_crop_error_t;
/*---------------------------------------------------------------
Clock
---------------------------------------------------------------*/
@@ -395,7 +402,7 @@ static inline bool isp_ll_set_input_data_color_format(isp_dev_t *hw, color_space
bool valid = false;
if (format.color_space == COLOR_SPACE_RAW) {
switch(format.pixel_format) {
switch (format.pixel_format) {
case COLOR_PIXEL_RAW8:
hw->cntl.isp_data_type = 0;
valid = true;
@@ -451,7 +458,7 @@ static inline bool isp_ll_set_output_data_color_format(isp_dev_t *hw, color_spac
bool valid = false;
if (format.color_space == COLOR_SPACE_RAW) {
switch(format.pixel_format) {
switch (format.pixel_format) {
case COLOR_PIXEL_RAW8:
hw->cntl.isp_out_type = 0;
hw->cntl.demosaic_en = 0;
@@ -463,7 +470,7 @@ static inline bool isp_ll_set_output_data_color_format(isp_dev_t *hw, color_spac
break;
}
} else if (format.color_space == COLOR_SPACE_RGB) {
switch(format.pixel_format) {
switch (format.pixel_format) {
case COLOR_PIXEL_RGB888:
hw->cntl.isp_out_type = 2;
hw->cntl.demosaic_en = 1;
@@ -482,7 +489,7 @@ static inline bool isp_ll_set_output_data_color_format(isp_dev_t *hw, color_spac
break;
}
} else if (format.color_space == COLOR_SPACE_YUV) {
switch(format.pixel_format) {
switch (format.pixel_format) {
case COLOR_PIXEL_YUV422:
hw->cntl.isp_out_type = 1;
hw->cntl.demosaic_en = 1;
@@ -1146,7 +1153,7 @@ static inline bool isp_ll_dvp_set_data_type(isp_dev_t *hw, color_space_pixel_for
bool valid = false;
if (format.color_space == COLOR_SPACE_RAW) {
switch(format.pixel_format) {
switch (format.pixel_format) {
case COLOR_PIXEL_RAW8:
hw->cam_conf.cam_data_type = ISP_LL_DVP_DATA_TYPE_RAW8;
valid = true;
@@ -1329,7 +1336,7 @@ static inline void isp_ll_ae_set_window_range(isp_dev_t *hw, int x_start, int x_
*/
static inline int isp_ll_ae_get_block_mean_lum(isp_dev_t *hw, int block_id)
{
HAL_ASSERT(block_id >=0 && block_id < (SOC_ISP_AE_BLOCK_X_NUMS * SOC_ISP_AE_BLOCK_Y_NUMS));
HAL_ASSERT(block_id >= 0 && block_id < (SOC_ISP_AE_BLOCK_X_NUMS * SOC_ISP_AE_BLOCK_Y_NUMS));
return hw->ae_block_mean[block_id / 4].ae_b_mean[3 - (block_id % 4)];
}
@@ -1558,7 +1565,7 @@ static inline uint32_t isp_ll_get_intr_status(isp_dev_t *hw)
*/
static inline uint32_t isp_ll_get_intr_status_reg_addr(isp_dev_t *hw)
{
return (uint32_t)&(hw->int_st);
return (uint32_t) & (hw->int_st);
}
/**
@@ -1987,21 +1994,27 @@ static inline bool isp_ll_shadow_update_wbg(isp_dev_t *hw)
/**
* @brief Update CCM shadow register
*
* @param[in] hw Hardware instance address
* @param[in] hw Hardware instance address
* @param[in] force_update Force update
* @return
* - True if update is successful, False otherwise
*/
static inline bool isp_ll_shadow_update_ccm(isp_dev_t *hw)
static inline bool isp_ll_shadow_update_ccm(isp_dev_t *hw, bool force_update)
{
//only valid when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
HAL_ASSERT(hw->shadow_reg_ctrl.shadow_update_sel == ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC);
if (hw->shadow_reg_ctrl.ccm_update == 1) {
return false;
}
if (force_update) {
//don't care shadow register
hw->shadow_reg_ctrl.ccm_update = 1;
} else {
if (hw->shadow_reg_ctrl.ccm_update == 1) {
return false;
}
//self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
hw->shadow_reg_ctrl.ccm_update = 1;
//self clear when ISP_SHADOW_MODE_UPDATE_ONLY_NEXT_VSYNC
hw->shadow_reg_ctrl.ccm_update = 1;
}
return true;
}
@@ -2531,8 +2544,8 @@ static inline void isp_ll_crop_enable(isp_dev_t *hw, bool enable)
* @param[in] y_end Crop end y coordinate (y_start+1 to image_height-1)
*/
static inline void isp_ll_crop_set_window(isp_dev_t *hw,
uint32_t x_start, uint32_t x_end,
uint32_t y_start, uint32_t y_end)
uint32_t x_start, uint32_t x_end,
uint32_t y_start, uint32_t y_end)
{
hw->crop_x_capture.crop_x_start = x_start;
hw->crop_x_capture.crop_x_end = x_end;
@@ -2550,8 +2563,8 @@ static inline void isp_ll_crop_set_window(isp_dev_t *hw,
* @param[out] y_end Crop end y coordinate (y_start+1 to image_height-1)
*/
static inline void isp_ll_crop_get_window(isp_dev_t *hw,
uint32_t *x_start, uint32_t *x_end,
uint32_t *y_start, uint32_t *y_end)
uint32_t *x_start, uint32_t *x_end,
uint32_t *y_start, uint32_t *y_end)
{
*x_start = hw->crop_x_capture.crop_x_start;
*x_end = hw->crop_x_capture.crop_x_end;
@@ -2592,15 +2605,15 @@ static inline void isp_ll_crop_enable(isp_dev_t *hw, bool enable)
}
static inline void isp_ll_crop_set_window(isp_dev_t *hw,
uint32_t x_start, uint32_t x_end,
uint32_t y_start, uint32_t y_end)
uint32_t x_start, uint32_t x_end,
uint32_t y_start, uint32_t y_end)
{
// for compatibility
}
static inline void isp_ll_crop_get_window(isp_dev_t *hw,
uint32_t *x_start, uint32_t *x_end,
uint32_t *y_start, uint32_t *y_end)
uint32_t *x_start, uint32_t *x_end,
uint32_t *y_start, uint32_t *y_end)
{
// for compatibility
}

6
components/soc/esp32p4/isp_periph.c → components/esp_hal_cam/esp32p4/isp_periph.c
View File

@@ -1,11 +1,11 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/periph_defs.h"
#include "soc/isp_periph.h"
#include "hal/isp_periph.h"
#ifdef __cplusplus
extern "C" {

2
components/hal/include/hal/isp_hal.h → components/esp_hal_cam/include/hal/isp_hal.h
View File

@@ -83,7 +83,6 @@ typedef struct {
*/
void isp_hal_init(isp_hal_context_t *hal, int isp_id);
/**
* @brief Color configurations
*/
@@ -94,7 +93,6 @@ typedef struct {
int color_brightness; ///< The color brightness value, range -128~127
} isp_hal_color_cfg_t;
/*---------------------------------------------------------------
AF
---------------------------------------------------------------*/

13
components/soc/include/soc/isp_periph.h → components/esp_hal_cam/include/hal/isp_periph.h
View File

@@ -1,7 +1,7 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -10,6 +10,9 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#if SOC_HAS(ISP)
#include "hal/isp_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
@@ -19,14 +22,14 @@ extern "C" {
typedef struct {
struct {
const uint32_t irq;
} instances[SOC_ISP_NUMS];
} instances[ISP_LL_PERIPH_NUMS];
struct {
const uint32_t dvp_pclk_sig;
const uint32_t dvp_hsync_sig;
const uint32_t dvp_vsync_sig;
const uint32_t dvp_de_sig;
const uint32_t dvp_data_sig[SOC_ISP_DVP_DATA_WIDTH_MAX];
} dvp_ctlr[SOC_ISP_DVP_CTLR_NUMS];
const uint32_t dvp_data_sig[ISP_LL_DVP_DATA_WIDTH_MAX];
} dvp_ctlr[ISP_LL_DVP_CTLR_NUMS];
} isp_info_t;
extern const isp_info_t isp_hw_info;

59
components/hal/include/hal/isp_types.h → components/esp_hal_cam/include/hal/isp_types.h
View File

@@ -95,7 +95,7 @@ typedef enum {
AE
---------------------------------------------------------------*/
#if (SOC_ISP_AE_BLOCK_X_NUMS && SOC_ISP_AE_BLOCK_Y_NUMS)
#if SOC_ISP_AWB_WINDOW_X_NUMS
#define ISP_AE_BLOCK_X_NUM SOC_ISP_AE_BLOCK_X_NUMS // The AF window number for sampling
#define ISP_AE_BLOCK_Y_NUM SOC_ISP_AE_BLOCK_Y_NUMS // The AF window number for sampling
#else
@@ -196,9 +196,9 @@ typedef enum {
*/
typedef union {
struct {
uint32_t decimal:ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS; ///< Integer part
uint32_t integer:ISP_DEMOSAIC_GRAD_RATIO_INT_BITS; ///< Decimal part
uint32_t reserved:ISP_DEMOSAIC_GRAD_RATIO_RES_BITS; ///< Reserved
uint32_t decimal: ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS; ///< Integer part
uint32_t integer: ISP_DEMOSAIC_GRAD_RATIO_INT_BITS; ///< Decimal part
uint32_t reserved: ISP_DEMOSAIC_GRAD_RATIO_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit gradient ratio value
} isp_demosaic_grad_ratio_t;
@@ -211,15 +211,6 @@ typedef enum {
ISP_DEMOSAIC_EDGE_PADDING_MODE_CUSTOM_DATA, ///< Fill Demosaic edge padding data with custom pixel data
} isp_demosaic_edge_padding_mode_t;
/*---------------------------------------------------------------
DVP
---------------------------------------------------------------*/
#if SOC_ISP_DVP_DATA_WIDTH_MAX
#define ISP_DVP_DATA_SIG_NUM SOC_ISP_DVP_DATA_WIDTH_MAX // The ISP DVP data signal number
#else
#define ISP_DVP_DATA_SIG_NUM 0
#endif
/*---------------------------------------------------------------
Sharpen
---------------------------------------------------------------*/
@@ -248,9 +239,9 @@ typedef enum {
*/
typedef union {
struct {
uint32_t decimal:ISP_SHARPEN_H_FREQ_COEF_DEC_BITS; ///< Decimal part
uint32_t integer:ISP_SHARPEN_H_FREQ_COEF_INT_BITS; ///< Integer part
uint32_t reserved:ISP_SHARPEN_H_FREQ_COEF_RES_BITS; ///< Reserved
uint32_t decimal: ISP_SHARPEN_H_FREQ_COEF_DEC_BITS; ///< Decimal part
uint32_t integer: ISP_SHARPEN_H_FREQ_COEF_INT_BITS; ///< Integer part
uint32_t reserved: ISP_SHARPEN_H_FREQ_COEF_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit high freq pixel sharpeness coeff register value
} isp_sharpen_h_freq_coeff_t;
@@ -260,9 +251,9 @@ typedef union {
*/
typedef union {
struct {
uint32_t decimal:ISP_SHARPEN_M_FREQ_COEF_DEC_BITS; ///< Decimal part
uint32_t integer:ISP_SHARPEN_M_FREQ_COEF_INT_BITS; ///< Integer part
uint32_t reserved:ISP_SHARPEN_M_FREQ_COEF_RES_BITS; ///< Reserved
uint32_t decimal: ISP_SHARPEN_M_FREQ_COEF_DEC_BITS; ///< Decimal part
uint32_t integer: ISP_SHARPEN_M_FREQ_COEF_INT_BITS; ///< Integer part
uint32_t reserved: ISP_SHARPEN_M_FREQ_COEF_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit medium freq pixel sharpeness coeff register value
} isp_sharpen_m_freq_coeff;
@@ -341,9 +332,9 @@ typedef enum {
*/
typedef union {
struct {
uint32_t decimal:ISP_HIST_WEIGHT_DEC_BITS; ///< Decimal part
uint32_t integer:ISP_HIST_WEIGHT_INT_BITS; ///< Integer part
uint32_t reserved:ISP_HIST_WEIGHT_RES_BITS; ///< Reserved
uint32_t decimal: ISP_HIST_WEIGHT_DEC_BITS; ///< Decimal part
uint32_t integer: ISP_HIST_WEIGHT_INT_BITS; ///< Integer part
uint32_t reserved: ISP_HIST_WEIGHT_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit histogram weight value
} isp_hist_weight_t;
@@ -353,9 +344,9 @@ typedef union {
*/
typedef union {
struct {
uint32_t decimal:ISP_HIST_COEFF_DEC_BITS; ///< Decimal part
uint32_t integer:ISP_HIST_COEFF_INT_BITS; ///< Integer part
uint32_t reserved:ISP_HIST_COEFF_RES_BITS; ///< Reserved
uint32_t decimal: ISP_HIST_COEFF_DEC_BITS; ///< Decimal part
uint32_t integer: ISP_HIST_COEFF_INT_BITS; ///< Integer part
uint32_t reserved: ISP_HIST_COEFF_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit histogram coefficient value
} isp_hist_coeff_t;
@@ -391,9 +382,9 @@ typedef struct {
*/
typedef union {
struct {
uint32_t decimal:ISP_COLOR_CONTRAST_DEC_BITS; ///< Decimal part
uint32_t integer:ISP_COLOR_CONTRAST_INT_BITS; ///< Integer part
uint32_t reserved:ISP_COLOR_CONTRAST_RES_BITS; ///< Reserved
uint32_t decimal: ISP_COLOR_CONTRAST_DEC_BITS; ///< Decimal part
uint32_t integer: ISP_COLOR_CONTRAST_INT_BITS; ///< Integer part
uint32_t reserved: ISP_COLOR_CONTRAST_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit color contrast value
} isp_color_contrast_t;
@@ -403,9 +394,9 @@ typedef union {
*/
typedef union {
struct {
uint32_t decimal:ISP_COLOR_SATURATION_DEC_BITS; ///< Decimal part
uint32_t integer:ISP_COLOR_SATURATION_INT_BITS; ///< Integer part
uint32_t reserved:ISP_COLOR_SATURATION_RES_BITS; ///< Reserved
uint32_t decimal: ISP_COLOR_SATURATION_DEC_BITS; ///< Decimal part
uint32_t integer: ISP_COLOR_SATURATION_INT_BITS; ///< Integer part
uint32_t reserved: ISP_COLOR_SATURATION_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit color saturation value
} isp_color_saturation_t;
@@ -428,9 +419,9 @@ typedef union {
*/
typedef union {
struct {
uint32_t decimal:8; ///< Integer part
uint32_t integer:2; ///< Decimal part
uint32_t reserved:ISP_LSC_GRAD_RATIO_RES_BITS; ///< Reserved
uint32_t decimal: ISP_LSC_GRAD_RATIO_DEC_BITS; ///< Integer part
uint32_t integer: ISP_LSC_GRAD_RATIO_INT_BITS; ///< Decimal part
uint32_t reserved: ISP_LSC_GRAD_RATIO_RES_BITS; ///< Reserved
};
uint32_t val; ///< 32-bit gradient ratio value
} isp_lsc_gain_t;

6
components/hal/isp_hal.c → components/esp_hal_cam/isp_hal.c
View File

@@ -56,9 +56,9 @@ void isp_hal_af_window_config(isp_hal_context_t *hal, int window_id, const isp_w
bool isp_hal_awb_set_window_range(isp_hal_context_t *hal, const isp_window_t *win)
{
if (win->top_left.x > win->btm_right.x ||
win->top_left.y > win->btm_right.y ||
win->btm_right.x > ISP_LL_AWB_WINDOW_MAX_RANGE ||
win->btm_right.y > ISP_LL_AWB_WINDOW_MAX_RANGE) {
win->top_left.y > win->btm_right.y ||
win->btm_right.x > ISP_LL_AWB_WINDOW_MAX_RANGE ||
win->btm_right.y > ISP_LL_AWB_WINDOW_MAX_RANGE) {
return false;
}
isp_ll_awb_set_window_range(hal->hw, win->top_left.x, win->top_left.y,

4
components/hal/CMakeLists.txt
View File

@@ -92,10 +92,6 @@ elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "i3c_master_hal.c")
endif()
if(CONFIG_SOC_ISP_SUPPORTED)
list(APPEND srcs "isp_hal.c")
endif()
if(CONFIG_SOC_UHCI_SUPPORTED)
list(APPEND srcs "uhci_hal.c")
endif()

4
components/soc/CMakeLists.txt
View File

@@ -77,10 +77,6 @@ if(CONFIG_SOC_LEDC_SUPPORTED)
list(APPEND srcs "${target_folder}/ledc_periph.c")
endif()
if(CONFIG_SOC_ISP_SUPPORTED)
list(APPEND srcs "${target}/isp_periph.c")
endif()
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "${target_folder}/i3c_master_periph.c")
endif()

24
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -943,18 +943,6 @@ config SOC_ISP_SHARE_CSI_BRG
bool
default y
config SOC_ISP_NUMS
int
default 1
config SOC_ISP_DVP_CTLR_NUMS
int
default 1
config SOC_ISP_AE_CTLR_NUMS
int
default 1
config SOC_ISP_AE_BLOCK_X_NUMS
int
default 5
@@ -963,10 +951,6 @@ config SOC_ISP_AE_BLOCK_Y_NUMS
int
default 5
config SOC_ISP_AF_CTLR_NUMS
int
default 1
config SOC_ISP_AF_WINDOW_NUMS
int
default 3
@@ -1003,10 +987,6 @@ config SOC_ISP_DEMOSAIC_GRAD_RATIO_RES_BITS
int
default 26
config SOC_ISP_DVP_DATA_WIDTH_MAX
int
default 16
config SOC_ISP_SHARPEN_TEMPLATE_X_NUMS
int
default 3
@@ -1039,10 +1019,6 @@ config SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS
int
default 24
config SOC_ISP_HIST_CTLR_NUMS
int
default 1
config SOC_ISP_HIST_BLOCK_X_NUMS
int
default 5

7
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -362,13 +362,8 @@
#define SOC_ISP_SHARPEN_SUPPORTED 1
#define SOC_ISP_WBG_SUPPORTED 1
#define SOC_ISP_SHARE_CSI_BRG 1
#define SOC_ISP_NUMS 1U
#define SOC_ISP_DVP_CTLR_NUMS 1U
#define SOC_ISP_AE_CTLR_NUMS 1U
#define SOC_ISP_AE_BLOCK_X_NUMS 5
#define SOC_ISP_AE_BLOCK_Y_NUMS 5
#define SOC_ISP_AF_CTLR_NUMS 1U
#define SOC_ISP_AF_WINDOW_NUMS 3
#define SOC_ISP_AWB_WINDOW_X_NUMS 5
#define SOC_ISP_AWB_WINDOW_Y_NUMS 5
@@ -378,7 +373,6 @@
#define SOC_ISP_DEMOSAIC_GRAD_RATIO_INT_BITS 2
#define SOC_ISP_DEMOSAIC_GRAD_RATIO_DEC_BITS 4
#define SOC_ISP_DEMOSAIC_GRAD_RATIO_RES_BITS 26
#define SOC_ISP_DVP_DATA_WIDTH_MAX 16
#define SOC_ISP_SHARPEN_TEMPLATE_X_NUMS 3
#define SOC_ISP_SHARPEN_TEMPLATE_Y_NUMS 3
#define SOC_ISP_SHARPEN_H_FREQ_COEF_INT_BITS 3
@@ -387,7 +381,6 @@
#define SOC_ISP_SHARPEN_M_FREQ_COEF_INT_BITS 3
#define SOC_ISP_SHARPEN_M_FREQ_COEF_DEC_BITS 5
#define SOC_ISP_SHARPEN_M_FREQ_COEF_RES_BITS 24
#define SOC_ISP_HIST_CTLR_NUMS 1U
#define SOC_ISP_HIST_BLOCK_X_NUMS 5
#define SOC_ISP_HIST_BLOCK_Y_NUMS 5
#define SOC_ISP_HIST_SEGMENT_NUMS 16

2
docs/doxygen/Doxyfile_esp32p4
View File

@@ -33,9 +33,9 @@ INPUT += \
$(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens.h \
$(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens_types.h \
$(PROJECT_PATH)/components/esp_hal_cam/include/hal/cam_ctlr_types.h \
$(PROJECT_PATH)/components/esp_hal_cam/include/hal/isp_types.h \
$(PROJECT_PATH)/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h \
$(PROJECT_PATH)/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h \
$(PROJECT_PATH)/components/hal/include/hal/isp_types.h \
$(PROJECT_PATH)/components/hal/include/hal/ppa_types.h \
$(PROJECT_PATH)/components/sdmmc/include/sd_pwr_ctrl.h \
$(PROJECT_PATH)/components/sdmmc/include/sd_pwr_ctrl_by_on_chip_ldo.h \

2
docs/en/api-reference/peripherals/isp.rst
View File

@@ -978,4 +978,4 @@ API Reference
.. include-build-file:: inc/isp_crop.inc
.. include-build-file:: inc/isp_core.inc
.. include-build-file:: inc/components/esp_driver_isp/include/driver/isp_types.inc
.. include-build-file:: inc/components/hal/include/hal/isp_types.inc
.. include-build-file:: inc/components/esp_hal_cam/include/hal/isp_types.inc

2
docs/zh_CN/api-reference/peripherals/isp.rst
View File

@@ -978,4 +978,4 @@ API 参考
.. include-build-file:: inc/isp_crop.inc
.. include-build-file:: inc/isp_core.inc
.. include-build-file:: inc/components/esp_driver_isp/include/driver/isp_types.inc
.. include-build-file:: inc/components/hal/include/hal/isp_types.inc
.. include-build-file:: inc/components/esp_hal_cam/include/hal/isp_types.inc