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Merge branch 'fix/fix_cache_sync_ops_multi_call_issue_v5.5' into 'release/v5.5'

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cache: fixed cache sync ops concurrent call issue (v5.5)

See merge request espressif/esp-idf!44556
This commit is contained in:
morris
2025-12-26 10:52:03 +08:00
parent 4b434bd71d 46ae86b4cf
commit 9615bfa2bd
4 changed files with 25 additions and 0 deletions
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10
components/esp_mm/esp_cache_msync.c
View File

@@ -32,6 +32,16 @@ DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock);
static _lock_t s_mutex;
#endif
void esp_cache_sync_ops_enter_critical_section(void)
{
esp_os_enter_critical_safe(&s_spinlock);
}
void esp_cache_sync_ops_exit_critical_section(void)
{
esp_os_exit_critical_safe(&s_spinlock);
}
#if SOC_CACHE_WRITEBACK_SUPPORTED
static void s_c2m_ops(uint32_t vaddr, size_t size)
{

2
components/esp_mm/esp_mmu_map.c
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@@ -404,7 +404,9 @@ static void IRAM_ATTR NOINLINE_ATTR s_do_cache_invalidate(uint32_t vaddr_start,
*/
cache_sync();
#else //Other chips
esp_cache_sync_ops_enter_critical_section();
cache_hal_invalidate_addr(vaddr_start, size);
esp_cache_sync_ops_exit_critical_section();
#endif // CONFIG_IDF_TARGET_ESP32
}

10
components/esp_mm/include/esp_private/esp_cache_private.h
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@@ -159,6 +159,16 @@ esp_err_t esp_cache_aligned_calloc(size_t n, size_t size, uint32_t heap_caps, vo
__attribute__((deprecated("Use 'heap_caps_calloc' with MALLOC_CAP_CACHE_ALIGNED caps instead")))
esp_err_t esp_cache_aligned_calloc_prefer(size_t n, size_t size, void **out_ptr, size_t *actual_size, size_t flag_nums, ...);
/**
* @brief Enter critical section for cache sync operations
*/
void esp_cache_sync_ops_enter_critical_section(void);
/**
* @brief Exit critical section for cache sync operations
*/
void esp_cache_sync_ops_exit_critical_section(void);
/**
* @brief Get Cache alignment requirement for data
*

3
components/spi_flash/flash_mmap.c
View File

@@ -22,6 +22,7 @@
#endif
#include "esp_private/esp_mmu_map_private.h"
#include "esp_private/esp_cache_private.h"
#include "esp_mmu_map.h"
#include "esp_rom_spiflash.h"
#if CONFIG_SPIRAM
@@ -315,7 +316,9 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
return true;
#else // CONFIG_IDF_TARGET_ESP32
if (vaddr != NULL) {
esp_cache_sync_ops_enter_critical_section();
cache_hal_invalidate_addr((uint32_t)vaddr, SPI_FLASH_MMU_PAGE_SIZE);
esp_cache_sync_ops_exit_critical_section();
ret = true;
}
#endif // CONFIG_IDF_TARGET_ESP32