alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-11 21:10:20 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix ld err since esp32c2 do not suport config gpio of spi flash via efuse

Browse Source
This commit is contained in:
jingli
2022-01-25 11:02:52 +08:00
parent e70c434780
commit ae127b04cd
13 changed files with 39 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
components/bootloader_support/src/bootloader_common.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,6 +21,7 @@
#include "soc/gpio_periph.h"
#include "soc/rtc.h"
#include "soc/efuse_reg.h"
#include "soc/soc_caps.h"
#include "hal/gpio_ll.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
@@ -195,6 +196,7 @@ RESET_REASON bootloader_common_get_reset_reason(int cpu_no)
uint8_t bootloader_flash_get_cs_io(void)
{
#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
uint8_t cs_io;
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
@@ -203,4 +205,7 @@ uint8_t bootloader_flash_get_cs_io(void)
cs_io = (spiconfig >> 18) & 0x3f;
}
return cs_io;
#else
return SPI_CS0_GPIO_NUM;
#endif
}

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@@ -579,6 +579,10 @@ config SOC_SPIRAM_SUPPORTED
bool
default y
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default y
config SOC_SHA_SUPPORT_PARALLEL_ENG
bool
default y

3
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -310,6 +310,9 @@
/*-------------------------- SPIRAM CAPS -------------------------------------*/
#define SOC_SPIRAM_SUPPORTED 1
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* ESP32 style SHA engine, where multiple states can be stored in parallel */
#define SOC_SHA_SUPPORT_PARALLEL_ENG (1)

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@@ -375,6 +375,10 @@ config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default n
config SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED
bool
default y

1
components/soc/esp32c2/include/soc/soc_caps.h
View File

@@ -203,6 +203,7 @@
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (0)
#define SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED 1

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -551,6 +551,10 @@ config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default y
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y

1
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -272,6 +272,7 @@
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -539,6 +539,10 @@ config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default y
config SOC_MEMSPI_SRC_FREQ_48M_SUPPORTED
bool
default y

1
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -280,6 +280,7 @@
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
#define SOC_MEMSPI_SRC_FREQ_48M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_24M_SUPPORTED 1

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@@ -807,6 +807,10 @@ config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default y
config SOC_PM_SUPPORT_EXT_WAKEUP
bool
default y

2
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -372,6 +372,8 @@
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
/*-------------------------- Power Management CAPS ---------------------------*/
#define SOC_PM_SUPPORT_EXT_WAKEUP (1)

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -947,6 +947,10 @@ config SOC_SPI_MEM_SUPPORT_TIME_TUNING
bool
default y
config SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
bool
default y
config SOC_COEX_HW_PTI
bool
default y

1
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -403,6 +403,7 @@
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_OPI_MODE (1)
#define SOC_SPI_MEM_SUPPORT_TIME_TUNING (1)
#define SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)