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esp_adc: support h2 oneshot mode and continuous mode

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This commit is contained in:
Armando
2023-02-02 14:46:44 +08:00
parent aa892a18a3
commit d0e4d36fb6
47 changed files with 1176 additions and 99 deletions
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15
components/hal/esp32c6/include/hal/sar_ctrl_ll.h
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@@ -26,9 +26,8 @@
extern "C" {
#endif
#define PWDET_CONF_REG 0x600A8010
#define PWDET_SAR_POWER_FORCE BIT(24)
#define PWDET_SAR_POWER_CNTL BIT(23)
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
typedef enum {
@@ -48,13 +47,13 @@ typedef enum {
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
{
if (mode == SAR_CTRL_LL_POWER_FSM) {
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
} else if (mode == SAR_CTRL_LL_POWER_ON) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
REG_SET_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_FORCE);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_SAR_POWER_CNTL);
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
}
}