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Merge branch 'fix/update_breakpoint_nums_on_c5_h4_v5.5' into 'release/v5.5'

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fix(soc): update breakpoint nums on c5 and h4 (v5.5)

See merge request espressif/esp-idf!44356
This commit is contained in:
morris
2025-12-30 12:19:23 +08:00
parent de3dad2a87 2ff54ff5c5
commit ded4814c8d
4 changed files with 8 additions and 8 deletions
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4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -453,11 +453,11 @@ config SOC_BRANCH_PREDICTOR_SUPPORTED
config SOC_CPU_BREAKPOINTS_NUM
int
default 4
default 3
config SOC_CPU_WATCHPOINTS_NUM
int
default 4
default 3
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex

4
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -165,8 +165,8 @@
#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting
#define SOC_BRANCH_PREDICTOR_SUPPORTED 1
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_BREAKPOINTS_NUM 3
#define SOC_CPU_WATCHPOINTS_NUM 3
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x100 // bytes
#define SOC_CPU_HAS_PMA 1

4
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -125,11 +125,11 @@ config SOC_CPU_COPROC_NUM
config SOC_CPU_BREAKPOINTS_NUM
int
default 4
default 3
config SOC_CPU_WATCHPOINTS_NUM
int
default 4
default 3
config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
hex

4
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -156,8 +156,8 @@
#define SOC_CPU_HAS_FPU_EXT_ILL_BUG 0 // EXT_ILL CSR doesn't support FLW/FSW
#define SOC_CPU_COPROC_NUM 2
#define SOC_CPU_BREAKPOINTS_NUM 4
#define SOC_CPU_WATCHPOINTS_NUM 4
#define SOC_CPU_BREAKPOINTS_NUM 3
#define SOC_CPU_WATCHPOINTS_NUM 3
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
#define SOC_CPU_HAS_PMA 1