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soc: add soc headers from S3 fpga bringup branch

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Marius Vikhammer
2021-03-17 18:47:51 +08:00
parent 8c4d9fa66e
commit e2919eca8e
73 changed files with 54415 additions and 37342 deletions
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components/soc/esp32s3/include/soc/apb_ctrl_reg.h
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@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,536 +11,645 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_APB_CTRL_REG_H_
#define _SOC_APB_CTRL_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000)
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_RST_TICK_CNT (BIT(12))
#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
#define APB_CTRL_RST_TICK_CNT_V 0x1
#define APB_CTRL_RST_TICK_CNT_S 12
/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_EN (BIT(11))
#define APB_CTRL_CLK_EN_M (BIT(11))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 11
/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_320M_EN (BIT(10))
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
#define APB_CTRL_CLK_320M_EN_V 0x1
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
#define APB_CTRL_PRE_DIV_CNT_S 0
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004)
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_TICK_ENABLE (BIT(16))
#define APB_CTRL_TICK_ENABLE_M (BIT(16))
#define APB_CTRL_TICK_ENABLE_V 0x1
#define APB_CTRL_TICK_ENABLE_S 16
/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
#define APB_CTRL_CK8M_TICK_NUM_S 8
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
/*description: .*/
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
#define APB_CTRL_XTAL_TICK_NUM_S 0
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008)
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x8)
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
#define APB_CTRL_CLK_XTAL_OEN_S 10
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
#define APB_CTRL_CLK40X_BB_OEN_S 9
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_320M_OEN (BIT(6))
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
#define APB_CTRL_CLK_320M_OEN_V 0x1
#define APB_CTRL_CLK_320M_OEN_S 6
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK160_OEN (BIT(5))
#define APB_CTRL_CLK160_OEN_M (BIT(5))
#define APB_CTRL_CLK160_OEN_V 0x1
#define APB_CTRL_CLK160_OEN_S 5
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK80_OEN (BIT(4))
#define APB_CTRL_CLK80_OEN_M (BIT(4))
#define APB_CTRL_CLK80_OEN_V 0x1
#define APB_CTRL_CLK80_OEN_S 4
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK_BB_OEN (BIT(3))
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
#define APB_CTRL_CLK_BB_OEN_V 0x1
#define APB_CTRL_CLK_BB_OEN_S 3
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK44_OEN (BIT(2))
#define APB_CTRL_CLK44_OEN_M (BIT(2))
#define APB_CTRL_CLK44_OEN_V 0x1
#define APB_CTRL_CLK44_OEN_S 2
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK22_OEN (BIT(1))
#define APB_CTRL_CLK22_OEN_M (BIT(1))
#define APB_CTRL_CLK22_OEN_V 0x1
#define APB_CTRL_CLK22_OEN_S 1
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_CLK20_OEN (BIT(0))
#define APB_CTRL_CLK20_OEN_M (BIT(0))
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C)
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0xC)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_S 0
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010)
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x10)
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014)
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x14)
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
/*description: .*/
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018)
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x18)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C)
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x1C)
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
#define APB_CTRL_PERI_IO_SWAP_S 0
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020)
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x20)
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x024)
#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x24)
/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to bypass cache writeback request to external memory so
that spi will not check its attribute.*/
/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
check its attribute..*/
#define APB_CTRL_WRITEBACK_BYPASS (BIT(0))
#define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0))
#define APB_CTRL_WRITEBACK_BYPASS_V 0x1
#define APB_CTRL_WRITEBACK_BYPASS_S 0
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028)
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x28)
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x2C)
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030)
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x30)
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034)
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x34)
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038)
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x38)
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C)
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x3C)
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040)
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x40)
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044)
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x44)
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048)
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x48)
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C)
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x4C)
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050)
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x50)
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054)
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x54)
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058)
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x58)
/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF
#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
#define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF
#define APB_CTRL_SRAM_ACE0_ATTR_S 0
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C)
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x5C)
/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF
#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x060)
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x60)
/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF
#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
#define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF
#define APB_CTRL_SRAM_ACE2_ATTR_S 0
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x064)
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x64)
/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF
#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
#define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF
#define APB_CTRL_SRAM_ACE3_ATTR_S 0
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068)
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x68)
/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C)
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x6C)
/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x070)
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x70)
/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x074)
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x74)
/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078)
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x78)
/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE0_SIZE_S 0
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C)
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x7C)
/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE1_SIZE_S 0
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x080)
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x80)
/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x084)
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x84)
/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF
#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF
#define APB_CTRL_SRAM_ACE3_SIZE_S 0
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088)
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x88)
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x8C)
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090)
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x90)
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094)
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x94)
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_REDCY_ANDOR (BIT(31))
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
#define APB_CTRL_REDCY_ANDOR_V 0x1
#define APB_CTRL_REDCY_ANDOR_S 31
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG0_S 0
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098)
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x98)
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_REDCY_NANDOR (BIT(31))
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
#define APB_CTRL_REDCY_NANDOR_V 0x1
#define APB_CTRL_REDCY_NANDOR_S 31
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
#define APB_CTRL_REDCY_SIG1_S 0
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C)
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x9C)
/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7))
#define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7))
#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1
#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7
/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: .*/
#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6))
#define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6))
#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1
#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xA0)
/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes.
1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
1024 bytes. 3: 2048 bytes..*/
#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003
#define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V)<<(APB_CTRL_SRAM_PAGE_SIZE_S))
#define APB_CTRL_SRAM_PAGE_SIZE_V 0x3
#define APB_CTRL_SRAM_PAGE_SIZE_S 20
/* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512
bytes. 2: 1024 bytes. 3: 2048 bytes.*/
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
tes. 3: 2048 bytes..*/
#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003
#define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V)<<(APB_CTRL_FLASH_PAGE_SIZE_S))
#define APB_CTRL_FLASH_PAGE_SIZE_V 0x3
#define APB_CTRL_FLASH_PAGE_SIZE_S 18
/* APB_CTRL_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: Set this bit to enable MSPI interrupt when the error times of
MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/
#define APB_CTRL_ECC_ERR_INT_EN (BIT(17))
#define APB_CTRL_ECC_ERR_INT_EN_M (BIT(17))
#define APB_CTRL_ECC_ERR_INT_EN_V 0x1
#define APB_CTRL_ECC_ERR_INT_EN_S 17
/* APB_CTRL_ECC_ERR_INT_NUM : R/W ;bitpos:[16:9] ;default: 8'd10 ; */
/*description: Set the error times of MSPI ECC read to generate MSPI interrupt.*/
#define APB_CTRL_ECC_ERR_INT_NUM 0x000000FF
#define APB_CTRL_ECC_ERR_INT_NUM_M ((APB_CTRL_ECC_ERR_INT_NUM_V) << (APB_CTRL_ECC_ERR_INT_NUM_S))
#define APB_CTRL_ECC_ERR_INT_NUM_V 0xFF
#define APB_CTRL_ECC_ERR_INT_NUM_S 9
/* APB_CTRL_ECC_ERR_CNT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */
/*description: Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/
#define APB_CTRL_ECC_ERR_CNT_CLR (BIT(8))
#define APB_CTRL_ECC_ERR_CNT_CLR_M (BIT(8))
#define APB_CTRL_ECC_ERR_CNT_CLR_V 0x1
#define APB_CTRL_ECC_ERR_CNT_CLR_S 8
/* APB_CTRL_ECC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */
/*description: This bits show the error times of MSPI ECC read.*/
#define APB_CTRL_ECC_ERR_CNT 0x000000FF
#define APB_CTRL_ECC_ERR_CNT_M ((APB_CTRL_ECC_ERR_CNT_V) << (APB_CTRL_ECC_ERR_CNT_S))
#define APB_CTRL_ECC_ERR_CNT_V 0xFF
#define APB_CTRL_ECC_ERR_CNT_S 0
#define APB_CTRL_SPI_MEM_ECC_ERR_AADR_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
/* APB_CTRL_ECC_ERR_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: This bits show the latest MSPI ECC error address.*/
#define APB_CTRL_ECC_ERR_ADDR 0xFFFFFFFF
#define APB_CTRL_ECC_ERR_ADDR_M ((APB_CTRL_ECC_ERR_ADDR_V) << (APB_CTRL_ECC_ERR_ADDR_S))
#define APB_CTRL_ECC_ERR_ADDR_V 0xFFFFFFFF
#define APB_CTRL_ECC_ERR_ADDR_S 0
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0xA8)
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
/*description: .*/
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x000007FF
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0x7FF
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: .*/
#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0xAC)
/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
/*description: .*/
#define APB_CTRL_SRAM_POWER_DOWN 0x000007FF
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
#define APB_CTRL_SRAM_POWER_DOWN_V 0x7FF
#define APB_CTRL_SRAM_POWER_DOWN_S 3
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: .*/
#define APB_CTRL_ROM_POWER_DOWN 0x00000007
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
#define APB_CTRL_ROM_POWER_DOWN_V 0x7
#define APB_CTRL_ROM_POWER_DOWN_S 0
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0xB0)
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
/*description: .*/
#define APB_CTRL_SRAM_POWER_UP 0x000007FF
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
#define APB_CTRL_SRAM_POWER_UP_V 0x7FF
#define APB_CTRL_SRAM_POWER_UP_S 3
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: .*/
#define APB_CTRL_ROM_POWER_UP 0x00000007
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
#define APB_CTRL_ROM_POWER_UP_V 0x7
#define APB_CTRL_ROM_POWER_UP_S 0
#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xB4)
/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: .*/
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: .*/
#define APB_CTRL_RETENTION_CPU_LINK_ADDR 0x07FFFFFF
#define APB_CTRL_RETENTION_CPU_LINK_ADDR_M ((APB_CTRL_RETENTION_CPU_LINK_ADDR_V)<<(APB_CTRL_RETENTION_CPU_LINK_ADDR_S))
#define APB_CTRL_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF
#define APB_CTRL_RETENTION_CPU_LINK_ADDR_S 0
#define APB_CTRL_RETENTION_CTRL1_REG (DR_REG_APB_CTRL_BASE + 0xB8)
/* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: .*/
#define APB_CTRL_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
#define APB_CTRL_RETENTION_TAG_LINK_ADDR_M ((APB_CTRL_RETENTION_TAG_LINK_ADDR_V)<<(APB_CTRL_RETENTION_TAG_LINK_ADDR_S))
#define APB_CTRL_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF
#define APB_CTRL_RETENTION_TAG_LINK_ADDR_S 0
#define APB_CTRL_RETENTION_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0xBC)
/* APB_CTRL_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define APB_CTRL_RET_ICACHE_ENABLE (BIT(31))
#define APB_CTRL_RET_ICACHE_ENABLE_M (BIT(31))
#define APB_CTRL_RET_ICACHE_ENABLE_V 0x1
#define APB_CTRL_RET_ICACHE_ENABLE_S 31
/* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
/*description: .*/
#define APB_CTRL_RET_ICACHE_START_POINT 0x000000FF
#define APB_CTRL_RET_ICACHE_START_POINT_M ((APB_CTRL_RET_ICACHE_START_POINT_V)<<(APB_CTRL_RET_ICACHE_START_POINT_S))
#define APB_CTRL_RET_ICACHE_START_POINT_V 0xFF
#define APB_CTRL_RET_ICACHE_START_POINT_S 22
/* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
/*description: .*/
#define APB_CTRL_RET_ICACHE_VLD_SIZE 0x000000FF
#define APB_CTRL_RET_ICACHE_VLD_SIZE_M ((APB_CTRL_RET_ICACHE_VLD_SIZE_V)<<(APB_CTRL_RET_ICACHE_VLD_SIZE_S))
#define APB_CTRL_RET_ICACHE_VLD_SIZE_V 0xFF
#define APB_CTRL_RET_ICACHE_VLD_SIZE_S 13
/* APB_CTRL_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
/*description: .*/
#define APB_CTRL_RET_ICACHE_SIZE 0x000000FF
#define APB_CTRL_RET_ICACHE_SIZE_M ((APB_CTRL_RET_ICACHE_SIZE_V)<<(APB_CTRL_RET_ICACHE_SIZE_S))
#define APB_CTRL_RET_ICACHE_SIZE_V 0xFF
#define APB_CTRL_RET_ICACHE_SIZE_S 4
#define APB_CTRL_RETENTION_CTRL3_REG (DR_REG_APB_CTRL_BASE + 0xC0)
/* APB_CTRL_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define APB_CTRL_RET_DCACHE_ENABLE (BIT(31))
#define APB_CTRL_RET_DCACHE_ENABLE_M (BIT(31))
#define APB_CTRL_RET_DCACHE_ENABLE_V 0x1
#define APB_CTRL_RET_DCACHE_ENABLE_S 31
/* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
/*description: .*/
#define APB_CTRL_RET_DCACHE_START_POINT 0x000001FF
#define APB_CTRL_RET_DCACHE_START_POINT_M ((APB_CTRL_RET_DCACHE_START_POINT_V)<<(APB_CTRL_RET_DCACHE_START_POINT_S))
#define APB_CTRL_RET_DCACHE_START_POINT_V 0x1FF
#define APB_CTRL_RET_DCACHE_START_POINT_S 22
/* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
/*description: .*/
#define APB_CTRL_RET_DCACHE_VLD_SIZE 0x000001FF
#define APB_CTRL_RET_DCACHE_VLD_SIZE_M ((APB_CTRL_RET_DCACHE_VLD_SIZE_V)<<(APB_CTRL_RET_DCACHE_VLD_SIZE_S))
#define APB_CTRL_RET_DCACHE_VLD_SIZE_V 0x1FF
#define APB_CTRL_RET_DCACHE_VLD_SIZE_S 13
/* APB_CTRL_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
/*description: .*/
#define APB_CTRL_RET_DCACHE_SIZE 0x000001FF
#define APB_CTRL_RET_DCACHE_SIZE_M ((APB_CTRL_RET_DCACHE_SIZE_V)<<(APB_CTRL_RET_DCACHE_SIZE_S))
#define APB_CTRL_RET_DCACHE_SIZE_V 0x1FF
#define APB_CTRL_RET_DCACHE_SIZE_S 4
#define APB_CTRL_RETENTION_CTRL4_REG (DR_REG_APB_CTRL_BASE + 0xC4)
/* APB_CTRL_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
/*description: .*/
#define APB_CTRL_RETENTION_INV_CFG 0xFFFFFFFF
#define APB_CTRL_RETENTION_INV_CFG_M ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S))
#define APB_CTRL_RETENTION_INV_CFG_V 0xFFFFFFFF
#define APB_CTRL_RETENTION_INV_CFG_S 0
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h20032301 ; */
/*description: Version control*/
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
/*description: Version control.*/
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
#define APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_CTRL_REG_H_ */

94
components/soc/esp32s3/include/soc/apb_ctrl_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_APB_CTRL_STRUCT_H_
#define _SOC_APB_CTRL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
@@ -240,31 +238,85 @@ typedef volatile struct {
uint32_t pbus_mem_force_pd: 1;
uint32_t dc_mem_force_pu: 1;
uint32_t dc_mem_force_pd: 1;
uint32_t reserved6: 26;
uint32_t freq_mem_force_pu: 1;
uint32_t freq_mem_force_pd: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} front_end_mem_pd;
union {
struct {
uint32_t ecc_err: 8; /*This bits show the error times of MSPI ECC read.*/
uint32_t ecc_err_clr: 1; /*Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/
uint32_t ecc_err_int_num: 8; /*Set the error times of MSPI ECC read to generate MSPI interrupt.*/
uint32_t ecc_err_int_en: 1; /*Set this bit to enable MSPI interrupt when the error times of MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/
uint32_t reserved0: 18; /*reserved*/
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} spi_mem_ecc_ctrl;
uint32_t spi_mem_ecc_err_aadr; /*This bits show the latest MSPI ECC error address.*/
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_a4;
union {
struct {
uint32_t rom_clkgate_force_on: 3;
uint32_t sram_clkgate_force_on:11;
uint32_t reserved14: 18;
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down: 3;
uint32_t sram_power_down:11;
uint32_t reserved14: 18;
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up: 3;
uint32_t sram_power_up:11;
uint32_t reserved14: 18;
};
uint32_t val;
} mem_power_up;
union {
struct {
uint32_t retention_cpu_link_addr:27;
uint32_t nobypass_cpu_iso_rst: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t retention_tag_link_addr:27;
uint32_t reserved27: 5;
};
uint32_t val;
} retention_ctrl1;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_icache_size: 8;
uint32_t reserved12: 1;
uint32_t ret_icache_vld_size: 8;
uint32_t reserved21: 1;
uint32_t ret_icache_start_point: 8;
uint32_t reserved30: 1;
uint32_t ret_icache_enable: 1;
};
uint32_t val;
} retention_ctrl2;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_dcache_size: 9;
uint32_t ret_dcache_vld_size: 9;
uint32_t ret_dcache_start_point: 9;
uint32_t ret_dcache_enable: 1;
};
uint32_t val;
} retention_ctrl3;
uint32_t retention_ctrl4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
@@ -472,9 +524,9 @@ typedef volatile struct {
uint32_t reserved_3f8;
uint32_t date; /*Version control*/
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_APB_CTRL_STRUCT_H_ */

316
components/soc/esp32s3/include/soc/apb_saradc_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,688 +11,636 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_APB_SARADC_REG_H_
#define _SOC_APB_SARADC_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
/*description: wait arbit signal stable after sar_done*/
/*description: wait arbit signal stable after sar_done.*/
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: force option to xpd sar blocks*/
/*description: force option to xpd sar blocks.*/
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
#define APB_SARADC_XPD_SAR_FORCE_S 27
/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
is from GPIO matrix*/
/*description: 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matr
ix.*/
#define APB_SARADC_DATA_TO_I2S (BIT(26))
#define APB_SARADC_DATA_TO_I2S_M (BIT(26))
#define APB_SARADC_DATA_TO_I2S_V 0x1
#define APB_SARADC_DATA_TO_I2S_S 26
/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
in this case the resolution should not be larger than 11 bits.*/
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
resolution should not be larger than 11 bits..*/
#define APB_SARADC_DATA_SAR_SEL (BIT(25))
#define APB_SARADC_DATA_SAR_SEL_M (BIT(25))
#define APB_SARADC_DATA_SAR_SEL_V 0x1
#define APB_SARADC_DATA_SAR_SEL_S 25
/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
/*description: clear the pointer of pattern table for DIG ADC2 CTRL.*/
#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24
/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/
#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1
#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23
/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
/*description: 0 ~ 15 means length 1 ~ 16.*/
#define APB_SARADC_SAR2_PATT_LEN 0x0000000F
#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S))
#define APB_SARADC_SAR2_PATT_LEN_V 0xF
#define APB_SARADC_SAR2_PATT_LEN_S 19
/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
/*description: 0 ~ 15 means length 1 ~ 16*/
/*description: 0 ~ 15 means length 1 ~ 16.*/
#define APB_SARADC_SAR1_PATT_LEN 0x0000000F
#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S))
#define APB_SARADC_SAR1_PATT_LEN_V 0xF
#define APB_SARADC_SAR1_PATT_LEN_S 15
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
/*description: SAR clock divider*/
/*description: SAR clock divider.*/
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
#define APB_SARADC_SAR_CLK_DIV_S 7
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
#define APB_SARADC_SAR_CLK_GATED_V 0x1
#define APB_SARADC_SAR_CLK_GATED_S 6
/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
/*description: 0: SAR1, 1: SAR2, only work for single SAR mode.*/
#define APB_SARADC_SAR_SEL (BIT(5))
#define APB_SARADC_SAR_SEL_M (BIT(5))
#define APB_SARADC_SAR_SEL_V 0x1
#define APB_SARADC_SAR_SEL_S 5
/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
/*description: 0: single mode 1: double mode 2: alternate mode*/
/*description: 0: single mode, 1: double mode, 2: alternate mode.*/
#define APB_SARADC_WORK_MODE 0x00000003
#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S))
#define APB_SARADC_WORK_MODE_V 0x3
#define APB_SARADC_WORK_MODE_S 3
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_START (BIT(1))
#define APB_SARADC_START_M (BIT(1))
#define APB_SARADC_START_V 0x1
#define APB_SARADC_START_S 1
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_START_FORCE (BIT(0))
#define APB_SARADC_START_FORCE_M (BIT(0))
#define APB_SARADC_START_FORCE_V 0x1
#define APB_SARADC_START_FORCE_S 0
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
/*description: to enable saradc timer trigger*/
/*description: to enable saradc timer trigger.*/
#define APB_SARADC_TIMER_EN (BIT(24))
#define APB_SARADC_TIMER_EN_M (BIT(24))
#define APB_SARADC_TIMER_EN_V 0x1
#define APB_SARADC_TIMER_EN_S 24
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
/*description: to set saradc timer target*/
/*description: to set saradc timer target.*/
#define APB_SARADC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
#define APB_SARADC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_TIMER_TARGET_S 12
/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
/*description: 1: select saradc timer 0: i2s_ws trigger*/
/*description: 1: select saradc timer 0: i2s_ws trigger.*/
#define APB_SARADC_TIMER_SEL (BIT(11))
#define APB_SARADC_TIMER_SEL_M (BIT(11))
#define APB_SARADC_TIMER_SEL_V 0x1
#define APB_SARADC_TIMER_SEL_S 11
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
#define APB_SARADC_SAR2_INV (BIT(10))
#define APB_SARADC_SAR2_INV_M (BIT(10))
#define APB_SARADC_SAR2_INV_V 0x1
#define APB_SARADC_SAR2_INV_S 10
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/
#define APB_SARADC_SAR1_INV (BIT(9))
#define APB_SARADC_SAR1_INV_M (BIT(9))
#define APB_SARADC_SAR1_INV_V 0x1
#define APB_SARADC_SAR1_INV_S 9
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
/*description: max conversion number*/
/*description: max conversion number.*/
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
#define APB_SARADC_MAX_MEAS_NUM_S 1
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008)
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_FILTER_FACTOR0 0x00000007
#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
#define APB_SARADC_FILTER_FACTOR0_V 0x7
#define APB_SARADC_FILTER_FACTOR0_S 29
/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_FILTER_FACTOR1 0x00000007
#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
#define APB_SARADC_FILTER_FACTOR1_V 0x7
#define APB_SARADC_FILTER_FACTOR1_S 26
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xC)
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
/*description: */
/*description: .*/
#define APB_SARADC_STANDBY_WAIT 0x000000FF
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
#define APB_SARADC_STANDBY_WAIT_V 0xFF
#define APB_SARADC_STANDBY_WAIT_S 16
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
/*description: */
/*description: .*/
#define APB_SARADC_RSTB_WAIT 0x000000FF
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
#define APB_SARADC_RSTB_WAIT_V 0xFF
#define APB_SARADC_RSTB_WAIT_S 8
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
/*description: */
/*description: .*/
#define APB_SARADC_XPD_WAIT 0x000000FF
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
#define APB_SARADC_XPD_WAIT_V 0xFF
#define APB_SARADC_XPD_WAIT_S 0
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR1_STATUS_S 0
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
#define APB_SARADC_SAR2_STATUS_S 0
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/
#define APB_SARADC_SAR1_PATT_TAB1 0x00FFFFFF
#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S))
#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFF
#define APB_SARADC_SAR1_PATT_TAB1_S 0
#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1C)
/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/
#define APB_SARADC_SAR1_PATT_TAB2 0x00FFFFFF
#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S))
#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFF
#define APB_SARADC_SAR1_PATT_TAB2_S 0
#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020)
#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x20)
/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte).*/
#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF
#define APB_SARADC_SAR1_PATT_TAB3_S 0
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024)
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x24)
/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte).*/
#define APB_SARADC_SAR1_PATT_TAB4 0x00FFFFFF
#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S))
#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFF
#define APB_SARADC_SAR1_PATT_TAB4_S 0
#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028)
#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x28)
/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
/*description: item 0 ~ 3 for pattern table 2 (each item one byte).*/
#define APB_SARADC_SAR2_PATT_TAB1 0x00FFFFFF
#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S))
#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFF
#define APB_SARADC_SAR2_PATT_TAB1_S 0
#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C)
#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x2C)
/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte).*/
#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF
#define APB_SARADC_SAR2_PATT_TAB2_S 0
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030)
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x30)
/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte).*/
#define APB_SARADC_SAR2_PATT_TAB3 0x00FFFFFF
#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S))
#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFF
#define APB_SARADC_SAR2_PATT_TAB3_S 0
#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034)
#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x34)
/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte).*/
#define APB_SARADC_SAR2_PATT_TAB4 0x00FFFFFF
#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S))
#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFF
#define APB_SARADC_SAR2_PATT_TAB4_S 0
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038)
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: adc2 arbiter uses fixed priority*/
/*description: adc2 arbiter uses fixed priority.*/
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
/*description: Set adc2 arbiter wifi priority*/
/*description: Set adc2 arbiter wifi priority.*/
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
/*description: Set adc2 arbiter rtc priority*/
/*description: Set adc2 arbiter rtc priority.*/
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
/*description: Set adc2 arbiterapb priority*/
/*description: Set adc2 arbiterapb priority.*/
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: adc2 arbiter force grant*/
/*description: adc2 arbiter force grant.*/
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable wifi controller*/
/*description: adc2 arbiter force to enable wifi controller.*/
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enable rtc controller*/
/*description: adc2 arbiter force to enable rtc controller.*/
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: adc2 arbiter force to enableapb controller*/
/*description: adc2 arbiter force to enableapb controller.*/
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x03C)
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x3C)
/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: enable apb_adc1_filter*/
/*description: enable apb_adc1_filter.*/
#define APB_SARADC_FILTER_RESET (BIT(31))
#define APB_SARADC_FILTER_RESET_M (BIT(31))
#define APB_SARADC_FILTER_RESET_V 0x1
#define APB_SARADC_FILTER_RESET_S 31
/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */
/*description: apb_adc1_filter_factor*/
/*description: apb_adc1_filter_factor.*/
#define APB_SARADC_FILTER_CHANNEL0 0x0000001F
#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
#define APB_SARADC_FILTER_CHANNEL0_V 0x1F
#define APB_SARADC_FILTER_CHANNEL0_S 19
/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */
/*description: */
/*description: .*/
#define APB_SARADC_FILTER_CHANNEL1 0x0000001F
#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
#define APB_SARADC_FILTER_CHANNEL1_V 0x1F
#define APB_SARADC_FILTER_CHANNEL1_S 14
#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040)
#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x40)
/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC1_DATA 0x0001FFFF
#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
#define APB_SARADC_ADC1_DATA_V 0x1FFFF
#define APB_SARADC_ADC1_DATA_S 0
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044)
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x44)
/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
/*description: saradc1's thres0 monitor thres*/
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES0_LOW 0x00001FFF
#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
#define APB_SARADC_THRES0_LOW_V 0x1FFF
#define APB_SARADC_THRES0_LOW_S 18
/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
/*description: saradc1's thres0 monitor thres*/
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES0_HIGH 0x00001FFF
#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
#define APB_SARADC_THRES0_HIGH_S 5
/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_CHANNEL 0x0000001F
#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
#define APB_SARADC_THRES0_CHANNEL_V 0x1F
#define APB_SARADC_THRES0_CHANNEL_S 0
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x048)
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x48)
/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
/*description: saradc1's thres0 monitor thres*/
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES1_LOW 0x00001FFF
#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
#define APB_SARADC_THRES1_LOW_V 0x1FFF
#define APB_SARADC_THRES1_LOW_S 18
/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
/*description: saradc1's thres0 monitor thres*/
/*description: saradc1's thres0 monitor thres.*/
#define APB_SARADC_THRES1_HIGH 0x00001FFF
#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
#define APB_SARADC_THRES1_HIGH_S 5
/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_CHANNEL 0x0000001F
#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
#define APB_SARADC_THRES1_CHANNEL_V 0x1F
#define APB_SARADC_THRES1_CHANNEL_S 0
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058)
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_EN (BIT(31))
#define APB_SARADC_THRES0_EN_M (BIT(31))
#define APB_SARADC_THRES0_EN_V 0x1
#define APB_SARADC_THRES0_EN_S 31
/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_EN (BIT(30))
#define APB_SARADC_THRES1_EN_M (BIT(30))
#define APB_SARADC_THRES1_EN_V 0x1
#define APB_SARADC_THRES1_EN_S 30
/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES2_EN (BIT(29))
#define APB_SARADC_THRES2_EN_M (BIT(29))
#define APB_SARADC_THRES2_EN_V 0x1
#define APB_SARADC_THRES2_EN_S 29
/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES3_EN (BIT(28))
#define APB_SARADC_THRES3_EN_M (BIT(28))
#define APB_SARADC_THRES3_EN_V 0x1
#define APB_SARADC_THRES3_EN_S 28
/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
#define APB_SARADC_THRES_ALL_EN_V 0x1
#define APB_SARADC_THRES_ALL_EN_S 27
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x05C)
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x5C)
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29
/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28
/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES0_LOW_INT_ENA_S 27
/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x060)
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x60)
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29
/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1
#define APB_SARADC_THRES0_LOW_INT_RAW_S 27
/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1
#define APB_SARADC_THRES1_LOW_INT_RAW_S 26
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x064)
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x64)
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_ST_S 29
/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_ST_S 28
/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES0_LOW_INT_ST_S 27
/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x068)
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x68)
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29))
#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29
/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27))
#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1
#define APB_SARADC_THRES0_LOW_INT_CLR_S 27
/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26))
#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1
#define APB_SARADC_THRES1_LOW_INT_CLR_S 26
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x06c)
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x6C)
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
/*description: enable apb_adc use spi_dma*/
/*description: enable apb_adc use spi_dma.*/
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
#define APB_SARADC_APB_ADC_TRANS_V 0x1
#define APB_SARADC_APB_ADC_TRANS_S 31
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: reset_apb_adc_state*/
/*description: reset_apb_adc_state.*/
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x070)
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x70)
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
/*description: Set this bit to enable clk_apll*/
/*description: Set this bit to enable clk_apll.*/
#define APB_SARADC_CLK_SEL 0x00000003
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
#define APB_SARADC_CLK_SEL_V 0x3
#define APB_SARADC_CLK_SEL_S 21
/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_CLK_EN (BIT(20))
#define APB_SARADC_CLK_EN_M (BIT(20))
#define APB_SARADC_CLK_EN_V 0x1
#define APB_SARADC_CLK_EN_S 20
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
/*description: Fractional clock divider denominator value*/
/*description: Fractional clock divider denominator value.*/
#define APB_SARADC_CLKM_DIV_A 0x0000003F
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
#define APB_SARADC_CLKM_DIV_A_V 0x3F
#define APB_SARADC_CLKM_DIV_A_S 14
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
/*description: Fractional clock divider numerator value*/
/*description: Fractional clock divider numerator value.*/
#define APB_SARADC_CLKM_DIV_B 0x0000003F
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
#define APB_SARADC_CLKM_DIV_B_V 0x3F
#define APB_SARADC_CLKM_DIV_B_S 8
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
/*description: Integral I2S clock divider value*/
/*description: Integral I2S clock divider value.*/
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
#define APB_SARADC_CLKM_DIV_NUM_S 0
#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x074)
/* APB_SARADC_DAC_CLK_GATE_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_DAC_CLK_GATE_EN (BIT(18))
#define APB_SARADC_DAC_CLK_GATE_EN_M (BIT(18))
#define APB_SARADC_DAC_CLK_GATE_EN_V 0x1
#define APB_SARADC_DAC_CLK_GATE_EN_S 18
/* APB_SARADC_DAC_CLK_FO : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_DAC_CLK_FO (BIT(17))
#define APB_SARADC_DAC_CLK_FO_M (BIT(17))
#define APB_SARADC_DAC_CLK_FO_V 0x1
#define APB_SARADC_DAC_CLK_FO_S 17
/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_APB_DAC_RST (BIT(16))
#define APB_SARADC_APB_DAC_RST_M (BIT(16))
#define APB_SARADC_APB_DAC_RST_V 0x1
#define APB_SARADC_APB_DAC_RST_S 16
/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_DAC_RESET_FIFO (BIT(15))
#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15))
#define APB_SARADC_DAC_RESET_FIFO_V 0x1
#define APB_SARADC_DAC_RESET_FIFO_S 15
/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: enable dma_dac*/
#define APB_SARADC_APB_DAC_TRANS (BIT(14))
#define APB_SARADC_APB_DAC_TRANS_M (BIT(14))
#define APB_SARADC_APB_DAC_TRANS_V 0x1
#define APB_SARADC_APB_DAC_TRANS_S 14
/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: enable dac alter mode*/
#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13))
#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13))
#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1
#define APB_SARADC_APB_DAC_ALTER_MODE_S 13
/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: enable read dac data*/
#define APB_SARADC_DAC_TIMER_EN (BIT(12))
#define APB_SARADC_DAC_TIMER_EN_M (BIT(12))
#define APB_SARADC_DAC_TIMER_EN_V 0x1
#define APB_SARADC_DAC_TIMER_EN_S 12
/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */
/*description: dac_timer target*/
#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF
#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V) << (APB_SARADC_DAC_TIMER_TARGET_S))
#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF
#define APB_SARADC_DAC_TIMER_TARGET_S 0
#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x078)
#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x78)
/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
/*description: */
/*description: .*/
#define APB_SARADC_ADC2_DATA 0x0001FFFF
#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
#define APB_SARADC_ADC2_DATA_S 0
#define APB_SARADC_APB_DAC_CLK_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x07c)
/* APB_SARADC_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
/*description: */
#define APB_SARADC_DAC_CLK_DIV 0x000000FF
#define APB_SARADC_DAC_CLK_DIV_M ((APB_SARADC_DAC_CLK_DIV_V) << (APB_SARADC_DAC_CLK_DIV_S))
#define APB_SARADC_DAC_CLK_DIV_V 0xFF
#define APB_SARADC_DAC_CLK_DIV_S 0
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02003060 ; */
/*description: */
/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02101180 ; */
/*description: .*/
#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF
#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S))
#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF
#define APB_SARADC_APB_CTRL_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_REG_H_ */

107
components/soc/esp32s3/include/soc/apb_saradc_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_APB_SARADC_STRUCT_H_
#define _SOC_APB_SARADC_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
@@ -25,16 +26,16 @@ typedef volatile struct {
uint32_t start_force : 1;
uint32_t start : 1;
uint32_t reserved2 : 1;
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
uint32_t work_mode : 2; /* 0: single mode, 1: double mode, 2: alternate mode*/
uint32_t sar_sel : 1; /* 0: SAR1, 1: SAR2, only work for single SAR mode*/
uint32_t sar_clk_gated : 1;
uint32_t sar_clk_div : 8; /*SAR clock divider*/
uint32_t sar1_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/
uint32_t sar2_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/
uint32_t sar1_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
uint32_t sar2_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t data_sar_sel : 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.*/
uint32_t data_to_i2s : 1; /*1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix*/
uint32_t xpd_sar_force : 2; /*force option to xpd sar blocks*/
uint32_t reserved29 : 1;
uint32_t wait_arb_cycle : 2; /*wait arbit signal stable after sar_done*/
@@ -45,8 +46,8 @@ typedef volatile struct {
struct {
uint32_t meas_num_limit : 1;
uint32_t max_meas_num : 8; /*max conversion number*/
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
uint32_t sar1_inv : 1; /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/
uint32_t sar2_inv : 1; /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/
uint32_t timer_sel : 1; /*1: select saradc timer 0: i2s_ws trigger*/
uint32_t timer_target : 12; /*to set saradc timer target*/
uint32_t timer_en : 1; /*to enable saradc timer trigger*/
@@ -71,64 +72,22 @@ typedef volatile struct {
};
uint32_t val;
} fsm_wait;
uint32_t sar1_status; /**/
uint32_t sar2_status; /**/
uint32_t sar1_status;
uint32_t sar2_status;
union {
struct {
uint32_t sar1_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t sar1_patt_tab : 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
uint32_t reserved24 : 8;
};
uint32_t val;
} sar1_patt_tab1;
} sar1_patt_tab[4];
union {
struct {
uint32_t sar1_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
uint32_t sar2_patt_tab : 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
uint32_t reserved24 : 8;
};
uint32_t val;
} sar1_patt_tab2;
union {
struct {
uint32_t sar1_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar1_patt_tab3;
union {
struct {
uint32_t sar1_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar1_patt_tab4;
union {
struct {
uint32_t sar2_patt_tab1: 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab1;
union {
struct {
uint32_t sar2_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab2;
union {
struct {
uint32_t sar2_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab3;
union {
struct {
uint32_t sar2_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
uint32_t reserved24: 8;
};
uint32_t val;
} sar2_patt_tab4;
} sar2_patt_tab[4];
union {
struct {
uint32_t reserved0 : 2;
@@ -166,6 +125,7 @@ typedef volatile struct {
uint32_t thres0_channel : 5;
uint32_t thres0_high : 13; /*saradc1's thres0 monitor thres*/
uint32_t thres0_low : 13; /*saradc1's thres0 monitor thres*/
uint32_t reserved31 : 1;
};
uint32_t val;
} thres0_ctrl;
@@ -260,20 +220,7 @@ typedef volatile struct {
};
uint32_t val;
} apb_adc_clkm_conf;
union {
struct {
uint32_t dac_timer_target: 12; /*dac_timer target*/
uint32_t dac_timer_en: 1; /*enable read dac data*/
uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/
uint32_t apb_dac_trans: 1; /*enable dma_dac*/
uint32_t dac_reset_fifo: 1;
uint32_t apb_dac_rst: 1;
uint32_t dac_clk_fo: 1;
uint32_t dac_clk_gate_en: 1;
uint32_t reserved19: 13;
};
uint32_t val;
} apb_dac_ctrl;
uint32_t reserved_74;
union {
struct {
uint32_t adc2_data : 17;
@@ -281,13 +228,7 @@ typedef volatile struct {
};
uint32_t val;
} apb_saradc2_data_status;
union {
struct {
uint32_t dac_clk_div: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} apb_dac_clk_ctrl;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
@@ -511,11 +452,13 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /**/
uint32_t apb_ctrl_date;
} apb_saradc_dev_t;
extern apb_saradc_dev_t APB_SARADC;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_APB_SARADC_STRUCT_H_ */

131
components/soc/esp32s3/include/soc/cpu.h Normal file
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@@ -0,0 +1,131 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "xtensa/corebits.h"
/* C macros for xtensa special register read/write/exchange */
#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
return sp;
}
/* Functions to set page attributes for Region Protection option in the CPU.
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
*/
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
{
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
{
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
/**
* @brief Configure memory region protection
*
* Make page 0 access raise an exception.
* Also protect some other unused pages so we can catch weirdness.
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect) / sizeof(pages_to_protect[0]); ++i) {
cpu_write_dtlb(pages_to_protect[i], 0xf);
cpu_write_itlb(pages_to_protect[i], 0xf);
}
cpu_write_dtlb(0x20000000, 0);
cpu_write_itlb(0x20000000, 0);
}
/**
* @brief Stall CPU using RTC controller
* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
*/
void esp_cpu_stall(int cpu_id);
/**
* @brief Un-stall CPU using RTC controller
* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
*/
void esp_cpu_unstall(int cpu_id);
/**
* @brief Reset CPU using RTC controller
* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
*/
void esp_cpu_reset(int cpu_id);
/**
* @brief Returns true if a JTAG debugger is attached to CPU
* OCD (on chip debug) port.
*
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address
*
* The address of the current instruction is not stored as an exact uint32_t
* representation in PC register. This function will convert the value stored in
* the PC register to a uint32_t address.
*
* @param pc_raw The PC as stored in register format.
*
* @return Address in uint32_t format
*/
static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
{
if (pc & 0x80000000) {
//Top two bits of a0 (return address) specify window increment. Overwrite to map to address space.
pc = (pc & 0x3fffffff) | 0x40000000;
}
//Minus 3 to get PC of previous instruction (i.e. instruction executed before return address)
return pc - 3;
}
typedef uint32_t esp_cpu_ccount_t;
static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
{
uint32_t result;
RSR(CCOUNT, result);
return result;
}

1375
components/soc/esp32s3/include/soc/efuse_reg.h
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412
components/soc/esp32s3/include/soc/efuse_struct.h
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@@ -11,116 +11,303 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_EFUSE_STRUCT_H_
#define _SOC_EFUSE_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t reserved_c;
uint32_t reserved_10;
uint32_t reserved_14;
uint32_t reserved_18;
uint32_t reserved_1c;
uint32_t reserved_20;
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t pgm_data0;
uint32_t pgm_data1;
uint32_t pgm_data2;
uint32_t pgm_data3;
uint32_t pgm_data4;
uint32_t pgm_data5;
uint32_t pgm_data6;
uint32_t pgm_data7;
uint32_t pgm_check_value0;
uint32_t pgm_check_value1;
uint32_t pgm_check_value2;
uint32_t rd_wr_dis;
union {
struct {
uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/
uint32_t reg_dis_rtc_ram_boot : 1; /*Set this bit to disable boot from RTC RAM.*/
uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/
uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/
uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/
uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/
uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/
uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/
uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/
uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/
uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/
uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/
uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/
uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/
uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/
uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/
uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/
uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/
uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/
};
uint32_t val;
} rd_repeat_data0;
union {
struct {
uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/
uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/
uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/
uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/
uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/
uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/
uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/
uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/
uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/
uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/
uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/
uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/
uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/
uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/
uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/
};
uint32_t val;
} rd_repeat_data1;
union {
struct {
uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/
uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/
uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/
uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/
uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/
uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/
uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/
uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/
uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/
uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/
uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/
uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/
};
uint32_t val;
} rd_repeat_data2;
union {
struct {
uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/
uint32_t reg_dis_legacy_spi_boot : 1; /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
uint32_t reg_uart_print_channel : 1; /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/
uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/
uint32_t reg_dis_usb_download_mode : 1; /*Set this bit to disable UART download mode through USB.*/
uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/
uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/
uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/
uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/
uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
uint32_t reg_powerglitch_en : 1; /*Set this bit to enable power glitch function.*/
uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/
};
uint32_t val;
} rd_repeat_data3;
union {
struct {
uint32_t reg_rpt4_reserved2 : 24; /*Reserved (used for four backups method).*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
} rd_repeat_data4;
uint32_t rd_mac_spi_sys_0;
union {
struct {
uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/
uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/
};
uint32_t val;
} rd_mac_spi_sys_1;
uint32_t rd_mac_spi_sys_2;
union {
struct {
uint32_t reg_spi_pad_conf_2 : 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t reg_sys_data_part0_0 : 14; /*Stores the fist 14 bits of the zeroth part of system data.*/
};
uint32_t val;
} rd_mac_spi_sys_3;
uint32_t rd_mac_spi_sys_4;
uint32_t rd_mac_spi_sys_5;
uint32_t rd_sys_part1_data0;
uint32_t rd_sys_part1_data1;
uint32_t rd_sys_part1_data2;
uint32_t rd_sys_part1_data3;
uint32_t rd_sys_part1_data4;
uint32_t rd_sys_part1_data5;
uint32_t rd_sys_part1_data6;
uint32_t rd_sys_part1_data7;
uint32_t rd_usr_data0;
uint32_t rd_usr_data1;
uint32_t rd_usr_data2;
uint32_t rd_usr_data3;
uint32_t rd_usr_data4;
uint32_t rd_usr_data5;
uint32_t rd_usr_data6;
uint32_t rd_usr_data7;
uint32_t rd_key0_data0;
uint32_t rd_key0_data1;
uint32_t rd_key0_data2;
uint32_t rd_key0_data3;
uint32_t rd_key0_data4;
uint32_t rd_key0_data5;
uint32_t rd_key0_data6;
uint32_t rd_key0_data7;
uint32_t rd_key1_data0;
uint32_t rd_key1_data1;
uint32_t rd_key1_data2;
uint32_t rd_key1_data3;
uint32_t rd_key1_data4;
uint32_t rd_key1_data5;
uint32_t rd_key1_data6;
uint32_t rd_key1_data7;
uint32_t rd_key2_data0;
uint32_t rd_key2_data1;
uint32_t rd_key2_data2;
uint32_t rd_key2_data3;
uint32_t rd_key2_data4;
uint32_t rd_key2_data5;
uint32_t rd_key2_data6;
uint32_t rd_key2_data7;
uint32_t rd_key3_data0;
uint32_t rd_key3_data1;
uint32_t rd_key3_data2;
uint32_t rd_key3_data3;
uint32_t rd_key3_data4;
uint32_t rd_key3_data5;
uint32_t rd_key3_data6;
uint32_t rd_key3_data7;
uint32_t rd_key4_data0;
uint32_t rd_key4_data1;
uint32_t rd_key4_data2;
uint32_t rd_key4_data3;
uint32_t rd_key4_data4;
uint32_t rd_key4_data5;
uint32_t rd_key4_data6;
uint32_t rd_key4_data7;
uint32_t rd_key5_data0;
uint32_t rd_key5_data1;
uint32_t rd_key5_data2;
uint32_t rd_key5_data3;
uint32_t rd_key5_data4;
uint32_t rd_key5_data5;
uint32_t rd_key5_data6;
uint32_t rd_key5_data7;
uint32_t rd_sys_part2_data0;
uint32_t rd_sys_part2_data1;
uint32_t rd_sys_part2_data2;
uint32_t rd_sys_part2_data3;
uint32_t rd_sys_part2_data4;
uint32_t rd_sys_part2_data5;
uint32_t rd_sys_part2_data6;
uint32_t rd_sys_part2_data7;
union {
struct {
uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_rtc_ram_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
};
uint32_t val;
} rd_repeat_err0;
union {
struct {
uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
};
uint32_t val;
} rd_repeat_err1;
union {
struct {
uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/
};
uint32_t val;
} rd_repeat_err2;
union {
struct {
uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_legacy_spi_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_uart_print_channel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_dis_usb_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reg_powerglitch_en_err : 1;
uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/
};
uint32_t val;
} rd_repeat_err3;
uint32_t reserved_18c;
uint32_t reserved_190;
union {
struct {
uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
} rd_repeat_err4;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
@@ -248,21 +435,12 @@ typedef volatile struct {
} dac_conf;
union {
struct {
uint32_t thr_a: 8; /*Configures the hold time of read operation.*/
uint32_t trd: 8; /*Configures the length of pulse of read operation.*/
uint32_t tsur_a: 8; /*Configures the setup time of read operation.*/
uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/
uint32_t reserved0 : 24; /*Reserved. (Default read timing parameter)*/
uint32_t reg_read_init_num : 8; /*Configures the initial read time of eFuse.*/
};
uint32_t val;
} rd_tim_conf;
union {
struct {
uint32_t thp_a: 8; /*Configures the hold time of programming operation.*/
uint32_t tpgm_inactive: 8; /*Configures the length of pulse during programming 0 to eFuse.*/
uint32_t tpgm: 16; /*Configures the length of pulse during programming 1 to eFuse.*/
};
uint32_t val;
} wr_tim_conf0;
uint32_t wr_tim_conf0;
union {
struct {
uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/
@@ -292,3 +470,7 @@ extern efuse_dev_t EFUSE;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_EFUSE_STRUCT_H_ */

875
components/soc/esp32s3/include/soc/extmem_reg.h
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81
components/soc/esp32s3/include/soc/extmem_struct.h
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@@ -22,27 +22,27 @@ extern "C" {
typedef volatile struct {
union {
struct {
uint32_t dcache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/
uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/
uint32_t reserved1 : 1; /*Reserved*/
uint32_t dcache_size_mode: 1; /*The bit is used to configure cache memory size.0: 32KB 1: 64KB*/
uint32_t dcache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/
uint32_t reserved4: 28;
uint32_t dcache_size_mode : 1; /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/
uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/
uint32_t reserved5 : 27;
};
uint32_t val;
} dcache_ctrl;
union {
struct {
uint32_t dcache_shut_core0_bus: 1; /*The bit is used to disable core0 dbus 0: enable 1: disable*/
uint32_t dcache_shut_core1_bus: 1; /*The bit is used to disable core1 dbus 0: enable 1: disable*/
uint32_t dcache_shut_core0_bus : 1; /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/
uint32_t dcache_shut_core1_bus : 1; /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/
uint32_t reserved2 : 30;
};
uint32_t val;
} dcache_ctrl1;
union {
struct {
uint32_t dcache_tag_mem_force_on: 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating 0: open clock gating.*/
uint32_t dcache_tag_mem_force_pd: 1; /*The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd 1: power down*/
uint32_t dcache_tag_mem_force_pu: 1; /*The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd 1: power up*/
uint32_t dcache_tag_mem_force_on : 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/
uint32_t dcache_tag_mem_force_pd : 1; /*The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down*/
uint32_t dcache_tag_mem_force_pu : 1; /*The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up*/
uint32_t reserved3 : 29;
};
uint32_t val;
@@ -141,7 +141,8 @@ typedef volatile struct {
uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t reserved9: 23;
uint32_t dcache_autoload_buffer_clear: 1; /*The bit is used to clear autoload buffer in dcache.*/
uint32_t reserved10: 22;
};
uint32_t val;
} dcache_autoload_ctrl;
@@ -259,27 +260,28 @@ typedef volatile struct {
struct {
uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/
uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable 0: disable.*/
uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
uint32_t reserved9: 23;
uint32_t icache_autoload_buffer_clear: 1; /*The bit is used to clear autoload buffer in icache.*/
uint32_t reserved10: 22;
};
uint32_t val;
} icache_autoload_ctrl;
uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
union {
struct {
uint32_t icache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
uint32_t icache_autoload_sct0_size:27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
uint32_t reserved27: 5;
};
uint32_t val;
} icache_autoload_sct0_size;
uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
union {
struct {
uint32_t icache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
uint32_t icache_autoload_sct1_size:27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
uint32_t reserved27: 5;
};
uint32_t val;
@@ -515,31 +517,31 @@ typedef volatile struct {
} cache_bridge_arbiter_ctrl;
union {
struct {
uint32_t icache_preload: 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/
uint32_t icache_preload: 1; /*The bit is used to enable the interrupt by icache pre-load done.*/
uint32_t icache_preload: 1; /*The bit is used to clear the interrupt by icache pre-load done.*/
uint32_t dcache_preload: 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/
uint32_t dcache_preload: 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
uint32_t dcache_preload: 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
uint32_t icache_preload_ist : 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/
uint32_t icache_preload_iena : 1; /*The bit is used to enable the interrupt by icache pre-load done.*/
uint32_t icache_preload_iclr : 1; /*The bit is used to clear the interrupt by icache pre-load done.*/
uint32_t dcache_preload_ist : 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/
uint32_t dcache_preload_iena : 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
uint32_t dcache_preload_iclr : 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} cache_preload_int_ctrl;
union {
struct {
uint32_t icache_sync: 1; /*The bit is used to indicate the interrupt by icache sync done.*/
uint32_t icache_sync: 1; /*The bit is used to enable the interrupt by icache sync done.*/
uint32_t icache_sync: 1; /*The bit is used to clear the interrupt by icache sync done.*/
uint32_t dcache_sync: 1; /*The bit is used to indicate the interrupt by dcache sync done.*/
uint32_t dcache_sync: 1; /*The bit is used to enable the interrupt by dcache sync done.*/
uint32_t dcache_sync: 1; /*The bit is used to clear the interrupt by dcache sync done.*/
uint32_t icache_sync_ist : 1; /*The bit is used to indicate the interrupt by icache sync done.*/
uint32_t icache_sync_iena : 1; /*The bit is used to enable the interrupt by icache sync done.*/
uint32_t icache_sync_iclr : 1; /*The bit is used to clear the interrupt by icache sync done.*/
uint32_t dcache_sync_ist : 1; /*The bit is used to indicate the interrupt by dcache sync done.*/
uint32_t dcache_sync_iena : 1; /*The bit is used to enable the interrupt by dcache sync done.*/
uint32_t dcache_sync_iclr : 1; /*The bit is used to clear the interrupt by dcache sync done.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} cache_sync_int_ctrl;
union {
struct {
uint32_t cache_mmu_owner: 24; /*The bits are used to specify the owner of MMU.bit0: icache bit1: dcache bit2: dma bit3: reserved.*/
uint32_t cache_mmu_owner : 24; /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/
uint32_t reserved24 : 8;
};
uint32_t val;
@@ -605,10 +607,23 @@ typedef volatile struct {
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
union {
struct {
uint32_t icache_tag_object: 1; /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
uint32_t dcache_tag_object: 1; /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
uint32_t reserved2: 30; /*Reserved*/
};
uint32_t val;
} cache_tag_object_ctrl;
union {
struct {
uint32_t cache_tag_way_object: 3; /*Set this bits to select which way of the tag-object will be accessed. 0: way0 1: way1 2: way2 3: way3 .. 7: way7.*/
uint32_t reserved3: 29; /*Reserved*/
};
uint32_t val;
} cache_tag_way_object;
uint32_t cache_vaddr; /*Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed.*/
uint32_t cache_tag_content; /*This is a constant place where we can write data to or read data from the tag memory on the specified cache.*/
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;

10003
components/soc/esp32s3/include/soc/gdma_reg.h
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377
components/soc/esp32s3/include/soc/gdma_struct.h
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@@ -1,4 +1,4 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -13,138 +13,99 @@
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
struct {
union {
struct {
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t in_loop_test : 1; /*reserved*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
uint32_t reserved11 : 21; /*reserved*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} conf0[5];
} conf0;
union {
struct {
uint32_t infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
uint32_t check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved17 : 15; /*reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1[5];
} conf1;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/
uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */
uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow.*/
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow.*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_raw[5];
uint32_t reserved_3c;
} int_raw;
union {
struct {
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_st[5];
} int_st;
union {
struct {
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_ena[5];
} int_ena;
union {
struct {
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} int_clr[5];
} int_clr;
union {
struct {
uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
@@ -164,7 +125,153 @@ typedef volatile struct {
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} infifo_status[5];
} infifo_status;
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} pop;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} link;
union {
struct {
uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} state;
uint32_t suc_eof_des_addr;
uint32_t err_eof_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t rx_weight : 4; /*The weight of Rx channel 0. */
uint32_t reserved4 : 28;
};
uint32_t val;
} wight;
union {
struct {
uint32_t in_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} sram_size;
union {
struct {
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
} in[5];
struct {
union {
struct {
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
uint32_t out_loop_test : 1; /*reserved*/
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
uint32_t reserved6 : 26;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t reserved0 : 12;
uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
uint32_t reserved15 : 17; /*reserved*/
};
uint32_t val;
} conf1;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
@@ -183,7 +290,7 @@ typedef volatile struct {
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} outfifo_status[5];
} outfifo_status;
union {
struct {
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
@@ -191,15 +298,7 @@ typedef volatile struct {
uint32_t reserved10 : 22; /*reserved*/
};
uint32_t val;
} out_push[5];
union {
struct {
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
uint32_t reserved13 : 19; /*reserved*/
};
uint32_t val;
} in_pop[5];
} push;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
@@ -210,41 +309,55 @@ typedef volatile struct {
uint32_t reserved24 : 8;
};
uint32_t val;
} out_link[5];
} link;
union {
struct {
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
uint32_t reserved25 : 7;
};
uint32_t val;
} in_link[5];
union {
struct {
uint32_t inlink_dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
uint32_t in_dscr_state : 2; /*reserved*/
uint32_t in_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} in_state[5];
union {
struct {
uint32_t outlink_dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
uint32_t out_dscr_state : 2; /*reserved*/
uint32_t out_state : 3; /*reserved*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} out_state[5];
uint32_t out_eof_des_addr[5]; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/
uint32_t in_suc_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/
uint32_t in_err_eof_des_addr[5]; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/
uint32_t out_eof_bfr_des_addr[5]; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/
} state;
uint32_t eof_des_addr;
uint32_t eof_bfr_des_addr;
uint32_t dscr;
uint32_t dscr_bf0;
uint32_t dscr_bf1;
union {
struct {
uint32_t tx_weight : 4; /*The weight of Tx channel 0. */
uint32_t reserved4 : 28;
};
uint32_t val;
} wight;
union {
struct {
uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
uint32_t reserved5 : 27;
};
uint32_t val;
} sram_size;
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
uint32_t reserved4 : 28;
};
uint32_t val;
} pri;
union {
struct {
uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: LCD_CAM; 7: AES. 8: SHA. 9: ADC_DAC.*/
uint32_t reserved6 : 26;
};
uint32_t val;
} peri_sel;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
} out[5];
union {
struct {
uint32_t ahb_testmode : 3; /*reserved*/
@@ -254,71 +367,29 @@ typedef volatile struct {
};
uint32_t val;
} ahb_test;
uint32_t in_dscr[5]; /*The address of the current inlink descriptor x.*/
uint32_t in_dscr_bf0[5]; /*The address of the last inlink descriptor x-1.*/
uint32_t in_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor x-2.*/
uint32_t out_dscr[5]; /*The address of the current outlink descriptor y.*/
uint32_t out_dscr_bf0[5]; /*The address of the last outlink descriptor y-1.*/
uint32_t out_dscr_bf1[5]; /*The address of the second-to-last inlink descriptor y-2.*/
union {
struct {
uint32_t reserved0 : 4; /*reserved*/
uint32_t ram_force_pd : 1; /*power down*/
uint32_t ram_force_pu : 1;
uint32_t ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/
uint32_t reserved7 : 25; /*reserved*/
uint32_t dma_ram_force_pd : 1; /*power down*/
uint32_t dma_ram_force_pu : 1;
uint32_t dma_ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/
uint32_t reserved7 : 25;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t tx_weight : 4; /*The weight of Tx channel 0.*/
uint32_t rx_weight : 4; /*The weight of Rx channel 0.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} wight[5];
union {
struct {
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} pri[5];
union {
struct {
uint32_t ahbm_rst_inter : 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/
uint32_t ahbm_rst_exter : 1; /*Set this bit then clear this bit to reset the external ahb FSM.*/
uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/
uint32_t ahbm_rst_exter : 1; /*Set this bit, then clear this bit to reset the external ahb FSM.*/
uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/
uint32_t clk_en : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} misc_conf;
union {
struct {
uint32_t peri_in_sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2*/
uint32_t peri_out_sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2*/
uint32_t reserved12 : 20;
};
uint32_t val;
} peri_sel[5];
union {
struct {
uint32_t in_size : 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 0. 0:16 bytes*/
uint32_t out_size : 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes*/
uint32_t reserved10 : 22;
};
uint32_t val;
} sram_size[5];
uint32_t date; /*register version.*/
uint32_t date;
} gdma_dev_t;
_Static_assert(sizeof(gdma_dev_t) == 0x244, "incorrect size of gdma_dev_t.");
extern gdma_dev_t GDMA;
#ifdef __cplusplus
}
#endif

74
components/soc/esp32s3/include/soc/gpio_sd_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,156 +11,162 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_GPIO_SD_REG_H_
#define _SOC_GPIO_SD_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0_PRESCALE_V 0xFF
#define GPIO_SD0_PRESCALE_S 8
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD0_IN 0x000000FF
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
#define GPIO_SD0_IN_V 0xFF
#define GPIO_SD0_IN_S 0
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD1_PRESCALE 0x000000FF
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
#define GPIO_SD1_PRESCALE_V 0xFF
#define GPIO_SD1_PRESCALE_S 8
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD1_IN 0x000000FF
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
#define GPIO_SD1_IN_V 0xFF
#define GPIO_SD1_IN_S 0
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD2_PRESCALE 0x000000FF
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
#define GPIO_SD2_PRESCALE_V 0xFF
#define GPIO_SD2_PRESCALE_S 8
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD2_IN 0x000000FF
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
#define GPIO_SD2_IN_V 0xFF
#define GPIO_SD2_IN_S 0
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xC)
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD3_PRESCALE 0x000000FF
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
#define GPIO_SD3_PRESCALE_V 0xFF
#define GPIO_SD3_PRESCALE_S 8
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD3_IN 0x000000FF
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
#define GPIO_SD3_IN_V 0xFF
#define GPIO_SD3_IN_S 0
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x10)
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD4_PRESCALE 0x000000FF
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
#define GPIO_SD4_PRESCALE_V 0xFF
#define GPIO_SD4_PRESCALE_S 8
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD4_IN 0x000000FF
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
#define GPIO_SD4_IN_V 0xFF
#define GPIO_SD4_IN_S 0
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x14)
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD5_PRESCALE 0x000000FF
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
#define GPIO_SD5_PRESCALE_V 0xFF
#define GPIO_SD5_PRESCALE_S 8
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD5_IN 0x000000FF
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
#define GPIO_SD5_IN_V 0xFF
#define GPIO_SD5_IN_S 0
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x18)
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD6_PRESCALE 0x000000FF
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
#define GPIO_SD6_PRESCALE_V 0xFF
#define GPIO_SD6_PRESCALE_S 8
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD6_IN 0x000000FF
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
#define GPIO_SD6_IN_V 0xFF
#define GPIO_SD6_IN_S 0
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x1C)
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
/*description: .*/
#define GPIO_SD7_PRESCALE 0x000000FF
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
#define GPIO_SD7_PRESCALE_V 0xFF
#define GPIO_SD7_PRESCALE_S 8
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD7_IN 0x000000FF
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
#define GPIO_SD7_IN_V 0xFF
#define GPIO_SD7_IN_S 0
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SD_CLK_EN (BIT(31))
#define GPIO_SD_CLK_EN_M (BIT(31))
#define GPIO_SD_CLK_EN_V 0x1
#define GPIO_SD_CLK_EN_S 31
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define GPIO_SPI_SWAP (BIT(31))
#define GPIO_SPI_SWAP_M (BIT(31))
#define GPIO_SPI_SWAP_V 0x1
#define GPIO_SPI_SWAP_S 31
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define GPIO_FUNCTION_CLK_EN (BIT(30))
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
#define GPIO_FUNCTION_CLK_EN_V 0x1
#define GPIO_FUNCTION_CLK_EN_S 30
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x28)
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
/*description: */
/*description: .*/
#define GPIO_SD_DATE 0x0FFFFFFF
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
#define GPIO_SD_DATE_V 0xFFFFFFF
#define GPIO_SD_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIO_REG_H_ */

15
components/soc/esp32s3/include/soc/gpio_sd_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_GPIO_SD_STRUCT_H_
#define _SOC_GPIO_SD_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
@@ -51,9 +52,11 @@ typedef volatile struct {
uint32_t val;
} version;
} gpio_sd_dev_t;
extern gpio_sd_dev_t SIGMADELTA;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_GPIO_STRUCT_H_ */

43
components/soc/esp32s3/include/soc/gpio_sig_map.h
View File

@@ -118,7 +118,8 @@
#define BB_DIAG17_IDX 52
#define I2S0I_SD3_IN_IDX 53
#define BB_DIAG18_IDX 53
#define BB_DIAG19_IDX 54
#define CORE1_GPIO_IN7_IDX 54
#define CORE1_GPIO_OUT7_IDX 54
#define USB_EXTPHY_VP_IDX 55
#define USB_EXTPHY_OEN_IDX 55
#define USB_EXTPHY_VM_IDX 56
@@ -168,6 +169,10 @@
#define RMT_SIG_OUT2_IDX 83
#define RMT_SIG_IN3_IDX 84
#define RMT_SIG_OUT3_IDX 84
#define USB_JTAG_TCK_IDX 85
#define USB_JTAG_TMS_IDX 86
#define USB_JTAG_TDI_IDX 87
#define USB_JTAG_TDO_IDX 88
#define I2CEXT0_SCL_IN_IDX 89
#define I2CEXT0_SCL_OUT_IDX 89
#define I2CEXT0_SDA_IN_IDX 90
@@ -226,6 +231,13 @@
#define SUBSPICS1_OUT_IDX 125
#define FSPIDQS_OUT_IDX 126
#define SPI3_CS2_OUT_IDX 127
#define I2S0O_SD1_OUT_IDX 128
#define CORE1_GPIO_IN0_IDX 129
#define CORE1_GPIO_OUT0_IDX 129
#define CORE1_GPIO_IN1_IDX 130
#define CORE1_GPIO_OUT1_IDX 130
#define CORE1_GPIO_IN2_IDX 131
#define CORE1_GPIO_OUT2_IDX 131
#define LCD_CS_IDX 132
#define CAM_DATA_IN0_IDX 133
#define LCD_DATA_OUT0_IDX 133
@@ -367,16 +379,16 @@
#define ANT_SEL5_IDX 205
#define ANT_SEL6_IDX 206
#define ANT_SEL7_IDX 207
#define SIG_IN_FUNC_223_IDX 208
#define SIG_IN_FUNC223_IDX 208
#define SIG_IN_FUNC_224_IDX 209
#define SIG_IN_FUNC224_IDX 209
#define SIG_IN_FUNC_225_IDX 210
#define SIG_IN_FUNC225_IDX 210
#define SIG_IN_FUNC_226_IDX 211
#define SIG_IN_FUNC226_IDX 211
#define SIG_IN_FUNC_227_IDX 212
#define SIG_IN_FUNC227_IDX 212
#define SIG_IN_FUNC_208_IDX 208
#define SIG_IN_FUNC208_IDX 208
#define SIG_IN_FUNC_209_IDX 209
#define SIG_IN_FUNC209_IDX 209
#define SIG_IN_FUNC_210_IDX 210
#define SIG_IN_FUNC210_IDX 210
#define SIG_IN_FUNC_211_IDX 211
#define SIG_IN_FUNC211_IDX 211
#define SIG_IN_FUNC_212_IDX 212
#define SIG_IN_FUNC212_IDX 212
#define SDHOST_CDATA_IN_20_IDX 213
#define SDHOST_CDATA_OUT_20_IDX 213
#define SDHOST_CDATA_IN_21_IDX 214
@@ -431,4 +443,13 @@
#define RX_STATUS_IDX 248
#define CLK_GPIO_IDX 249
#define NBT_BLE_IDX 250
#define USB_JTAG_TRST_IDX 251
#define CORE1_GPIO_IN3_IDX 252
#define CORE1_GPIO_OUT3_IDX 252
#define CORE1_GPIO_IN4_IDX 253
#define CORE1_GPIO_OUT4_IDX 253
#define CORE1_GPIO_IN5_IDX 254
#define CORE1_GPIO_OUT5_IDX 254
#define CORE1_GPIO_IN6_IDX 255
#define CORE1_GPIO_OUT6_IDX 255
#define SIG_GPIO_OUT_IDX 256

35
components/soc/esp32s3/include/soc/host_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_HOST_STRUCT_H_
#define _SOC_HOST_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
uint32_t reserved_0;
@@ -39,7 +40,7 @@ typedef volatile struct {
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t gpio_status0; /**/
uint32_t gpio_status0;
union {
struct {
uint32_t sdio_int1 : 22;
@@ -47,7 +48,7 @@ typedef volatile struct {
};
uint32_t val;
} gpio_status1;
uint32_t gpio_in0; /**/
uint32_t gpio_in0;
union {
struct {
uint32_t sdio_in1 : 22;
@@ -65,7 +66,7 @@ typedef volatile struct {
};
uint32_t val;
} slc0_token_rdata;
uint32_t slc0_pf; /**/
uint32_t slc0_pf;
uint32_t reserved_4c;
union {
struct {
@@ -330,8 +331,8 @@ typedef volatile struct {
};
uint32_t val;
} conf_w15;
uint32_t check_sum0; /**/
uint32_t check_sum1; /**/
uint32_t check_sum0;
uint32_t check_sum1;
uint32_t reserved_c4;
union {
struct {
@@ -464,8 +465,8 @@ typedef volatile struct {
uint32_t val;
} slc0_rx_infor;
uint32_t reserved_f8;
uint32_t slc0_len_wd; /**/
uint32_t apbwin_wdata; /**/
uint32_t slc0_len_wd;
uint32_t apbwin_wdata;
union {
struct {
uint32_t addr : 28;
@@ -476,7 +477,7 @@ typedef volatile struct {
};
uint32_t val;
} apbwin_conf;
uint32_t apbwin_rdata; /**/
uint32_t apbwin_rdata;
union {
struct {
uint32_t bit7_clraddr : 9;
@@ -542,8 +543,8 @@ typedef volatile struct {
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t date; /**/
uint32_t id; /**/
uint32_t date;
uint32_t id;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
@@ -596,9 +597,11 @@ typedef volatile struct {
uint32_t val;
} inf_st;
} host_dev_t;
extern host_dev_t HOST;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_HOST_STRUCT_H_ */

572
components/soc/esp32s3/include/soc/i2c_reg.h
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File diff suppressed because it is too large Load Diff

43
components/soc/esp32s3/include/soc/i2c_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -42,7 +42,9 @@ typedef volatile struct {
uint32_t fsm_rst : 1;
uint32_t conf_upgate : 1;
uint32_t slv_tx_auto_start_en : 1;
uint32_t reserved13: 19;
uint32_t addr_10bit_rw_check_en : 1;
uint32_t addr_broadcasting_en : 1;
uint32_t reserved15 : 17;
};
uint32_t val;
} ctr;
@@ -66,10 +68,10 @@ typedef volatile struct {
uint32_t reserved31 : 1;
};
uint32_t val;
} status_reg;
} sr;
union {
struct {
uint32_t time_out_value: 5;
uint32_t tout : 5;
uint32_t time_out_en : 1;
uint32_t reserved6 : 26;
};
@@ -114,7 +116,8 @@ typedef volatile struct {
} fifo_conf;
union {
struct {
uint32_t data;
uint8_t data;
uint8_t reserved[3];
};
uint32_t val;
} fifo_data;
@@ -137,7 +140,8 @@ typedef volatile struct {
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t reserved17: 15;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_raw;
@@ -160,7 +164,8 @@ typedef volatile struct {
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t reserved17: 15;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_clr;
@@ -183,7 +188,8 @@ typedef volatile struct {
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t reserved17: 15;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_ena;
@@ -206,7 +212,8 @@ typedef volatile struct {
uint32_t scl_main_st_to : 1;
uint32_t det_start : 1;
uint32_t slave_stretch : 1;
uint32_t reserved17: 15;
uint32_t general_call : 1;
uint32_t reserved18 : 14;
};
uint32_t val;
} int_status;
@@ -284,7 +291,11 @@ typedef volatile struct {
} clk_conf;
union {
struct {
uint32_t command0: 14;
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
uint32_t reserved14: 17;
uint32_t done: 1;
};
@@ -319,7 +330,9 @@ typedef volatile struct {
uint32_t stretch_protect_num : 10;
uint32_t slave_scl_stretch_en : 1;
uint32_t slave_scl_stretch_clr : 1;
uint32_t reserved12: 20;
uint32_t slave_byte_ack_ctl_en : 1;
uint32_t slave_byte_ack_level : 1;
uint32_t reserved14 : 18;
};
uint32_t val;
} scl_stretch_conf;
@@ -351,9 +364,9 @@ typedef volatile struct {
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t date; /**/
uint32_t date;
uint32_t reserved_fc;
uint32_t txfifo_start_addr; /**/
uint32_t txfifo_start_addr;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
@@ -385,12 +398,10 @@ typedef volatile struct {
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t fifo_start_addr; /**/
uint32_t rxfifo_start_addr;
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifdef __cplusplus
}
#endif

654
components/soc/esp32s3/include/soc/i2s_reg.h
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File diff suppressed because it is too large Load Diff

117
components/soc/esp32s3/include/soc/i2s_struct.h
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@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_I2S_STRUCT_H_
#define _SOC_I2S_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
@@ -72,21 +70,21 @@ typedef volatile struct {
uint32_t rx_slave_mod : 1; /*Set this bit to enable slave receiver mode*/
uint32_t reserved4 : 1; /* Reserved*/
uint32_t rx_mono : 1; /*Set this bit to enable receiver in mono mode*/
uint32_t reserved6: 1;
uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t reserved6 : 1; /*Reserve*/
uint32_t rx_big_endian : 1; /*I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t rx_update : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t rx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
uint32_t rx_pcm_conf : 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
uint32_t rx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t rx_stop_mode : 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
uint32_t rx_24_fill_en : 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/
uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/
uint32_t rx_ws_idle_pol : 1; /*0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. */
uint32_t rx_bit_order : 1; /*I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.*/
uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
uint32_t rx_pdm2pcm_en : 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
uint32_t rx_sinc_dsr_16_en: 1;
uint32_t rx_pdm_sinc_dsr_16_en : 1; /*Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64.*/
uint32_t reserved23 : 9; /*Reserve*/
};
uint32_t val;
@@ -100,31 +98,31 @@ typedef volatile struct {
uint32_t reserved4 : 1; /* Reserved*/
uint32_t tx_mono : 1; /*Set this bit to enable transmitter in mono mode */
uint32_t tx_chan_equal : 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t tx_big_endian : 1; /*I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t tx_update : 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t tx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
uint32_t tx_pcm_conf : 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
uint32_t tx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t reserved14: 1;
uint32_t reserved14 : 1; /* Reserved*/
uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
uint32_t tx_24_fill_en : 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/
uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/
uint32_t tx_ws_idle_pol : 1; /*0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. */
uint32_t tx_bit_order : 1; /*I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.*/
uint32_t tx_tdm_en : 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
uint32_t tx_pdm_en : 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
uint32_t reserved21 : 3; /*Reserved*/
uint32_t tx_chan_mod : 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t sig_loopback : 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t reserved28: 4; /*Reserved*/
uint32_t reserved28 : 4; /*Reserve*/
};
uint32_t val;
} tx_conf;
union {
struct {
uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
uint32_t rx_tdm_ws_width : 7; /* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
uint32_t rx_bck_div_num : 6; /*Bit clock configuration bits in receiver mode. */
uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t rx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
uint32_t rx_half_sample_bits : 6; /*I2S Rx half sample bits -1.*/
uint32_t rx_tdm_chan_bits : 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
uint32_t rx_msb_shift : 1; /*Set this bit to enable receiver in Phillips standard mode*/
@@ -134,13 +132,14 @@ typedef volatile struct {
} rx_conf1;
union {
struct {
uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
uint32_t tx_tdm_ws_width : 7; /* The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
uint32_t tx_bck_div_num : 6; /*Bit clock configuration bits in transmitter mode. */
uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t tx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
uint32_t tx_half_sample_bits : 6; /* I2S Tx half sample bits -1.*/
uint32_t tx_tdm_chan_bits : 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
uint32_t tx_msb_shift : 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t reserved30: 2; /*Reserved*/
uint32_t tx_bck_no_dly : 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
uint32_t reserved31 : 1; /* Reserved*/
};
uint32_t val;
} tx_conf1;
@@ -186,8 +185,34 @@ typedef volatile struct {
};
uint32_t val;
} tx_clkm_div_conf;
uint32_t reserved_40;
uint32_t reserved_44;
union {
struct {
uint32_t txhp_bypass: 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
uint32_t tx_sinc_osr2: 4; /*I2S TX PDM OSR2 value*/
uint32_t tx_prescale: 8; /*I2S TX PDM prescale for sigmadelta*/
uint32_t tx_hp_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_lp_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_sinc_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_sigmadelta_in_shift: 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 1:x1 2:x2 3: x4*/
uint32_t tx_sigmadelta_dither2: 1; /*I2S TX PDM sigmadelta dither2 value*/
uint32_t tx_sigmadelta_dither: 1; /*I2S TX PDM sigmadelta dither value*/
uint32_t tx_dac_2out_en: 1; /*I2S TX PDM dac mode enable*/
uint32_t tx_dac_mode_en: 1; /*I2S TX PDM dac 2channel enable*/
uint32_t pcm2pdm_conv_en: 1; /*I2S TX PDM Converter enable*/
uint32_t reserved26: 6; /*Reserved*/
};
uint32_t val;
} tx_pcm2pdm_conf;
union {
struct {
uint32_t tx_pdm_fp: 10; /*I2S TX PDM Fp*/
uint32_t tx_pdm_fs: 10; /*I2S TX PDM Fs*/
uint32_t tx_iir_hp_mult12_5: 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
uint32_t tx_iir_hp_mult12_0: 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
uint32_t reserved26: 6; /*Reserved*/
};
uint32_t val;
} tx_pcm2pdm_conf1;
uint32_t reserved_48;
uint32_t reserved_4c;
union {
@@ -231,7 +256,7 @@ typedef volatile struct {
uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/
uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
uint32_t reserved21: 11; /*Reserved*/
};
@@ -248,28 +273,30 @@ typedef volatile struct {
uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved14: 2;
uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2;
uint32_t reserved18: 2; /*Reserved*/
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2;
uint32_t reserved22: 2; /*Reserved*/
uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2;
uint32_t reserved26: 2; /*Reserved*/
uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2;
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} rx_timing;
union {
struct {
uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2: 14; /*Reserved*/
uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2;
uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2;
uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2;
uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2;
uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2: 2; /*Reserved*/
uint32_t tx_sd1_out_dm: 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6: 10; /*Reserved*/
uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2; /*Reserved*/
uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2; /*Reserved*/
uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2; /*Reserved*/
uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} tx_timing;
@@ -284,12 +311,12 @@ typedef volatile struct {
} lc_hung_conf;
union {
struct {
uint32_t rx_eof_num: 12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t rx_eof_num:12; /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
uint32_t reserved12:20; /*Reserved*/
};
uint32_t val;
} rx_eof_num;
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
} rxeof_num;
uint32_t conf_sigle_data; /*I2S signal data register*/
union {
struct {
uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
@@ -303,16 +330,16 @@ typedef volatile struct {
uint32_t reserved_7c;
union {
struct {
uint32_t date: 28; /*Version control register*/
uint32_t date: 28; /*I2S version control register*/
uint32_t reserved28: 4; /*Reserved*/
};
uint32_t val;
} date;
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2S_STRUCT_H_ */

213
components/soc/esp32s3/include/soc/interrupt_core0_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,14 +11,17 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
#define _SOC_INTERRUPT_CORE0_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
@@ -315,13 +318,13 @@ extern "C" {
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TWAI_INT_MAP_M ((INTERRUPT_CORE0_TWAI_INT_MAP_V) << (INTERRUPT_CORE0_TWAI_INT_MAP_S))
#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0
#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CAN_INT_MAP_S 0
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
@@ -547,47 +550,87 @@ extern "C" {
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
/* INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
/* INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/* INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/* INTERRUPT_CORE0_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/* INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH3_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/* INTERRUPT_CORE0_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/* INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH4_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S 0
#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
/* INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/* INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/* INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/* INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
/* INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S 0
#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F
@@ -595,7 +638,7 @@ extern "C" {
#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_RSA_INT_MAP_S 0
#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F
@@ -603,7 +646,7 @@ extern "C" {
#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_AES_INT_MAP_S 0
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F
@@ -611,7 +654,7 @@ extern "C" {
#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_SHA_INT_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
@@ -619,7 +662,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
@@ -627,7 +670,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
@@ -635,7 +678,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
@@ -643,7 +686,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F
@@ -651,7 +694,7 @@ extern "C" {
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -659,7 +702,7 @@ extern "C" {
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -667,7 +710,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -675,7 +718,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -683,7 +726,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
@@ -691,7 +734,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
/* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -699,7 +742,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
/* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -707,7 +750,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -715,7 +758,7 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
@@ -723,7 +766,15 @@ extern "C" {
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F
@@ -731,7 +782,7 @@ extern "C" {
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
/* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP 0x0000001F
@@ -739,7 +790,31 @@ extern "C" {
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S 0
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S))
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S 0
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
/* INTERRUPT_CORE0_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_M ((INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S))
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S 0
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
/* INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_M ((INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S))
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S 0
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
@@ -747,7 +822,7 @@ extern "C" {
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
@@ -755,7 +830,7 @@ extern "C" {
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF
@@ -763,7 +838,15 @@ extern "C" {
#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_2_S 0
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
#define INTERRUPT_CORE0_INTR_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_3 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_3_M ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S))
#define INTERRUPT_CORE0_INTR_STATUS_3_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_3_S 0
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define INTERRUPT_CORE0_CLK_EN (BIT(0))
@@ -772,7 +855,7 @@ extern "C" {
#define INTERRUPT_CORE0_CLK_EN_S 0
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
/*description: */
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
@@ -782,3 +865,7 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */

106
components/soc/esp32s3/include/soc/interrupt_core0_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_
#define _SOC_INTERRUPT_CORE0_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
@@ -484,39 +482,74 @@ typedef volatile struct {
} core0_apb_adc_int_map;
union {
struct {
uint32_t core0_dma_ch0_int_map: 5;
uint32_t core0_dma_in_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch0_int_map;
} core0_dma_in_ch0_int_map;
union {
struct {
uint32_t core0_dma_ch1_int_map: 5;
uint32_t core0_dma_in_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch1_int_map;
} core0_dma_in_ch1_int_map;
union {
struct {
uint32_t core0_dma_ch2_int_map: 5;
uint32_t core0_dma_in_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch2_int_map;
} core0_dma_in_ch2_int_map;
union {
struct {
uint32_t core0_dma_ch3_int_map: 5;
uint32_t core0_dma_in_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch3_int_map;
} core0_dma_in_ch3_int_map;
union {
struct {
uint32_t core0_dma_ch4_int_map: 5;
uint32_t core0_dma_in_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_ch4_int_map;
} core0_dma_in_ch4_int_map;
union {
struct {
uint32_t core0_dma_out_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch0_int_map;
union {
struct {
uint32_t core0_dma_out_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch1_int_map;
union {
struct {
uint32_t core0_dma_out_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch2_int_map;
union {
struct {
uint32_t core0_dma_out_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch3_int_map;
union {
struct {
uint32_t core0_dma_out_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_out_ch4_int_map;
union {
struct {
uint32_t core0_rsa_int_map: 5;
@@ -636,6 +669,13 @@ typedef volatile struct {
};
uint32_t val;
} core0_core_1_pif_pms_monitor_violate_size_intr_map;
union {
struct {
uint32_t core0_backup_pms_violate_intr_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_backup_pms_violate_intr_map;
union {
struct {
uint32_t core0_cache_core0_acs_int_map: 5;
@@ -650,9 +690,31 @@ typedef volatile struct {
};
uint32_t val;
} core0_cache_core1_acs_int_map;
union {
struct {
uint32_t core0_usb_device_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_usb_device_int_map;
union {
struct {
uint32_t core0_peri_backup_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_peri_backup_int_map;
union {
struct {
uint32_t core0_dma_extmem_reject_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core0_dma_extmem_reject_int_map;
uint32_t core0_intr_status_0; /**/
uint32_t core0_intr_status_1; /**/
uint32_t core0_intr_status_2; /**/
uint32_t core0_intr_status_3; /**/
union {
struct {
uint32_t core0_clk_en: 1;
@@ -660,16 +722,6 @@ typedef volatile struct {
};
uint32_t val;
} core0_clock_gate;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
@@ -1085,9 +1137,9 @@ typedef volatile struct {
uint32_t val;
} core0_interrupt_date;
} interrupt_core0_dev_t;
extern interrupt_core0_dev_t INTERRUPT_CORE0;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_INTERRUPT_CORE0_STRUCT_H_ */

213
components/soc/esp32s3/include/soc/interrupt_core1_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,14 +11,17 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_INTERRUPT_CORE1_REG_H_
#define _SOC_INTERRUPT_CORE1_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_INTERRUPT_CORE1_BASE DR_REG_INTERRUPT_BASE
#define INTERRUPT_CORE1_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x800)
/* INTERRUPT_CORE1_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
@@ -315,13 +318,13 @@ extern "C" {
#define INTERRUPT_CORE1_EFUSE_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_EFUSE_INT_MAP_S 0
#define INTERRUPT_CORE1_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894)
/* INTERRUPT_CORE1_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE1_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894)
/* INTERRUPT_CORE1_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_TWAI_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_TWAI_INT_MAP_M ((INTERRUPT_CORE1_TWAI_INT_MAP_V) << (INTERRUPT_CORE1_TWAI_INT_MAP_S))
#define INTERRUPT_CORE1_TWAI_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_TWAI_INT_MAP_S 0
#define INTERRUPT_CORE1_CAN_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_CAN_INT_MAP_M ((INTERRUPT_CORE1_CAN_INT_MAP_V)<<(INTERRUPT_CORE1_CAN_INT_MAP_S))
#define INTERRUPT_CORE1_CAN_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_CAN_INT_MAP_S 0
#define INTERRUPT_CORE1_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x898)
/* INTERRUPT_CORE1_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
@@ -547,47 +550,87 @@ extern "C" {
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908)
/* INTERRUPT_CORE1_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908)
/* INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH0_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C)
/* INTERRUPT_CORE1_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C)
/* INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH1_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910)
/* INTERRUPT_CORE1_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910)
/* INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH2_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914)
/* INTERRUPT_CORE1_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914)
/* INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH3_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918)
/* INTERRUPT_CORE1_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918)
/* INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH4_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S 0
#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C)
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C)
/* INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920)
/* INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924)
/* INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928)
/* INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C)
/* INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S 0
#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930)
/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000001F
@@ -595,7 +638,7 @@ extern "C" {
#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_RSA_INT_MAP_S 0
#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920)
#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934)
/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_AES_INT_MAP 0x0000001F
@@ -603,7 +646,7 @@ extern "C" {
#define INTERRUPT_CORE1_AES_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_AES_INT_MAP_S 0
#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924)
#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938)
/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000001F
@@ -611,7 +654,7 @@ extern "C" {
#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_SHA_INT_MAP_S 0
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928)
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C)
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
@@ -619,7 +662,7 @@ extern "C" {
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S 0
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C)
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940)
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
@@ -627,7 +670,7 @@ extern "C" {
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S 0
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930)
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944)
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
@@ -635,7 +678,7 @@ extern "C" {
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S 0
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934)
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948)
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
@@ -643,7 +686,7 @@ extern "C" {
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S 0
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938)
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C)
/* INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP 0x0000001F
@@ -651,7 +694,7 @@ extern "C" {
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S 0
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C)
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950)
/* INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -659,7 +702,7 @@ extern "C" {
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940)
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954)
/* INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -667,7 +710,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944)
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958)
/* INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -675,7 +718,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948)
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C)
/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -683,7 +726,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C)
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960)
/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
@@ -691,7 +734,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950)
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964)
/* INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -699,7 +742,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954)
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968)
/* INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -707,7 +750,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958)
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C)
/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
@@ -715,7 +758,7 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C)
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970)
/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
@@ -723,7 +766,15 @@ extern "C" {
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960)
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974)
/* INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S))
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S 0
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x978)
/* INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP 0x0000001F
@@ -731,7 +782,7 @@ extern "C" {
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S 0
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964)
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x97C)
/* INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP 0x0000001F
@@ -739,7 +790,31 @@ extern "C" {
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S 0
#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968)
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x980)
/* INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S))
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S 0
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x984)
/* INTERRUPT_CORE1_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_M ((INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S))
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S 0
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x988)
/* INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
/*description: */
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP 0x0000001F
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_M ((INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S))
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V 0x1F
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S 0
#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98C)
/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF
@@ -747,7 +822,7 @@ extern "C" {
#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF
#define INTERRUPT_CORE1_INTR_STATUS_0_S 0
#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C)
#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x990)
/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF
@@ -755,7 +830,7 @@ extern "C" {
#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF
#define INTERRUPT_CORE1_INTR_STATUS_1_S 0
#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970)
#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x994)
/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF
@@ -763,7 +838,15 @@ extern "C" {
#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF
#define INTERRUPT_CORE1_INTR_STATUS_2_S 0
#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974)
#define INTERRUPT_CORE1_INTR_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x998)
/* INTERRUPT_CORE1_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE1_INTR_STATUS_3 0xFFFFFFFF
#define INTERRUPT_CORE1_INTR_STATUS_3_M ((INTERRUPT_CORE1_INTR_STATUS_3_V)<<(INTERRUPT_CORE1_INTR_STATUS_3_S))
#define INTERRUPT_CORE1_INTR_STATUS_3_V 0xFFFFFFFF
#define INTERRUPT_CORE1_INTR_STATUS_3_S 0
#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x99c)
/* INTERRUPT_CORE1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define INTERRUPT_CORE1_CLK_EN (BIT(0))
@@ -772,7 +855,7 @@ extern "C" {
#define INTERRUPT_CORE1_CLK_EN_S 0
#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFFC)
/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
/*description: */
#define INTERRUPT_CORE1_INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_CORE1_INTERRUPT_DATE_M ((INTERRUPT_CORE1_INTERRUPT_DATE_V)<<(INTERRUPT_CORE1_INTERRUPT_DATE_S))
@@ -782,3 +865,7 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /*_SOC_INTERRUPT_CORE1_REG_H_ */

106
components/soc/esp32s3/include/soc/interrupt_core1_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,14 +11,12 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_
#define _SOC_INTERRUPT_CORE1_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
uint32_t reserved_0;
uint32_t reserved_4;
@@ -996,39 +994,74 @@ typedef volatile struct {
} core1_apb_adc_int_map;
union {
struct {
uint32_t core1_dma_ch0_int_map: 5;
uint32_t core1_dma_in_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch0_int_map;
} core1_dma_in_ch0_int_map;
union {
struct {
uint32_t core1_dma_ch1_int_map: 5;
uint32_t core1_dma_in_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch1_int_map;
} core1_dma_in_ch1_int_map;
union {
struct {
uint32_t core1_dma_ch2_int_map: 5;
uint32_t core1_dma_in_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch2_int_map;
} core1_dma_in_ch2_int_map;
union {
struct {
uint32_t core1_dma_ch3_int_map: 5;
uint32_t core1_dma_in_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch3_int_map;
} core1_dma_in_ch3_int_map;
union {
struct {
uint32_t core1_dma_ch4_int_map: 5;
uint32_t core1_dma_in_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_ch4_int_map;
} core1_dma_in_ch4_int_map;
union {
struct {
uint32_t core1_dma_out_ch0_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch0_int_map;
union {
struct {
uint32_t core1_dma_out_ch1_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch1_int_map;
union {
struct {
uint32_t core1_dma_out_ch2_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch2_int_map;
union {
struct {
uint32_t core1_dma_out_ch3_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch3_int_map;
union {
struct {
uint32_t core1_dma_out_ch4_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_out_ch4_int_map;
union {
struct {
uint32_t core1_rsa_int_map: 5;
@@ -1148,6 +1181,13 @@ typedef volatile struct {
};
uint32_t val;
} core1_core_1_pif_pms_monitor_violate_size_intr_map;
union {
struct {
uint32_t core1_backup_pms_violate_intr_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_backup_pms_violate_intr_map;
union {
struct {
uint32_t core1_cache_core0_acs_int_map: 5;
@@ -1162,9 +1202,31 @@ typedef volatile struct {
};
uint32_t val;
} core1_cache_core1_acs_int_map;
union {
struct {
uint32_t core1_usb_device_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_usb_device_int_map;
union {
struct {
uint32_t core1_peri_backup_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_peri_backup_int_map;
union {
struct {
uint32_t core1_dma_extmem_reject_int_map: 5;
uint32_t reserved5: 27;
};
uint32_t val;
} core1_dma_extmem_reject_int_map;
uint32_t core1_intr_status_0; /**/
uint32_t core1_intr_status_1; /**/
uint32_t core1_intr_status_2; /**/
uint32_t core1_intr_status_3; /**/
union {
struct {
uint32_t core1_clk_en: 1;
@@ -1172,16 +1234,6 @@ typedef volatile struct {
};
uint32_t val;
} core1_clock_gate;
uint32_t reserved_978;
uint32_t reserved_97c;
uint32_t reserved_980;
uint32_t reserved_984;
uint32_t reserved_988;
uint32_t reserved_98c;
uint32_t reserved_990;
uint32_t reserved_994;
uint32_t reserved_998;
uint32_t reserved_99c;
uint32_t reserved_9a0;
uint32_t reserved_9a4;
uint32_t reserved_9a8;
@@ -1597,9 +1649,9 @@ typedef volatile struct {
uint32_t val;
} core1_interrupt_date;
} interrupt_core1_dev_t;
extern interrupt_core1_dev_t INTERRUPT_CORE1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_INTERRUPT_CORE1_STRUCT_H_ */

360
components/soc/esp32s3/include/soc/lcd_cam_reg.h
View File

File diff suppressed because it is too large Load Diff

1071
components/soc/esp32s3/include/soc/mcpwm_reg.h
View File

File diff suppressed because it is too large Load Diff

101
components/soc/esp32s3/include/soc/mcpwm_struct.h
View File

@@ -13,13 +13,13 @@
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct mcpwm_dev_s {
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t prescale : 8;
@@ -32,15 +32,15 @@ typedef volatile struct mcpwm_dev_s {
struct {
uint32_t prescale : 8;
uint32_t period : 16;
uint32_t upmethod: 2; /*0: immediate 1: eqz 2: sync 3: eqz | sync*/
uint32_t upmethod : 2; /*0: immediate, 1: eqz, 2: sync, 3: eqz | sync*/
uint32_t reserved26 : 6;
};
uint32_t val;
} period;
union {
struct {
uint32_t start: 3; /*0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop @ next eqz 4: start and stop @ next eqp*/
uint32_t mode: 2; /*0: freeze 1: inc 2: dec 3: up-down*/
uint32_t start : 3; /*0: stop @ eqz, 1: stop @ eqp, 2: free run, 3: start and stop @ next eqz, 4: start and stop @ next eqp,*/
uint32_t mod : 2; /* 0: freeze, 1: inc, 2: dec, 3: up-down*/
uint32_t reserved5 : 27;
};
uint32_t val;
@@ -50,8 +50,7 @@ typedef volatile struct mcpwm_dev_s {
uint32_t in_en : 1;
uint32_t sync_sw : 1; /*write the negate value will trigger a sw sync*/
uint32_t out_sel : 2;
uint32_t timer_phase: 16;
uint32_t phase_direct : 1;
uint32_t phase : 17;
uint32_t reserved21 : 11;
};
uint32_t val;
@@ -79,9 +78,9 @@ typedef volatile struct mcpwm_dev_s {
} timer_synci_cfg;
union {
struct {
uint32_t operator0_sel: 2; /*0: timer0 1: timer1 2: timer2*/
uint32_t operator1_sel: 2; /*0: timer0 1: timer1 2: timer2*/
uint32_t operator2_sel: 2; /*0: timer0 1: timer1 2: timer2*/
uint32_t operator0_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/
uint32_t operator1_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/
uint32_t operator2_sel : 2; /*0: timer0, 1: timer1, 2: timer2*/
uint32_t reserved6 : 26;
};
uint32_t val;
@@ -89,8 +88,8 @@ typedef volatile struct mcpwm_dev_s {
struct {
union {
struct {
uint32_t a_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t b_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t a_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t b_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t a_shdw_full : 1;
uint32_t b_shdw_full : 1;
uint32_t reserved10 : 22;
@@ -106,22 +105,22 @@ typedef volatile struct mcpwm_dev_s {
} cmpr_value[2];
union {
struct {
uint32_t upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/
uint32_t t0_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/
uint32_t t1_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/
uint32_t upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync. bit3: freeze*/
uint32_t t0_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/
uint32_t t1_sel : 3; /*take effect immediately, 0: extra0, 1: extra1, 2: extra2, 3: sync_taken, 4: none*/
uint32_t reserved10 : 22;
};
uint32_t val;
} gen_cfg0;
union {
struct {
uint32_t cntu_force_upmethod: 6; /*0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: sync bit5: freeze*/
uint32_t a_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t b_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t a_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/
uint32_t a_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t b_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/
uint32_t b_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
uint32_t cntu_force_upmethod : 6; /*0: immediate, bit0: tez, bit1: tep, bit2: tea, bit3: teb, bit4: sync, bit5: freeze*/
uint32_t a_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t b_cntuforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t a_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/
uint32_t a_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t b_nciforce : 1; /*non-continuous immediate sw force, a toggle will trigger a force event*/
uint32_t b_nciforce_mode : 2; /*0: disabled, 1: low, 2: high, 3: disabled*/
uint32_t reserved16 : 16;
};
uint32_t val;
@@ -139,16 +138,16 @@ typedef volatile struct mcpwm_dev_s {
uint32_t dtea : 2;
uint32_t dteb : 2;
uint32_t dt0 : 2;
uint32_t dt1: 2; /*0: no change 1: low 2: high 3: toggle*/
uint32_t dt1 : 2; /*0: no change, 1: low, 2: high, 3: toggle*/
uint32_t reserved24 : 8;
};
uint32_t val;
} generator[2];
union {
struct {
uint32_t fed_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t red_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t deb_mode: 1; /*immediate dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
uint32_t fed_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t red_upmethod : 4; /*0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze*/
uint32_t deb_mode : 1; /*immediate, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode*/
uint32_t a_outswap : 1;
uint32_t b_outswap : 1;
uint32_t red_insel : 1;
@@ -190,22 +189,22 @@ typedef volatile struct mcpwm_dev_s {
} carrier_cfg;
union {
struct {
uint32_t sw_cbc: 1; /*0: disable 1: enable*/
uint32_t f2_cbc: 1; /*0: disable 1: enable*/
uint32_t f1_cbc: 1; /*0: disable 1: enable*/
uint32_t f0_cbc: 1; /*0: disable 1: enable*/
uint32_t sw_ost: 1; /*0: disable 1: enable*/
uint32_t f2_ost: 1; /*0: disable 1: enable*/
uint32_t f1_ost: 1; /*0: disable 1: enable*/
uint32_t f0_ost: 1; /*0: disable 1: enable*/
uint32_t a_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t sw_cbc : 1; /*0: disable, 1: enable*/
uint32_t f2_cbc : 1; /*0: disable, 1: enable*/
uint32_t f1_cbc : 1; /*0: disable, 1: enable*/
uint32_t f0_cbc : 1; /*0: disable, 1: enable*/
uint32_t sw_ost : 1; /*0: disable, 1: enable*/
uint32_t f2_ost : 1; /*0: disable, 1: enable*/
uint32_t f1_ost : 1; /*0: disable, 1: enable*/
uint32_t f0_ost : 1; /*0: disable, 1: enable*/
uint32_t a_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t a_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t a_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t a_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_cbc_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_cbc_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_ost_d : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t b_ost_u : 2; /*0: do nothing, 1: force lo, 2: force hi, 3: toggle*/
uint32_t reserved24 : 8;
};
uint32_t val;
@@ -213,7 +212,7 @@ typedef volatile struct mcpwm_dev_s {
union {
struct {
uint32_t clr_ost : 1; /*a toggle will clear oneshot tripping*/
uint32_t cbcpulse: 2; /*bit0: tez bit1: tep*/
uint32_t cbcpulse : 2; /*bit0: tez, bit1: tep*/
uint32_t force_cbc : 1; /*a toggle trigger a cycle-by-cycle tripping*/
uint32_t force_ost : 1; /*a toggle trigger a oneshot tripping*/
uint32_t reserved5 : 27;
@@ -254,11 +253,11 @@ typedef volatile struct mcpwm_dev_s {
};
uint32_t val;
} cap_timer_cfg;
uint32_t cap_timer_phase; /**/
uint32_t cap_timer_phase;
union {
struct {
uint32_t en : 1;
uint32_t mode: 2; /*bit0: negedge cap en bit1: posedge cap en*/
uint32_t mode : 2; /*bit0: negedge cap en, bit1: posedge cap en*/
uint32_t prescale : 8;
uint32_t in_invert : 1;
uint32_t sw : 1; /*Write 1 will trigger a sw capture*/
@@ -266,12 +265,12 @@ typedef volatile struct mcpwm_dev_s {
};
uint32_t val;
} cap_cfg_ch[3];
uint32_t cap_val_ch[3]; /**/
uint32_t cap_val_ch[3];
union {
struct {
uint32_t cap0_edge : 1;
uint32_t cap1_edge : 1;
uint32_t cap2_edge: 1; /*cap trigger's edge 0: posedge 1: negedge*/
uint32_t cap2_edge : 1; /*cap trigger's edge, 0: posedge, 1: negedge*/
uint32_t reserved3 : 29;
};
uint32_t val;
@@ -279,7 +278,7 @@ typedef volatile struct mcpwm_dev_s {
union {
struct {
uint32_t global_up_en : 1;
uint32_t global_force_up: 1; /*a toggle will trigger a force update all timers and operators will update their active regs*/
uint32_t global_force_up : 1; /*a toggle will trigger a force update, all timers and operators will update their active regs*/
uint32_t op0_up_en : 1;
uint32_t op0_force_up : 1; /*a toggle will trigger a force update*/
uint32_t op1_up_en : 1;
@@ -436,7 +435,7 @@ typedef volatile struct mcpwm_dev_s {
} int_clr;
union {
struct {
uint32_t clk_en: 1;
uint32_t en : 1;
uint32_t reserved1 : 31;
};
uint32_t val;
@@ -449,10 +448,8 @@ typedef volatile struct mcpwm_dev_s {
uint32_t val;
} version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1;
#ifdef __cplusplus
}
#endif

26
components/soc/esp32s3/include/soc/pcnt_caps.h Normal file
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@@ -0,0 +1,26 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_PCNT_PORT_NUM (1)
#define SOC_PCNT_UNIT_NUM (4)
#ifdef __cplusplus
}
#endif

324
components/soc/esp32s3/include/soc/pcnt_reg.h
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File diff suppressed because it is too large Load Diff

6
components/soc/esp32s3/include/soc/pcnt_struct.h
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@@ -105,7 +105,7 @@ typedef volatile struct {
} int_clr;
union {
struct {
uint32_t cnt_mode: 2;
uint32_t zero_mode : 2;
uint32_t thres1_lat : 1;
uint32_t thres0_lat : 1;
uint32_t l_lim_lat : 1;
@@ -169,11 +169,9 @@ typedef volatile struct {
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
uint32_t date;
} pcnt_dev_t;
extern pcnt_dev_t PCNT;
#ifdef __cplusplus
}
#endif

198
components/soc/esp32s3/include/soc/peri_backup_reg.h Normal file
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@@ -0,0 +1,198 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_PERI_BACKUP_REG_H_
#define _SOC_PERI_BACKUP_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define PERI_BACKUP_CONFIG_REG (DR_REG_PERI_BACKUP_BASE + 0x0)
/* PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_ENA (BIT(31))
#define PERI_BACKUP_ENA_M (BIT(31))
#define PERI_BACKUP_ENA_V 0x1
#define PERI_BACKUP_ENA_S 31
/* PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_TO_MEM (BIT(30))
#define PERI_BACKUP_TO_MEM_M (BIT(30))
#define PERI_BACKUP_TO_MEM_V 0x1
#define PERI_BACKUP_TO_MEM_S 30
/* PERI_BACKUP_START : WT ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_START (BIT(29))
#define PERI_BACKUP_START_M (BIT(29))
#define PERI_BACKUP_START_V 0x1
#define PERI_BACKUP_START_S 29
/* PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
/*description: .*/
#define PERI_BACKUP_SIZE 0x000003FF
#define PERI_BACKUP_SIZE_M ((PERI_BACKUP_SIZE_V)<<(PERI_BACKUP_SIZE_S))
#define PERI_BACKUP_SIZE_V 0x3FF
#define PERI_BACKUP_SIZE_S 19
/* PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
/*description: .*/
#define PERI_BACKUP_TOUT_THRES 0x000003FF
#define PERI_BACKUP_TOUT_THRES_M ((PERI_BACKUP_TOUT_THRES_V)<<(PERI_BACKUP_TOUT_THRES_S))
#define PERI_BACKUP_TOUT_THRES_V 0x3FF
#define PERI_BACKUP_TOUT_THRES_S 9
/* PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
/*description: .*/
#define PERI_BACKUP_BURST_LIMIT 0x0000001F
#define PERI_BACKUP_BURST_LIMIT_M ((PERI_BACKUP_BURST_LIMIT_V)<<(PERI_BACKUP_BURST_LIMIT_S))
#define PERI_BACKUP_BURST_LIMIT_V 0x1F
#define PERI_BACKUP_BURST_LIMIT_S 4
/* PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: .*/
#define PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
#define PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
#define PERI_BACKUP_ADDR_MAP_MODE_V 0x1
#define PERI_BACKUP_ADDR_MAP_MODE_S 3
/* PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
/*description: .*/
#define PERI_BACKUP_FLOW_ERR 0x00000007
#define PERI_BACKUP_FLOW_ERR_M ((PERI_BACKUP_FLOW_ERR_V)<<(PERI_BACKUP_FLOW_ERR_S))
#define PERI_BACKUP_FLOW_ERR_V 0x7
#define PERI_BACKUP_FLOW_ERR_S 0
#define PERI_BACKUP_APB_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x4)
/* PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define PERI_BACKUP_APB_START_ADDR_M ((PERI_BACKUP_APB_START_ADDR_V)<<(PERI_BACKUP_APB_START_ADDR_S))
#define PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define PERI_BACKUP_APB_START_ADDR_S 0
#define PERI_BACKUP_MEM_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x8)
/* PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define PERI_BACKUP_MEM_START_ADDR_M ((PERI_BACKUP_MEM_START_ADDR_V)<<(PERI_BACKUP_MEM_START_ADDR_S))
#define PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define PERI_BACKUP_MEM_START_ADDR_S 0
#define PERI_BACKUP_REG_MAP0_REG (DR_REG_PERI_BACKUP_BASE + 0xC)
/* PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP0 0xFFFFFFFF
#define PERI_BACKUP_MAP0_M ((PERI_BACKUP_MAP0_V)<<(PERI_BACKUP_MAP0_S))
#define PERI_BACKUP_MAP0_V 0xFFFFFFFF
#define PERI_BACKUP_MAP0_S 0
#define PERI_BACKUP_REG_MAP1_REG (DR_REG_PERI_BACKUP_BASE + 0x10)
/* PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP1 0xFFFFFFFF
#define PERI_BACKUP_MAP1_M ((PERI_BACKUP_MAP1_V)<<(PERI_BACKUP_MAP1_S))
#define PERI_BACKUP_MAP1_V 0xFFFFFFFF
#define PERI_BACKUP_MAP1_S 0
#define PERI_BACKUP_REG_MAP2_REG (DR_REG_PERI_BACKUP_BASE + 0x14)
/* PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP2 0xFFFFFFFF
#define PERI_BACKUP_MAP2_M ((PERI_BACKUP_MAP2_V)<<(PERI_BACKUP_MAP2_S))
#define PERI_BACKUP_MAP2_V 0xFFFFFFFF
#define PERI_BACKUP_MAP2_S 0
#define PERI_BACKUP_REG_MAP3_REG (DR_REG_PERI_BACKUP_BASE + 0x18)
/* PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define PERI_BACKUP_MAP3 0xFFFFFFFF
#define PERI_BACKUP_MAP3_M ((PERI_BACKUP_MAP3_V)<<(PERI_BACKUP_MAP3_S))
#define PERI_BACKUP_MAP3_V 0xFFFFFFFF
#define PERI_BACKUP_MAP3_S 0
#define PERI_BACKUP_INT_RAW_REG (DR_REG_PERI_BACKUP_BASE + 0x1C)
/* PERI_BACKUP_ERR_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_RAW (BIT(1))
#define PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
#define PERI_BACKUP_ERR_INT_RAW_V 0x1
#define PERI_BACKUP_ERR_INT_RAW_S 1
/* PERI_BACKUP_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_RAW (BIT(0))
#define PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
#define PERI_BACKUP_DONE_INT_RAW_V 0x1
#define PERI_BACKUP_DONE_INT_RAW_S 0
#define PERI_BACKUP_INT_ST_REG (DR_REG_PERI_BACKUP_BASE + 0x20)
/* PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_ST (BIT(1))
#define PERI_BACKUP_ERR_INT_ST_M (BIT(1))
#define PERI_BACKUP_ERR_INT_ST_V 0x1
#define PERI_BACKUP_ERR_INT_ST_S 1
/* PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_ST (BIT(0))
#define PERI_BACKUP_DONE_INT_ST_M (BIT(0))
#define PERI_BACKUP_DONE_INT_ST_V 0x1
#define PERI_BACKUP_DONE_INT_ST_S 0
#define PERI_BACKUP_INT_ENA_REG (DR_REG_PERI_BACKUP_BASE + 0x24)
/* PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_ENA (BIT(1))
#define PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
#define PERI_BACKUP_ERR_INT_ENA_V 0x1
#define PERI_BACKUP_ERR_INT_ENA_S 1
/* PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_ENA (BIT(0))
#define PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
#define PERI_BACKUP_DONE_INT_ENA_V 0x1
#define PERI_BACKUP_DONE_INT_ENA_S 0
#define PERI_BACKUP_INT_CLR_REG (DR_REG_PERI_BACKUP_BASE + 0x28)
/* PERI_BACKUP_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_ERR_INT_CLR (BIT(1))
#define PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
#define PERI_BACKUP_ERR_INT_CLR_V 0x1
#define PERI_BACKUP_ERR_INT_CLR_S 1
/* PERI_BACKUP_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define PERI_BACKUP_DONE_INT_CLR (BIT(0))
#define PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
#define PERI_BACKUP_DONE_INT_CLR_V 0x1
#define PERI_BACKUP_DONE_INT_CLR_S 0
#define PERI_BACKUP_DATE_REG (DR_REG_PERI_BACKUP_BASE + 0xFC)
/* PERI_BACKUP_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating.*/
#define PERI_BACKUP_CLK_EN (BIT(31))
#define PERI_BACKUP_CLK_EN_M (BIT(31))
#define PERI_BACKUP_CLK_EN_V 0x1
#define PERI_BACKUP_CLK_EN_S 31
/* PERI_BACKUP_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
/*description: .*/
#define PERI_BACKUP_DATE 0x0FFFFFFF
#define PERI_BACKUP_DATE_M ((PERI_BACKUP_DATE_V)<<(PERI_BACKUP_DATE_S))
#define PERI_BACKUP_DATE_V 0xFFFFFFF
#define PERI_BACKUP_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_PERI_BACKUP_REG_H_ */

11
components/soc/esp32s3/include/soc/periph_defs.h
View File

@@ -33,6 +33,8 @@ typedef enum {
PERIPH_TIMG1_MODULE,
PERIPH_PWM0_MODULE,
PERIPH_PWM1_MODULE,
PERIPH_PWM2_MODULE,
PERIPH_PWM3_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_UHCI1_MODULE,
PERIPH_RMT_MODULE,
@@ -130,6 +132,11 @@ typedef enum {
ETS_DMA_CH2_INTR_SOURCE, /**< interrupt of general DMA channel 2, LEVEL*/
ETS_DMA_CH3_INTR_SOURCE, /**< interrupt of general DMA channel 3, LEVEL*/
ETS_DMA_CH4_INTR_SOURCE, /**< interrupt of general DMA channel 4, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH2_INTR_SOURCE,
ETS_DMA_OUT_CH3_INTR_SOURCE,
ETS_DMA_OUT_CH4_INTR_SOURCE,
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
@@ -147,8 +154,12 @@ typedef enum {
ETS_CORE1_DRAM0_PMS_INTR_SOURCE,
ETS_CORE1_PIF_PMS_INTR_SOURCE,
ETS_CORE1_PIF_PMS_SIZE_INTR_SOURCE,
ETS_BACKUP_PMS_VIOLATE_INTR_SOURCE,
ETS_CACHE_CORE0_ACS_INTR_SOURCE,
ETS_CACHE_CORE1_ACS_INTR_SOURCE,
ETS_USB_DEVICE_INTR_SOURCE,
ETS_PREI_BACKUP_INTR_SOURCE,
ETS_DMA_EXTMEM_REJECT_SOURCE,
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
} periph_interrput_t;

30
components/soc/esp32s3/include/soc/rmt_caps.h Normal file
View File

@@ -0,0 +1,30 @@
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
#ifdef __cplusplus
}
#endif

878
components/soc/esp32s3/include/soc/rmt_reg.h
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File diff suppressed because it is too large Load Diff

60
components/soc/esp32s3/include/soc/rmt_struct.h
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@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RMT_STRUCT_H_
#define _SOC_RMT_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
uint32_t data_ch[8];
@@ -25,7 +26,7 @@ typedef volatile struct {
struct {
uint32_t tx_start : 1;
uint32_t mem_rd_rst : 1;
uint32_t apb_mem_rst : 1;
uint32_t mem_rst : 1;
uint32_t tx_conti_mode : 1;
uint32_t mem_tx_wrap_en : 1;
uint32_t idle_out_lv : 1;
@@ -59,7 +60,7 @@ typedef volatile struct {
struct {
uint32_t rx_en : 1;
uint32_t mem_wr_rst : 1;
uint32_t apb_mem_rst : 1;
uint32_t mem_rst : 1;
uint32_t mem_owner : 1;
uint32_t rx_filter_en : 1;
uint32_t rx_filter_thres : 8;
@@ -75,11 +76,11 @@ typedef volatile struct {
struct {
uint32_t mem_raddr_ex : 10;
uint32_t reserved10 : 1;
uint32_t apb_mem_waddr : 10;
uint32_t mem_waddr : 10;
uint32_t reserved21 : 1;
uint32_t state : 3;
uint32_t mem_empty : 1;
uint32_t apb_mem_wr_err : 1;
uint32_t mem_wr_err : 1;
uint32_t reserved27 : 5;
};
uint32_t val;
@@ -88,13 +89,13 @@ typedef volatile struct {
struct {
uint32_t mem_waddr_ex : 10;
uint32_t reserved10 : 1;
uint32_t apb_mem_raddr : 10;
uint32_t mem_raddr : 10;
uint32_t reserved21 : 1;
uint32_t state : 3;
uint32_t mem_owner_err : 1;
uint32_t mem_full : 1;
uint32_t apb_mem_rd_err : 1;
uint32_t reserved27 : 4;
uint32_t mem_rd_err : 1;
uint32_t reserved28 : 4;
};
uint32_t val;
} rx_status[4];
@@ -128,7 +129,9 @@ typedef volatile struct {
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_raw;
@@ -162,7 +165,9 @@ typedef volatile struct {
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_st;
@@ -196,7 +201,9 @@ typedef volatile struct {
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_ena;
@@ -230,7 +237,9 @@ typedef volatile struct {
uint32_t ch5_rx_thr_event : 1;
uint32_t ch6_rx_thr_event : 1;
uint32_t ch7_rx_thr_event : 1;
uint32_t reserved28 : 4;
uint32_t ch3_dma_access_fail : 1;
uint32_t ch7_dma_access_fail : 1;
uint32_t reserved30 : 2;
};
uint32_t val;
} int_clr;
@@ -254,7 +263,8 @@ typedef volatile struct {
uint32_t tx_loop_num : 10;
uint32_t tx_loop_cnt_en : 1;
uint32_t loop_count_reset : 1;
uint32_t reserved21 : 11;
uint32_t loop_stop_en : 1;
uint32_t reserved22 : 10;
};
uint32_t val;
} tx_lim[4];
@@ -294,14 +304,14 @@ typedef volatile struct {
} tx_sim;
union {
struct {
uint32_t ref_cnt_rst_ch0 : 1;
uint32_t ref_cnt_rst_ch1 : 1;
uint32_t ref_cnt_rst_ch2 : 1;
uint32_t ref_cnt_rst_ch3 : 1;
uint32_t ref_cnt_rst_ch4 : 1;
uint32_t ref_cnt_rst_ch5 : 1;
uint32_t ref_cnt_rst_ch6 : 1;
uint32_t ref_cnt_rst_ch7 : 1;
uint32_t ch0 : 1;
uint32_t ch1 : 1;
uint32_t ch2 : 1;
uint32_t ch3 : 1;
uint32_t ch4 : 1;
uint32_t ch5 : 1;
uint32_t ch6 : 1;
uint32_t ch7 : 1;
uint32_t reserved8 : 24;
};
uint32_t val;
@@ -342,3 +352,7 @@ extern rmt_mem_t RMTMEM;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RMT_STRUCT_H_ */

1401
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
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File diff suppressed because it is too large Load Diff

105
components/soc/esp32s3/include/soc/rtc_cntl_struct.h
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@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,19 +11,20 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RTC_CNTL_STRUCT_H_
#define _SOC_RTC_CNTL_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
uint32_t sw_appcpu_rst : 1; /*APP CPU SW reset*/
uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/
uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/
@@ -48,7 +49,7 @@ typedef volatile struct {
};
uint32_t val;
} options0;
uint32_t slp_timer0; /**/
uint32_t slp_timer0;
union {
struct {
uint32_t slp_val_hi : 16; /*RTC sleep timer high 16 bits*/
@@ -68,7 +69,7 @@ typedef volatile struct {
};
uint32_t val;
} time_update;
uint32_t time_low0; /*RTC timer low 32 bits*/
uint32_t time_low0;
union {
struct {
uint32_t rtc_timer_value0_high : 16; /*RTC timer high 16 bits*/
@@ -300,10 +301,10 @@ typedef volatile struct {
};
uint32_t val;
} int_clr;
uint32_t store[4]; /**/
uint32_t store[4];
union {
struct {
uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/
uint32_t xtal32k_en : 1; /*xtal 32k watch dog enable*/
uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/
uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/
uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/
@@ -329,8 +330,8 @@ typedef volatile struct {
struct {
uint32_t reserved0 : 29;
uint32_t gpio_wakeup_filter : 1; /*enable filter for gpio wakeup event*/
uint32_t wakeup0_lv: 1; /*0: external wakeup at low level*/
uint32_t wakeup1_lv: 1;
uint32_t ext_wakeup0_lv : 1; /*0: external wakeup at low level*/
uint32_t ext_wakeup1_lv : 1;
};
uint32_t val;
} ext_wakeup_conf;
@@ -445,24 +446,24 @@ typedef volatile struct {
} rtc;
union {
struct {
uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/
uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/
uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/
uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/
uint32_t rtc_fastmem_force_noiso : 1; /*Fast RTC memory force no ISO*/
uint32_t rtc_fastmem_force_iso : 1; /*Fast RTC memory force ISO*/
uint32_t rtc_slowmem_force_noiso : 1; /*RTC memory force no ISO*/
uint32_t rtc_slowmem_force_iso : 1; /*RTC memory force ISO*/
uint32_t rtc_force_iso : 1; /*rtc_peri force ISO*/
uint32_t rtc_force_noiso : 1; /*rtc_peri force no ISO*/
uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU*/
uint32_t rtc_fastmem_folw_cpu : 1; /*1: Fast RTC memory PD following CPU*/
uint32_t fastmem_force_lpd : 1; /*Fast RTC memory force PD*/
uint32_t fastmem_force_lpu : 1; /*Fast RTC memory force no PD*/
uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/
uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/
uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/
uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/
uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/
uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/
uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/
uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/
uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/
uint32_t rtc_slowmem_folw_cpu : 1; /*1: RTC memory PD following CPU*/
uint32_t rtc_slowmem_force_lpd : 1; /*RTC memory force PD*/
uint32_t rtc_slowmem_force_lpu : 1; /*RTC memory force no PD*/
uint32_t rtc_fastmem_force_pd : 1; /*Fast RTC memory force power down*/
uint32_t rtc_fastmem_force_pu : 1; /*Fast RTC memory force power up*/
uint32_t rtc_fastmem_pd_en : 1; /*enable power down fast RTC memory in sleep*/
uint32_t rtc_slowmem_force_pd : 1; /*RTC memory force power down*/
uint32_t rtc_slowmem_force_pu : 1; /*RTC memory force power up*/
uint32_t rtc_slowmem_pd_en : 1; /*enable power down RTC memory in sleep*/
uint32_t rtc_force_pd : 1; /*rtc_peri force power down*/
uint32_t rtc_force_pu : 1; /*rtc_peri force power up*/
uint32_t rtc_pd_en : 1; /*enable power down rtc_peri in sleep */
@@ -470,7 +471,7 @@ typedef volatile struct {
uint32_t reserved22 : 10;
};
uint32_t val;
} rtc_pwc;
} pwc;
union {
struct {
uint32_t reserved0 : 3;
@@ -555,10 +556,10 @@ typedef volatile struct {
};
uint32_t val;
} wdt_config0;
uint32_t wdt_config1; /**/
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
uint32_t wdt_config1;
uint32_t wdt_config2;
uint32_t wdt_config3;
uint32_t wdt_config4;
union {
struct {
uint32_t reserved0 : 31;
@@ -566,7 +567,7 @@ typedef volatile struct {
};
uint32_t val;
} wdt_feed;
uint32_t wdt_wprotect; /**/
uint32_t wdt_wprotect;
union {
struct {
uint32_t swd_reset_flag : 1; /*swd reset flag*/
@@ -581,7 +582,7 @@ typedef volatile struct {
};
uint32_t val;
} swd_conf;
uint32_t swd_wprotect; /**/
uint32_t swd_wprotect;
union {
struct {
uint32_t reserved0 : 20;
@@ -590,10 +591,10 @@ typedef volatile struct {
};
uint32_t val;
} sw_cpu_stall;
uint32_t store4; /**/
uint32_t store5; /**/
uint32_t store6; /**/
uint32_t store7; /**/
uint32_t store4;
uint32_t store5;
uint32_t store6;
uint32_t store7;
union {
struct {
uint32_t xpd_rom0 : 1; /*rom0 power down*/
@@ -628,7 +629,7 @@ typedef volatile struct {
};
uint32_t val;
} low_power_st;
uint32_t diag0; /**/
uint32_t diag0;
union {
struct {
uint32_t touch_pad0_hold : 1;
@@ -657,18 +658,18 @@ typedef volatile struct {
};
uint32_t val;
} pad_hold;
uint32_t dig_pad_hold; /**/
uint32_t dig_pad_hold;
union {
struct {
uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/
uint32_t status_clr: 1; /*clear ext wakeup1 status*/
uint32_t ext_wakeup1_sel : 22; /*Bitmap to select RTC pads for ext wakeup1*/
uint32_t ext_wakeup1_status_clr : 1; /*clear ext wakeup1 status*/
uint32_t reserved23 : 9;
};
uint32_t val;
} ext_wakeup1;
union {
struct {
uint32_t status: 22; /*ext wakeup1 status*/
uint32_t ext_wakeup1_status : 22; /*ext wakeup1 status*/
uint32_t reserved22 : 10;
};
uint32_t val;
@@ -689,7 +690,7 @@ typedef volatile struct {
};
uint32_t val;
} brown_out;
uint32_t time_low1; /*RTC timer low 32 bits*/
uint32_t time_low1;
union {
struct {
uint32_t rtc_timer_value1_high : 16; /*RTC timer high 16 bits*/
@@ -697,7 +698,7 @@ typedef volatile struct {
};
uint32_t val;
} time_high1;
uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/
uint32_t xtal32k_clk_factor;
union {
struct {
uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/
@@ -794,7 +795,7 @@ typedef volatile struct {
uint32_t touch_slp_th : 22; /*the threshold for sleep touch pad*/
uint32_t reserved22 : 4;
uint32_t touch_slp_approach_en : 1; /*sleep pad approach function enable*/
uint32_t touch_slp_pad: 5;
uint32_t touch_slp_pad : 5; /* */
};
uint32_t val;
} touch_slp_thres;
@@ -809,14 +810,14 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0 : 7;
uint32_t touch_bypass_neg_thres: 1;
uint32_t touch_bypass_neg_noise_thres : 1;
uint32_t touch_bypass_noise_thres : 1;
uint32_t touch_smooth_lvl : 2;
uint32_t touch_jitter_step : 4; /*touch jitter step*/
uint32_t config1: 4;
uint32_t config2: 2;
uint32_t touch_neg_noise_limit : 4; /*negative threshold counter limit*/
uint32_t touch_neg_noise_thres : 2;
uint32_t touch_noise_thres : 2;
uint32_t config3: 2;
uint32_t touch_hysteresis : 2;
uint32_t touch_debounce : 3; /*debounce counter*/
uint32_t touch_filter_mode : 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
uint32_t touch_filter_en : 1; /*touch filter enable*/
@@ -959,9 +960,11 @@ typedef volatile struct {
uint32_t val;
} date;
} rtc_cntl_dev_t;
extern rtc_cntl_dev_t RTCCNTL;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_CNTL_STRUCT_H_ */

272
components/soc/esp32s3/include/soc/rtc_i2c_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,670 +11,676 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RTC_I2C_REG_H_
#define _SOC_RTC_I2C_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0)
/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
/*description: time period that scl = 0*/
/*description: time period that scl = 0.*/
#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_LOW_PERIOD_S 0
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4)
/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: rtc i2c reg clk gating*/
/*description: rtc i2c reg clk gating.*/
#define RTC_I2C_CLK_EN (BIT(31))
#define RTC_I2C_CLK_EN_M (BIT(31))
#define RTC_I2C_CLK_EN_V 0x1
#define RTC_I2C_CLK_EN_S 31
/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: rtc i2c sw reset*/
/*description: rtc i2c sw reset.*/
#define RTC_I2C_RESET (BIT(30))
#define RTC_I2C_RESET_M (BIT(30))
#define RTC_I2C_RESET_V 0x1
#define RTC_I2C_RESET_S 30
/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29))
#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29))
#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1
#define RTC_I2C_CTRL_CLK_GATE_EN_S 29
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: receive lsb first*/
/*description: receive lsb first.*/
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
#define RTC_I2C_RX_LSB_FIRST_M (BIT(5))
#define RTC_I2C_RX_LSB_FIRST_V 0x1
#define RTC_I2C_RX_LSB_FIRST_S 5
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: transit lsb first*/
/*description: transit lsb first.*/
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
#define RTC_I2C_TX_LSB_FIRST_M (BIT(4))
#define RTC_I2C_TX_LSB_FIRST_V 0x1
#define RTC_I2C_TX_LSB_FIRST_S 4
/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: force start*/
/*description: force start.*/
#define RTC_I2C_TRANS_START (BIT(3))
#define RTC_I2C_TRANS_START_M (BIT(3))
#define RTC_I2C_TRANS_START_V 0x1
#define RTC_I2C_TRANS_START_S 3
/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: 1=master 0=slave*/
/*description: 1=master, 0=slave.*/
#define RTC_I2C_MS_MODE (BIT(2))
#define RTC_I2C_MS_MODE_M (BIT(2))
#define RTC_I2C_MS_MODE_V 0x1
#define RTC_I2C_MS_MODE_S 2
/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: 1=push pull 0=open drain*/
/*description: 1=push pull, 0=open drain.*/
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1))
#define RTC_I2C_SCL_FORCE_OUT_V 0x1
#define RTC_I2C_SCL_FORCE_OUT_S 1
/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: 1=push pull 0=open drain*/
/*description: 1=push pull, 0=open drain.*/
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0))
#define RTC_I2C_SDA_FORCE_OUT_V 0x1
#define RTC_I2C_SDA_FORCE_OUT_S 0
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8)
/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
/*description: scl last status*/
/*description: scl last status.*/
#define RTC_I2C_SCL_STATE_LAST 0x00000007
#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
#define RTC_I2C_SCL_STATE_LAST_V 0x7
#define RTC_I2C_SCL_STATE_LAST_S 28
/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
/*description: i2c last main status*/
/*description: i2c last main status.*/
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007
#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
/*description: shifter content*/
/*description: shifter content.*/
#define RTC_I2C_SHIFT 0x000000FF
#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
#define RTC_I2C_SHIFT_V 0xFF
#define RTC_I2C_SHIFT_S 16
/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
/*description: which operation is working*/
/*description: which operation is working.*/
#define RTC_I2C_OP_CNT 0x00000003
#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
#define RTC_I2C_OP_CNT_V 0x3
#define RTC_I2C_OP_CNT_S 6
/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: One byte transit done*/
/*description: One byte transit done.*/
#define RTC_I2C_BYTE_TRANS (BIT(5))
#define RTC_I2C_BYTE_TRANS_M (BIT(5))
#define RTC_I2C_BYTE_TRANS_V 0x1
#define RTC_I2C_BYTE_TRANS_S 5
/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: slave reg sub address*/
/*description: slave reg sub address.*/
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4))
#define RTC_I2C_SLAVE_ADDRESSED_V 0x1
#define RTC_I2C_SLAVE_ADDRESSED_S 4
/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: bus is busy*/
/*description: bus is busy.*/
#define RTC_I2C_BUS_BUSY (BIT(3))
#define RTC_I2C_BUS_BUSY_M (BIT(3))
#define RTC_I2C_BUS_BUSY_V 0x1
#define RTC_I2C_BUS_BUSY_S 3
/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: arbitration is lost*/
/*description: arbitration is lost.*/
#define RTC_I2C_ARB_LOST (BIT(2))
#define RTC_I2C_ARB_LOST_M (BIT(2))
#define RTC_I2C_ARB_LOST_V 0x1
#define RTC_I2C_ARB_LOST_S 2
/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: slave read or write*/
/*description: slave read or write.*/
#define RTC_I2C_SLAVE_RW (BIT(1))
#define RTC_I2C_SLAVE_RW_M (BIT(1))
#define RTC_I2C_SLAVE_RW_V 0x1
#define RTC_I2C_SLAVE_RW_S 1
/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: ack response*/
/*description: ack response.*/
#define RTC_I2C_ACK_REC (BIT(0))
#define RTC_I2C_ACK_REC_M (BIT(0))
#define RTC_I2C_ACK_REC_V 0x1
#define RTC_I2C_ACK_REC_S 0
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0xC)
/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
/*description: time out threshold*/
/*description: time out threshold.*/
#define RTC_I2C_TIMEOUT 0x000FFFFF
#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
#define RTC_I2C_TIMEOUT_V 0xFFFFF
#define RTC_I2C_TIMEOUT_S 0
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10)
/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: i2c 10bit mode enable*/
/*description: i2c 10bit mode enable.*/
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31))
#define RTC_I2C_ADDR_10BIT_EN_V 0x1
#define RTC_I2C_ADDR_10BIT_EN_S 31
/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
/*description: slave address*/
/*description: slave address.*/
#define RTC_I2C_SLAVE_ADDR 0x00007FFF
#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
#define RTC_I2C_SLAVE_ADDR_S 0
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14)
/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
/*description: time period that scl = 1*/
/*description: time period that scl = 1.*/
#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_HIGH_PERIOD_S 0
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18)
/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
/*description: time period for SDA to toggle after SCL goes low*/
/*description: time period for SDA to toggle after SCL goes low.*/
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF
#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF
#define RTC_I2C_SDA_DUTY_NUM_S 0
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1C)
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
/*description: time period for SCL to toggle after I2C start is triggered*/
/*description: time period for SCL to toggle after I2C start is triggered.*/
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_START_PERIOD_S 0
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20)
/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
/*description: time period for SCL to stop after I2C end is triggered*/
/*description: time period for SCL to stop after I2C end is triggered.*/
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF
#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
#define RTC_I2C_SCL_STOP_PERIOD_S 0
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24)
/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: clear detect start interrupt*/
/*description: clear detect start interrupt.*/
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_CLR_V 0x1
#define RTC_I2C_DETECT_START_INT_CLR_S 8
/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: clear transit load data complete interrupt*/
/*description: clear transit load data complete interrupt.*/
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_CLR_V 0x1
#define RTC_I2C_TX_DATA_INT_CLR_S 7
/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: clear receive data interrupt*/
/*description: clear receive data interrupt.*/
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_CLR_V 0x1
#define RTC_I2C_RX_DATA_INT_CLR_S 6
/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: clear ack error interrupt*/
/*description: clear ack error interrupt.*/
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: clear time out interrupt*/
/*description: clear time out interrupt.*/
#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4))
#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1
#define RTC_I2C_TIMEOUT_INT_CLR_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: clear transit complete interrupt*/
/*description: clear transit complete interrupt.*/
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: clear master transit complete interrupt*/
/*description: clear master transit complete interrupt.*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: clear arbitration lost interrupt*/
/*description: clear arbitration lost interrupt.*/
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: clear slave transit complete interrupt*/
/*description: clear slave transit complete interrupt.*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028)
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28)
/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: detect start interrupt raw*/
/*description: detect start interrupt raw.*/
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_RAW_V 0x1
#define RTC_I2C_DETECT_START_INT_RAW_S 8
/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: transit data interrupt raw*/
/*description: transit data interrupt raw.*/
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_RAW_V 0x1
#define RTC_I2C_TX_DATA_INT_RAW_S 7
/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: receive data interrupt raw*/
/*description: receive data interrupt raw.*/
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_RAW_V 0x1
#define RTC_I2C_RX_DATA_INT_RAW_S 6
/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ack error interrupt raw*/
/*description: ack error interrupt raw.*/
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: time out interrupt raw*/
/*description: time out interrupt raw.*/
#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4))
#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1
#define RTC_I2C_TIMEOUT_INT_RAW_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: transit complete interrupt raw*/
/*description: transit complete interrupt raw.*/
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: master transit complete interrupt raw*/
/*description: master transit complete interrupt raw.*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: arbitration lost interrupt raw*/
/*description: arbitration lost interrupt raw.*/
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: slave transit complete interrupt raw*/
/*description: slave transit complete interrupt raw.*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c)
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2C)
/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: detect start interrupt state*/
/*description: detect start interrupt state.*/
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_ST_V 0x1
#define RTC_I2C_DETECT_START_INT_ST_S 8
/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: transit data interrupt state*/
/*description: transit data interrupt state.*/
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_ST_V 0x1
#define RTC_I2C_TX_DATA_INT_ST_S 7
/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: receive data interrupt state*/
/*description: receive data interrupt state.*/
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_ST_V 0x1
#define RTC_I2C_RX_DATA_INT_ST_S 6
/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: ack error interrupt state*/
/*description: ack error interrupt state.*/
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ST_V 0x1
#define RTC_I2C_ACK_ERR_INT_ST_S 5
/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: time out interrupt state*/
/*description: time out interrupt state.*/
#define RTC_I2C_TIMEOUT_INT_ST (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ST_V 0x1
#define RTC_I2C_TIMEOUT_INT_ST_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: transit complete interrupt state*/
/*description: transit complete interrupt state.*/
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: master transit complete interrupt state*/
/*description: master transit complete interrupt state.*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: arbitration lost interrupt state*/
/*description: arbitration lost interrupt state.*/
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: slave transit complete interrupt state*/
/*description: slave transit complete interrupt state.*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030)
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30)
/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: enable detect start interrupt*/
/*description: enable detect start interrupt.*/
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8))
#define RTC_I2C_DETECT_START_INT_ENA_V 0x1
#define RTC_I2C_DETECT_START_INT_ENA_S 8
/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: enable transit data interrupt*/
/*description: enable transit data interrupt.*/
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7))
#define RTC_I2C_TX_DATA_INT_ENA_V 0x1
#define RTC_I2C_TX_DATA_INT_ENA_S 7
/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: enable receive data interrupt*/
/*description: enable receive data interrupt.*/
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6))
#define RTC_I2C_RX_DATA_INT_ENA_V 0x1
#define RTC_I2C_RX_DATA_INT_ENA_S 6
/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: enable eack error interrupt*/
/*description: enable eack error interrupt.*/
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5))
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: enable time out interrupt*/
/*description: enable time out interrupt.*/
#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4))
#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1
#define RTC_I2C_TIMEOUT_INT_ENA_S 4
/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: enable transit complete interrupt*/
/*description: enable transit complete interrupt.*/
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3))
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: enable master transit complete interrupt*/
/*description: enable master transit complete interrupt.*/
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2))
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: enable arbitration lost interrupt*/
/*description: enable arbitration lost interrupt.*/
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1))
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: enable slave transit complete interrupt*/
/*description: enable slave transit complete interrupt.*/
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0))
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034)
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34)
/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: i2c done*/
/*description: i2c done.*/
#define RTC_I2C_DONE (BIT(31))
#define RTC_I2C_DONE_M (BIT(31))
#define RTC_I2C_DONE_V 0x1
#define RTC_I2C_DONE_S 31
/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
/*description: data sent by slave*/
/*description: data sent by slave.*/
#define RTC_I2C_SLAVE_TX_DATA 0x000000FF
#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
#define RTC_I2C_SLAVE_TX_DATA_V 0xFF
#define RTC_I2C_SLAVE_TX_DATA_S 8
/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: data received*/
/*description: data received.*/
#define RTC_I2C_RDATA 0x000000FF
#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
#define RTC_I2C_RDATA_V 0xFF
#define RTC_I2C_RDATA_S 0
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038)
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38)
/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command0_done*/
/*description: command0_done.*/
#define RTC_I2C_COMMAND0_DONE (BIT(31))
#define RTC_I2C_COMMAND0_DONE_M (BIT(31))
#define RTC_I2C_COMMAND0_DONE_V 0x1
#define RTC_I2C_COMMAND0_DONE_S 31
/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
/*description: command0*/
/*description: command0.*/
#define RTC_I2C_COMMAND0 0x00003FFF
#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
#define RTC_I2C_COMMAND0_V 0x3FFF
#define RTC_I2C_COMMAND0_S 0
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c)
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3C)
/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command1_done*/
/*description: command1_done.*/
#define RTC_I2C_COMMAND1_DONE (BIT(31))
#define RTC_I2C_COMMAND1_DONE_M (BIT(31))
#define RTC_I2C_COMMAND1_DONE_V 0x1
#define RTC_I2C_COMMAND1_DONE_S 31
/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command1*/
/*description: command1.*/
#define RTC_I2C_COMMAND1 0x00003FFF
#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
#define RTC_I2C_COMMAND1_V 0x3FFF
#define RTC_I2C_COMMAND1_S 0
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040)
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40)
/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command2_done*/
/*description: command2_done.*/
#define RTC_I2C_COMMAND2_DONE (BIT(31))
#define RTC_I2C_COMMAND2_DONE_M (BIT(31))
#define RTC_I2C_COMMAND2_DONE_V 0x1
#define RTC_I2C_COMMAND2_DONE_S 31
/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
/*description: command2*/
/*description: command2.*/
#define RTC_I2C_COMMAND2 0x00003FFF
#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
#define RTC_I2C_COMMAND2_V 0x3FFF
#define RTC_I2C_COMMAND2_S 0
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044)
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44)
/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command3_done*/
/*description: command3_done.*/
#define RTC_I2C_COMMAND3_DONE (BIT(31))
#define RTC_I2C_COMMAND3_DONE_M (BIT(31))
#define RTC_I2C_COMMAND3_DONE_V 0x1
#define RTC_I2C_COMMAND3_DONE_S 31
/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
/*description: command3*/
/*description: command3.*/
#define RTC_I2C_COMMAND3 0x00003FFF
#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
#define RTC_I2C_COMMAND3_V 0x3FFF
#define RTC_I2C_COMMAND3_S 0
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048)
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48)
/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command4_done*/
/*description: command4_done.*/
#define RTC_I2C_COMMAND4_DONE (BIT(31))
#define RTC_I2C_COMMAND4_DONE_M (BIT(31))
#define RTC_I2C_COMMAND4_DONE_V 0x1
#define RTC_I2C_COMMAND4_DONE_S 31
/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
/*description: command4*/
/*description: command4.*/
#define RTC_I2C_COMMAND4 0x00003FFF
#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
#define RTC_I2C_COMMAND4_V 0x3FFF
#define RTC_I2C_COMMAND4_S 0
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c)
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4C)
/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command5_done*/
/*description: command5_done.*/
#define RTC_I2C_COMMAND5_DONE (BIT(31))
#define RTC_I2C_COMMAND5_DONE_M (BIT(31))
#define RTC_I2C_COMMAND5_DONE_V 0x1
#define RTC_I2C_COMMAND5_DONE_S 31
/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
/*description: command5*/
/*description: command5.*/
#define RTC_I2C_COMMAND5 0x00003FFF
#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
#define RTC_I2C_COMMAND5_V 0x3FFF
#define RTC_I2C_COMMAND5_S 0
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050)
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50)
/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command6_done*/
/*description: command6_done.*/
#define RTC_I2C_COMMAND6_DONE (BIT(31))
#define RTC_I2C_COMMAND6_DONE_M (BIT(31))
#define RTC_I2C_COMMAND6_DONE_V 0x1
#define RTC_I2C_COMMAND6_DONE_S 31
/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command6*/
/*description: command6.*/
#define RTC_I2C_COMMAND6 0x00003FFF
#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
#define RTC_I2C_COMMAND6_V 0x3FFF
#define RTC_I2C_COMMAND6_S 0
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054)
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54)
/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command7_done*/
/*description: command7_done.*/
#define RTC_I2C_COMMAND7_DONE (BIT(31))
#define RTC_I2C_COMMAND7_DONE_M (BIT(31))
#define RTC_I2C_COMMAND7_DONE_V 0x1
#define RTC_I2C_COMMAND7_DONE_S 31
/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
/*description: command7*/
/*description: command7.*/
#define RTC_I2C_COMMAND7 0x00003FFF
#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
#define RTC_I2C_COMMAND7_V 0x3FFF
#define RTC_I2C_COMMAND7_S 0
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058)
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58)
/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command8_done*/
/*description: command8_done.*/
#define RTC_I2C_COMMAND8_DONE (BIT(31))
#define RTC_I2C_COMMAND8_DONE_M (BIT(31))
#define RTC_I2C_COMMAND8_DONE_V 0x1
#define RTC_I2C_COMMAND8_DONE_S 31
/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command8*/
/*description: command8.*/
#define RTC_I2C_COMMAND8 0x00003FFF
#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
#define RTC_I2C_COMMAND8_V 0x3FFF
#define RTC_I2C_COMMAND8_S 0
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c)
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5C)
/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command9_done*/
/*description: command9_done.*/
#define RTC_I2C_COMMAND9_DONE (BIT(31))
#define RTC_I2C_COMMAND9_DONE_M (BIT(31))
#define RTC_I2C_COMMAND9_DONE_V 0x1
#define RTC_I2C_COMMAND9_DONE_S 31
/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
/*description: command9*/
/*description: command9.*/
#define RTC_I2C_COMMAND9 0x00003FFF
#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
#define RTC_I2C_COMMAND9_V 0x3FFF
#define RTC_I2C_COMMAND9_S 0
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060)
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60)
/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command10_done*/
/*description: command10_done.*/
#define RTC_I2C_COMMAND10_DONE (BIT(31))
#define RTC_I2C_COMMAND10_DONE_M (BIT(31))
#define RTC_I2C_COMMAND10_DONE_V 0x1
#define RTC_I2C_COMMAND10_DONE_S 31
/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
/*description: command10*/
/*description: command10.*/
#define RTC_I2C_COMMAND10 0x00003FFF
#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
#define RTC_I2C_COMMAND10_V 0x3FFF
#define RTC_I2C_COMMAND10_S 0
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064)
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64)
/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command11_done*/
/*description: command11_done.*/
#define RTC_I2C_COMMAND11_DONE (BIT(31))
#define RTC_I2C_COMMAND11_DONE_M (BIT(31))
#define RTC_I2C_COMMAND11_DONE_V 0x1
#define RTC_I2C_COMMAND11_DONE_S 31
/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
/*description: command11*/
/*description: command11.*/
#define RTC_I2C_COMMAND11 0x00003FFF
#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
#define RTC_I2C_COMMAND11_V 0x3FFF
#define RTC_I2C_COMMAND11_S 0
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068)
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68)
/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command12_done*/
/*description: command12_done.*/
#define RTC_I2C_COMMAND12_DONE (BIT(31))
#define RTC_I2C_COMMAND12_DONE_M (BIT(31))
#define RTC_I2C_COMMAND12_DONE_V 0x1
#define RTC_I2C_COMMAND12_DONE_S 31
/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
/*description: command12*/
/*description: command12.*/
#define RTC_I2C_COMMAND12 0x00003FFF
#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
#define RTC_I2C_COMMAND12_V 0x3FFF
#define RTC_I2C_COMMAND12_S 0
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c)
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6C)
/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command13_done*/
/*description: command13_done.*/
#define RTC_I2C_COMMAND13_DONE (BIT(31))
#define RTC_I2C_COMMAND13_DONE_M (BIT(31))
#define RTC_I2C_COMMAND13_DONE_V 0x1
#define RTC_I2C_COMMAND13_DONE_S 31
/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
/*description: command13*/
/*description: command13.*/
#define RTC_I2C_COMMAND13 0x00003FFF
#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
#define RTC_I2C_COMMAND13_V 0x3FFF
#define RTC_I2C_COMMAND13_S 0
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070)
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70)
/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command14_done*/
/*description: command14_done.*/
#define RTC_I2C_COMMAND14_DONE (BIT(31))
#define RTC_I2C_COMMAND14_DONE_M (BIT(31))
#define RTC_I2C_COMMAND14_DONE_V 0x1
#define RTC_I2C_COMMAND14_DONE_S 31
/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: command14*/
/*description: command14.*/
#define RTC_I2C_COMMAND14 0x00003FFF
#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
#define RTC_I2C_COMMAND14_V 0x3FFF
#define RTC_I2C_COMMAND14_S 0
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074)
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74)
/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: command15_done*/
/*description: command15_done.*/
#define RTC_I2C_COMMAND15_DONE (BIT(31))
#define RTC_I2C_COMMAND15_DONE_M (BIT(31))
#define RTC_I2C_COMMAND15_DONE_V 0x1
#define RTC_I2C_COMMAND15_DONE_S 31
/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
/*description: command15*/
/*description: command15.*/
#define RTC_I2C_COMMAND15 0x00003FFF
#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
#define RTC_I2C_COMMAND15_V 0x3FFF
#define RTC_I2C_COMMAND15_S 0
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xFC)
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
/*description: */
/*description: .*/
#define RTC_I2C_DATE 0x0FFFFFFF
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
#define RTC_I2C_DATE_V 0xFFFFFFF
#define RTC_I2C_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_I2C_REG_H_ */

8
components/soc/esp32s3/include/soc/rtc_i2c_struct.h
View File

@@ -29,9 +29,9 @@ typedef volatile struct {
} scl_low;
union {
struct {
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
uint32_t ms_mode: 1; /*1=master 0=slave*/
uint32_t sda_force_out : 1; /*1=push pull, 0=open drain*/
uint32_t scl_force_out : 1; /*1=push pull, 0=open drain*/
uint32_t ms_mode : 1; /*1=master, 0=slave*/
uint32_t trans_start : 1; /*force start*/
uint32_t tx_lsb_first : 1; /*transit lsb first*/
uint32_t rx_lsb_first : 1; /*receive lsb first*/
@@ -221,9 +221,7 @@ typedef volatile struct {
uint32_t val;
} date;
} rtc_i2c_dev_t;
extern rtc_i2c_dev_t RTC_I2C;
#ifdef __cplusplus
}
#endif

860
components/soc/esp32s3/include/soc/rtc_io_reg.h
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File diff suppressed because it is too large Load Diff

49
components/soc/esp32s3/include/soc/rtc_io_struct.h
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@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_RTC_IO_STRUCT_H_
#define _SOC_RTC_IO_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
@@ -93,9 +94,9 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0 : 2;
uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t pad_driver : 1; /*if set to 0: normal output, if set to 1: open drain*/
uint32_t reserved3 : 4;
uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t int_type : 3; /*if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger*/
uint32_t wakeup_enable : 1; /*RTC GPIO wakeup enable bit*/
uint32_t reserved11 : 21;
};
@@ -119,9 +120,9 @@ typedef volatile struct {
uint32_t fun_ie : 1; /*input enable in work mode*/
uint32_t slp_oe : 1; /*output enable in sleep mode*/
uint32_t slp_ie : 1; /*input enable in sleep mode*/
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t fun_sel : 2; /*function sel*/
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t xpd : 1; /*TOUCH_XPD*/
uint32_t tie_opt : 1; /*TOUCH_TIE_OPT*/
uint32_t start : 1; /*TOUCH_START*/
@@ -140,9 +141,9 @@ typedef volatile struct {
uint32_t x32p_fun_ie : 1; /*input enable in work mode*/
uint32_t x32p_slp_oe : 1; /*output enable in sleep mode*/
uint32_t x32p_slp_ie : 1; /*input enable in sleep mode*/
uint32_t x32p_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t x32p_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t x32p_fun_sel : 2; /*function sel*/
uint32_t x32p_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t x32p_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t x32p_rue : 1; /*RUE*/
uint32_t x32p_rde : 1; /*RDE*/
@@ -157,9 +158,9 @@ typedef volatile struct {
uint32_t x32n_fun_ie : 1; /*input enable in work mode*/
uint32_t x32n_slp_oe : 1; /*output enable in sleep mode*/
uint32_t x32n_slp_ie : 1; /*input enable in sleep mode*/
uint32_t x32n_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t x32n_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t x32n_fun_sel : 2; /*function sel*/
uint32_t x32n_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t x32n_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t x32n_rue : 1; /*RUE*/
uint32_t x32n_rde : 1; /*RDE*/
@@ -173,13 +174,13 @@ typedef volatile struct {
uint32_t reserved0 : 3;
uint32_t dac : 8; /*PDAC1_DAC*/
uint32_t xpd_dac : 1; /*PDAC1_XPD_DAC*/
uint32_t dac_xpd_force: 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
uint32_t dac_xpd_force : 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
uint32_t fun_ie : 1; /*input enable in work mode*/
uint32_t slp_oe : 1; /*output enable in sleep mode*/
uint32_t slp_ie : 1; /*input enable in sleep mode*/
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t fun_sel : 2; /*PDAC1 function sel*/
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rue : 1; /*PDAC1_RUE*/
uint32_t rde : 1; /*PDAC1_RDE*/
@@ -194,9 +195,9 @@ typedef volatile struct {
uint32_t rtc_pad19_fun_ie : 1; /*input enable in work mode*/
uint32_t rtc_pad19_slp_oe : 1; /*output enable in sleep mode*/
uint32_t rtc_pad19_slp_ie : 1; /*input enable in sleep mode*/
uint32_t rtc_pad19_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad19_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t rtc_pad19_fun_sel : 2; /*function sel*/
uint32_t rtc_pad19_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t rtc_pad19_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rtc_pad19_rue : 1; /*RUE*/
uint32_t rtc_pad19_rde : 1; /*RDE*/
@@ -211,9 +212,9 @@ typedef volatile struct {
uint32_t rtc_pad20_fun_ie : 1; /*input enable in work mode*/
uint32_t rtc_pad20_slp_oe : 1; /*output enable in sleep mode*/
uint32_t rtc_pad20_slp_ie : 1; /*input enable in sleep mode*/
uint32_t rtc_pad20_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad20_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t rtc_pad20_fun_sel : 2; /*function sel*/
uint32_t rtc_pad20_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t rtc_pad20_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rtc_pad20_rue : 1; /*RUE*/
uint32_t rtc_pad20_rde : 1; /*RDE*/
@@ -228,9 +229,9 @@ typedef volatile struct {
uint32_t rtc_pad21_fun_ie : 1; /*input enable in work mode*/
uint32_t rtc_pad21_slp_oe : 1; /*output enable in sleep mode*/
uint32_t rtc_pad21_slp_ie : 1; /*input enable in sleep mode*/
uint32_t rtc_pad21_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
uint32_t rtc_pad21_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
uint32_t rtc_pad21_fun_sel : 2; /*function sel*/
uint32_t rtc_pad21_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
uint32_t rtc_pad21_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
uint32_t reserved20 : 7;
uint32_t rtc_pad21_rue : 1; /*RUE*/
uint32_t rtc_pad21_rde : 1; /*RDE*/
@@ -346,9 +347,11 @@ typedef volatile struct {
uint32_t val;
} date;
} rtc_io_dev_t;
extern rtc_io_dev_t RTCIO;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_RTC_IO_STRUCT_H_ */

1132
components/soc/esp32s3/include/soc/sens_reg.h
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File diff suppressed because it is too large Load Diff

104
components/soc/esp32s3/include/soc/sens_struct.h
View File

@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SENS_STRUCT_H_
#define _SOC_SENS_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
@@ -232,6 +233,13 @@ typedef volatile struct {
};
uint32_t val;
} sar_touch_conf;
union {
struct {
uint32_t touch_denoise_data : 22;
uint32_t reserved22 : 10;
};
uint32_t val;
} sar_touch_denoise;
union {
struct {
uint32_t thresh : 22; /*Finger threshold for touch pad 1*/
@@ -239,21 +247,6 @@ typedef volatile struct {
};
uint32_t val;
} touch_thresh[14];
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
union {
struct {
uint32_t touch_pad_active: 15; /*touch active status*/
@@ -431,8 +424,7 @@ typedef volatile struct {
uint32_t sar_nouse; /**/
union {
struct {
uint32_t reserved0: 26;
uint32_t dac_clk_en: 1;
uint32_t reserved0 : 27;
uint32_t rtc_i2c_clk_en : 1;
uint32_t reserved28 : 1;
uint32_t tsens_clk_en : 1;
@@ -445,7 +437,7 @@ typedef volatile struct {
struct {
uint32_t reserved0: 25;
uint32_t reset: 1;
uint32_t dac_reset: 1;
uint32_t reserved26 : 1;
uint32_t rtc_i2c_reset: 1;
uint32_t reserved28: 1;
uint32_t tsens_reset: 1;
@@ -490,6 +482,70 @@ typedef volatile struct {
};
uint32_t val;
} sar_cocpu_int_ena_w1tc;
union {
struct {
uint32_t debug_bit_sel : 5;
uint32_t reserved5 : 27;
};
uint32_t val;
} sar_debug_conf;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
union {
struct {
uint32_t sar_date : 28;
@@ -498,9 +554,11 @@ typedef volatile struct {
uint32_t val;
} sardate;
} sens_dev_t;
extern sens_dev_t SENS;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SENS_STRUCT_H_ */

4586
components/soc/esp32s3/include/soc/sensitive_reg.h
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File diff suppressed because it is too large Load Diff

1136
components/soc/esp32s3/include/soc/sensitive_struct.h
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File diff suppressed because it is too large Load Diff

37
components/soc/esp32s3/include/soc/sigmadelta_caps.h Normal file
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@@ -0,0 +1,37 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S3 have 1 SIGMADELTA peripheral.
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
#define SIGMADELTA_CHANNEL_MAX (8)
#ifdef __cplusplus
}
#endif

4
components/soc/esp32s3/include/soc/soc.h
View File

@@ -71,7 +71,7 @@
#define DR_REG_PCNT_BASE 0x60017000
#define DR_REG_SLC_BASE 0x60018000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_EFUSE_BASE 0x6001A000
#define DR_REG_EFUSE_BASE 0x60007000
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_PWM0_BASE 0x6001E000
@@ -85,11 +85,13 @@
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define DR_REG_PERI_BACKUP_BASE 0x6002A000
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_SPI4_BASE 0x60037000
#define DR_REG_USB_DEVICE_BASE 0x60038000
#define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_LCD_CAM_BASE 0x60041000

1753
components/soc/esp32s3/include/soc/spi_mem_reg.h
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File diff suppressed because it is too large Load Diff

539
components/soc/esp32s3/include/soc/spi_mem_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,27 +11,25 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SPI_MEM_STRUCT_H_
#define _SOC_SPI_MEM_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t reserved0 : 17; /*reserved*/
uint32_t flash_pe : 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_res : 1; /*This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
uint32_t flash_pp : 1; /*Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
@@ -41,43 +39,42 @@ typedef volatile struct {
};
uint32_t val;
} cmd;
uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/
uint32_t addr;
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
uint32_t fdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/
uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/
uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/
uint32_t fcs_crc_en : 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en : 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t fdummy_out : 1; /*In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
uint32_t fdout_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.*/
uint32_t fdin_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DIN phase.*/
uint32_t faddr_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.*/
uint32_t fcmd_dual : 1; /*Set this bit to enable 2-bit-mode(2-bm) in CMD phase.*/
uint32_t fcmd_quad : 1; /*Set this bit to enable 4-bit-mode(4-bm) in CMD phase.*/
uint32_t fcmd_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in CMD phase.*/
uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/
uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
uint32_t reserved12 : 1; /*reserved*/
uint32_t fastrd_mode : 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
uint32_t fread_dual : 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t reserved15 : 3; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
uint32_t reserved22 : 1; /*reserved*/
uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t fastrd_mode : 1; /*This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.*/
uint32_t fread_dual : 1; /*In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. */
uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
uint32_t reserved16 : 2; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/
uint32_t fread_quad : 1; /*In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */
uint32_t wrsr_2b : 1; /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. */
uint32_t fread_dio : 1; /*In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. */
uint32_t fread_qio : 1; /*In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t cs_hold_dly_res : 12; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by spi clock.*/
uint32_t cs_hold_dly : 12; /*SPI fsm is delayed to idle by spi clock cycles.*/
uint32_t cs_dly_num : 2; /*spi_mem_cs signal is delayed by system clock cycles*/
uint32_t cs_dly_mode : 2; /*The cs signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/
uint32_t reserved30 : 1;
uint32_t cs_dly_edge : 1; /*The bit is used to select the spi clock edge to modify CS line timing.*/
uint32_t clk_mode : 2; /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/
uint32_t cs_hold_dly_res : 10; /*Delay cycles of resume Flash when resume Flash from standby mode is enable by SPI_CLK.*/
uint32_t reserved12 : 18; /*reserved*/
uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} ctrl1;
@@ -86,18 +83,21 @@ typedef volatile struct {
uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t ecc_cs_hold_time: 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/
uint32_t reserved13 : 18; /*reserved*/
uint32_t ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
uint32_t ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
uint32_t reserved15: 10; /*reserved*/
uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
uint32_t sync_reset : 1; /*The FSM will be reset.*/
};
uint32_t val;
} ctrl2;
union {
struct {
uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk.*/
uint32_t clk_equ_sysclk : 1; /*reserved*/
uint32_t clkcnt_l : 8; /*It must equal to the value of SPI_MEM_CLKCNT_N. */
uint32_t clkcnt_h : 8; /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/
uint32_t clkcnt_n : 8; /*When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
};
uint32_t val;
} clock;
@@ -107,51 +107,51 @@ typedef volatile struct {
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t reserved8: 1; /*reserved*/
uint32_t ck_out_edge : 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
uint32_t ck_out_edge : 1; /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/
uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t fwrite_dual : 1; /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/
uint32_t fwrite_quad : 1; /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/
uint32_t fwrite_dio : 1; /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/
uint32_t fwrite_qio : 1; /*Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.*/
uint32_t reserved16 : 8; /*reserved*/
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/
uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/
uint32_t usr_miso_highpart : 1; /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
uint32_t usr_mosi_highpart : 1; /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
uint32_t usr_dummy_idle : 1; /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/
uint32_t usr_mosi : 1; /*This bit enable the DOUT phase of an write-data operation.*/
uint32_t usr_miso : 1; /*This bit enable the DIN phase of a read-data operation.*/
uint32_t usr_dummy : 1; /*This bit enable the DUMMY phase of an operation.*/
uint32_t usr_addr : 1; /*This bit enable the ADDR phase of an operation.*/
uint32_t usr_command : 1; /*This bit enable the CMD phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
uint32_t usr_dummy_cyclelen : 6; /*The SPI_CLK cycle length minus 1 of DUMMY phase.*/
uint32_t reserved6 : 20; /*reserved*/
uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t usr_addr_bitlen : 6; /*The length in bits of ADDR phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command.*/
uint32_t usr_command_value : 16; /*The value of user defined(USR) command.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
uint32_t usr_command_bitlen : 4; /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/
};
uint32_t val;
} user2;
union {
struct {
uint32_t usr_mosi_bit_len : 11; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved11 : 21; /*reserved*/
uint32_t usr_mosi_bit_len:10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len : 11; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved11 : 21; /*reserved*/
uint32_t usr_miso_bit_len:10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} miso_dlen;
@@ -171,7 +171,7 @@ typedef volatile struct {
uint32_t reserved2: 1; /*reserved*/
uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/
uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/
uint32_t cs_pol : 2; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/
uint32_t reserved5: 2; /*reserved*/
uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/
uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
@@ -184,123 +184,133 @@ typedef volatile struct {
uint32_t tx_crc; /*For SPI1 the value of crc32.*/
union {
struct {
uint32_t req_en : 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
uint32_t usr_cmd_4byte : 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t flash_usr_cmd : 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
uint32_t fdin_dual : 1; /*For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdout_dual : 1; /*For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t faddr_dual : 1; /*For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad : 1; /*For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad : 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t faddr_quad : 1; /*For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t req_en : 1; /*Set this bit to enable Cache's access and SPI0's transfer.*/
uint32_t usr_cmd_4byte : 1; /*Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.*/
uint32_t flash_usr_cmd : 1; /*1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/
uint32_t fdin_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/
uint32_t fdout_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.*/
uint32_t faddr_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.*/
uint32_t fdin_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.*/
uint32_t fdout_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.*/
uint32_t faddr_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} cache_fctrl;
union {
struct {
uint32_t usr_scmd_4byte : 1; /*For SPI0 In the spi sram mode cache read flash with 4 bytes command 1: enable 0:disable.*/
uint32_t usr_sram_dio : 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
uint32_t usr_sram_qio : 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
uint32_t usr_wr_sram_dummy : 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
uint32_t usr_rd_sram_dummy : 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
uint32_t cache_sram_usr_rcmd : 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
uint32_t sram_rdummy_cyclelen : 6; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
uint32_t usr_scmd_4byte : 1; /*Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/
uint32_t usr_sram_dio : 1; /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/
uint32_t usr_sram_qio : 1; /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/
uint32_t usr_wr_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.*/
uint32_t usr_rd_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.*/
uint32_t usr_rcmd : 1; /*1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.*/
uint32_t sram_rdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.*/
uint32_t reserved12 : 2; /*reserved*/
uint32_t sram_addr_bitlen : 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t cache_sram_usr_wcmd : 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
uint32_t sram_oct : 1; /*reserved*/
uint32_t sram_wdummy_cyclelen : 6; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
uint32_t sram_addr_bitlen : 6; /*When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).*/
uint32_t usr_wcmd : 1; /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/
uint32_t sram_oct : 1; /*Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.*/
uint32_t sram_wdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} cache_sctrl;
union {
struct {
uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t swb_mode : 8; /*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/
uint32_t sdin_dual : 1; /*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdout_dual : 1; /*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t saddr_dual : 1; /*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t scmd_dual : 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
uint32_t sdin_quad : 1; /*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t sdout_quad : 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t saddr_quad : 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t scmd_quad : 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
uint32_t sdin_oct : 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/
uint32_t sdout_oct : 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/
uint32_t saddr_oct : 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/
uint32_t scmd_oct : 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/
uint32_t sdummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
uint32_t sclk_mode : 2; /*SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.*/
uint32_t swb_mode : 8; /*Mode bits when SPI0 accesses to Ext_RAM.*/
uint32_t sdin_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/
uint32_t sdout_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/
uint32_t saddr_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.*/
uint32_t scmd_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.*/
uint32_t sdin_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.*/
uint32_t sdout_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.*/
uint32_t saddr_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.*/
uint32_t scmd_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.*/
uint32_t sdin_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/
uint32_t sdout_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/
uint32_t saddr_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.*/
uint32_t scmd_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.*/
uint32_t sdummy_out : 1; /*When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} sram_cmd;
union {
struct {
uint32_t usr_rd_cmd_value : 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/
uint32_t usr_rd_cmd_value : 16; /*When SPI0 reads Ext_RAM, it is the command value of CMD phase.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_rd_cmd_bitlen : 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
uint32_t usr_rd_cmd_bitlen : 4; /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_drd_cmd;
union {
struct {
uint32_t usr_wr_cmd_value : 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
uint32_t usr_wr_cmd_value : 16; /*When SPI0 writes Ext_RAM, it is the command value of CMD phase.*/
uint32_t reserved16 : 12; /*reserved*/
uint32_t usr_wr_cmd_bitlen : 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/
uint32_t usr_wr_cmd_bitlen : 4; /*When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
};
uint32_t val;
} sram_dwr_cmd;
union {
struct {
uint32_t cnt_l : 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/
uint32_t cnt_h : 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t cnt_n : 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t cnt_l : 8; /*It must equal to the value of SPI_MEM_SCLKCNT_N. */
uint32_t cnt_h : 8; /*It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).*/
uint32_t cnt_n : 8; /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t equ_sysclk : 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
uint32_t equ_sysclk : 1; /*When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
};
uint32_t val;
} sram_clk;
union {
struct {
uint32_t st : 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
uint32_t st : 3; /*The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} fsm;
uint32_t data_buf[18]; /*data buffer*/
uint32_t data_buf[16]; /*data buffer*/
union {
struct {
uint32_t waiti_en : 1; /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/
uint32_t waiti_en : 1; /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/
uint32_t waiti_dummy : 1; /*The dummy phase enable when auto wait flash idle*/
uint32_t waiti_cmd : 8; /*The command to auto wait idle*/
uint32_t waiti_dummy_cyclelen : 8; /*The dummy cycle length when auto wait flash idle*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when auto wait flash idle */
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} flash_waiti_ctrl;
union {
struct {
uint32_t flash_per : 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes : 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t reserved2 : 30;
uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
uint32_t flash_per_wait_en : 1; /*Set this bit to add delay time after program erase resume(PER) is sent.*/
uint32_t flash_pes_wait_en : 1; /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/
uint32_t pes_per_en : 1; /*Set this bit to enable PES transfer trigger PES transfer option.*/
uint32_t pesr_idle_en : 1; /*1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.*/
uint32_t reserved6 : 26; /*reserved*/
};
uint32_t val;
} flash_sus_cmd;
union {
struct {
uint32_t flash_pes_en : 1; /*Auto-suspending enable*/
uint32_t flash_per_command : 8; /*Program/Erase resume command.*/
uint32_t flash_pes_command : 8; /*Program/Erase suspend command.*/
uint32_t reserved17 : 15;
uint32_t flash_pes_en : 1; /*Set this bit to enable auto-suspend function.*/
uint32_t flash_per_command : 8; /*Program/Erase resume command value.*/
uint32_t flash_pes_command : 8; /*Program/Erase suspend command value.*/
uint32_t reserved17 : 15; /*reserved*/
};
uint32_t val;
} flash_sus_ctrl;
union {
struct {
uint32_t flash_sus : 1; /*The status of flash suspend only used in SPI1.*/
uint32_t reserved1 : 31;
uint32_t flash_sus : 1; /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.*/
uint32_t reserved1 : 1; /*reserved*/
uint32_t flash_hpm_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
uint32_t flash_res_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
uint32_t flash_dp_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
uint32_t flash_per_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
uint32_t flash_pes_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
uint32_t reserved7 : 25; /*reserved*/
};
uint32_t val;
} sus_status;
@@ -315,45 +325,45 @@ typedef volatile struct {
} timing_cali;
union {
struct {
uint32_t din0_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din1_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din2_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din3_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t din4_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din5_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din6_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t din7_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t dins_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} din_mode;
union {
struct {
uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din0_num : 2; /*SPI_D input delay number.*/
uint32_t din1_num : 2; /*SPI_Q input delay number.*/
uint32_t din2_num : 2; /*SPI_WP input delay number.*/
uint32_t din3_num : 2; /*SPI_HD input delay number.*/
uint32_t din4_num : 2; /*SPI_IO4 input delay number.*/
uint32_t din5_num : 2; /*SPI_IO5 input delay number.*/
uint32_t din6_num : 2; /*SPI_IO6 input delay number.*/
uint32_t din7_num : 2; /*SPI_IO7 input delay number.*/
uint32_t dins_num : 2; /*SPI_DQS input delay number.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
uint32_t dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
@@ -361,114 +371,141 @@ typedef volatile struct {
uint32_t reserved_b8;
union {
struct {
uint32_t spi_smem_timing_clk_ena : 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/
uint32_t spi_smem_timing_cali : 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t spi_smem_extra_dummy_cyclelen : 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5 : 27;
uint32_t smem_timing_clk_ena : 1; /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
uint32_t smem_timing_cali : 1; /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
uint32_t smem_extra_dummy_cyclelen : 3; /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} spi_smem_timing_cali;
union {
struct {
uint32_t spi_smem_din0_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din1_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din2_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din3_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din4_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din5_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din6_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_din7_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t spi_smem_dins_mode : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t reserved18 : 14; /*reserved*/
uint32_t smem_din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
} spi_smem_din_mode;
union {
struct {
uint32_t spi_smem_din0_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din1_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din2_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din3_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din4_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din5_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din6_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_din7_num : 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t spi_smem_dins_num : 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
uint32_t smem_din0_num : 2; /*SPI_D input delay number.*/
uint32_t smem_din1_num : 2; /*SPI_Q input delay number.*/
uint32_t smem_din2_num : 2; /*SPI_WP input delay number.*/
uint32_t smem_din3_num : 2; /*SPI_HD input delay number.*/
uint32_t smem_din4_num : 2; /*SPI_IO4 input delay number.*/
uint32_t smem_din5_num : 2; /*SPI_IO5 input delay number.*/
uint32_t smem_din6_num : 2; /*SPI_IO6 input delay number.*/
uint32_t smem_din7_num : 2; /*SPI_IO7 input delay number.*/
uint32_t smem_dins_num : 2; /*SPI_DQS input delay number.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} spi_smem_din_num;
union {
struct {
uint32_t spi_smem_dout0_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout1_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout2_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout3_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout4_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout5_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout6_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_dout7_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t spi_smem_douts_mode : 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
uint32_t smem_dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t smem_douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} spi_smem_dout_mode;
uint32_t reserved_cc;
union {
struct {
uint32_t spi_smem_cs_setup : 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_hold : 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
uint32_t spi_smem_cs_setup_time : 5; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t spi_smem_cs_hold_time : 5; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
uint32_t spi_smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accessed external RAM.*/
uint32_t reserved15 : 17;
uint32_t ecc_err_int_num : 8; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} ecc_ctrl;
uint32_t ecc_err_addr;
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
uint32_t ecc_data_err_bit : 7; /*It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
uint32_t ecc_chk_err_bit : 3; /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/
uint32_t ecc_byte_err : 1; /*It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
uint32_t ecc_err_cnt : 8; /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} ecc_err_bit;
uint32_t reserved_d8;
union {
struct {
uint32_t smem_cs_setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
uint32_t smem_cs_hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
uint32_t smem_cs_setup_time : 5; /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
uint32_t smem_cs_hold_time : 5; /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
uint32_t smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/
uint32_t smem_ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.*/
uint32_t smem_ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.*/
uint32_t reserved17 : 7; /*reserved*/
uint32_t smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
uint32_t smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} spi_smem_ac;
union {
struct {
uint32_t spi_fmem_ddr_en : 1; /*1: in ddr mode 0 in sdr mode*/
uint32_t spi_fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t spi_fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/
uint32_t spi_fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to flash.*/
uint32_t spi_fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to flash.*/
uint32_t spi_fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/
uint32_t spi_fmem_ddr_dqs_loop : 1; /*the data strobe is generated by SPI.*/
uint32_t spi_fmem_ddr_dqs_loop_mode : 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_t spi_fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t spi_fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t spi_fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t spi_fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/
uint32_t spi_fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
uint32_t spi_fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/
uint32_t spi_fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/
uint32_t fmem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
uint32_t fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in DDR mode.*/
uint32_t fmem_ddr_rdat_swp : 1; /*Set the bit to reorder RX data of the word in DDR mode.*/
uint32_t fmem_ddr_wdat_swp : 1; /*Set the bit to swap TX data of a word in DDR mode.*/
uint32_t fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
uint32_t fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/
uint32_t fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.*/
uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/
uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
uint32_t fmem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
uint32_t fmem_ddr_dqs_loop_mode : 1; /*When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/
uint32_t reserved23 : 1; /*reserved*/
uint32_t fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
uint32_t fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
uint32_t fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
uint32_t fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
} ddr;
union {
struct {
uint32_t spi_smem_ddr_en : 1; /*1: in ddr mode 0 in sdr mode*/
uint32_t spi_smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t spi_smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t spi_smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
uint32_t spi_smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/
uint32_t spi_smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to external RAM.*/
uint32_t spi_smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to external RAM.*/
uint32_t spi_smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/
uint32_t spi_smem_ddr_dqs_loop : 1; /*the data strobe is generated by SPI.*/
uint32_t spi_smem_ddr_dqs_loop_mode : 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
uint32_t spi_smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t spi_smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t spi_smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t spi_smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/
uint32_t spi_smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
uint32_t spi_smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/
uint32_t spi_smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/
uint32_t smem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
uint32_t smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
uint32_t smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
uint32_t smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
uint32_t smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
uint32_t smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/
uint32_t smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.*/
uint32_t smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.*/
uint32_t smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
uint32_t smem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
uint32_t smem_ddr_dqs_loop_mode : 1; /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/
uint32_t reserved23 : 1; /*reserved*/
uint32_t smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
uint32_t smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
uint32_t smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
uint32_t smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
uint32_t smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
uint32_t smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
uint32_t smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
uint32_t reserved31 : 1; /*reserved*/
};
uint32_t val;
@@ -487,13 +524,50 @@ typedef volatile struct {
};
uint32_t val;
} core_clk_sel;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
union {
struct {
uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t total_trans_end_en : 1; /*The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t per_end_int_clr : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_int_clr : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t total_trans_end_int_clr : 1; /*The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_int_clr : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_int_clr : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t per_end_int_raw : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
uint32_t total_trans_end_int_raw : 1; /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.*/
uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t ecc_err_int_raw : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t per_end_int_st : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
uint32_t pes_end_int_st : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t total_trans_end_int_st : 1; /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
uint32_t brown_out_int_st : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
uint32_t ecc_err_int_st : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} int_st;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
@@ -695,6 +769,11 @@ typedef volatile struct {
} spi_mem_dev_t;
extern spi_mem_dev_t SPIMEM0;
extern spi_mem_dev_t SPIMEM1;
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SPI_MEM_STRUCT_H_ */

1299
components/soc/esp32s3/include/soc/spi_reg.h
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File diff suppressed because it is too large Load Diff

215
components/soc/esp32s3/include/soc/spi_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,26 +11,24 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SPI_STRUCT_H_
#define _SOC_SPI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
uint32_t reserved18 : 5; /*reserved*/
uint32_t update: 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain which is only used in SPI master mode.*/
uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} cmd;
uint32_t addr; /*Address to slave. Can be configured in CONF state.*/
uint32_t addr;
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
@@ -43,17 +41,17 @@ typedef volatile struct {
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved11 : 3; /*reserved*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved17 : 1; /*reserved*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t hold_pol: 1; /*SPI_HOLD output value when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/
uint32_t reserved22: 3; /*reserved*/
uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t reserved22 : 1; /*reserved*/
uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27 : 5; /*reserved*/
};
uint32_t val;
@@ -63,7 +61,8 @@ typedef volatile struct {
uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
uint32_t reserved22 : 9; /*reserved*/
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
};
uint32_t val;
@@ -74,16 +73,16 @@ typedef volatile struct {
uint32_t reserved1 : 2; /*reserved*/
uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
uint32_t opi_mode : 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
uint32_t tsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t rsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
uint32_t reserved10 : 2; /*reserved*/
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
uint32_t reserved16 : 1; /*reserved*/
uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved18 : 6; /*reserved*/
@@ -101,7 +100,8 @@ typedef volatile struct {
union {
struct {
uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
uint32_t reserved8: 9; /*reserved*/
uint32_t reserved8 : 8; /*reserved*/
uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
@@ -111,7 +111,8 @@ typedef volatile struct {
union {
struct {
uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/
uint32_t reserved16: 12; /*reserved*/
uint32_t reserved16 : 11; /*reserved*/
uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
@@ -125,19 +126,19 @@ typedef volatile struct {
} ms_dlen;
union {
struct {
uint32_t cs0_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs1_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs2_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs3_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs4_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs5_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/
uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/
uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
uint32_t reserved13 : 3; /*reserved*/
uint32_t clk_data_dtr_en: 1; /*1: SPI master DTR mode is applied to SPI clk data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.*/
uint32_t data_dtr_en: 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
uint32_t addr_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
uint32_t cmd_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
uint32_t clk_data_dtr_en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. */
uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
uint32_t addr_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
uint32_t reserved20 : 3; /*reserved*/
uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/
uint32_t dqs_idle_edge : 1; /*The default value of spi_dqs. Can be configured in CONF state.*/
@@ -150,14 +151,14 @@ typedef volatile struct {
} misc;
union {
struct {
uint32_t din0_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din1_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din2_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din3_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din4_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din5_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din6_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din7_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din4_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din5_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/
uint32_t reserved17 : 15; /*reserved*/
};
@@ -165,36 +166,38 @@ typedef volatile struct {
} din_mode;
union {
struct {
uint32_t din0_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din1_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din2_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din3_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din4_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din5_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din6_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din7_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/
uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din4_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din5_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} din_num;
union {
struct {
uint32_t dout0_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout1_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout2_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout3_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout4_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout5_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout6_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout7_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t d_dqs_mode: 1; /*The output signal SPI_DQS is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout4_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout5_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t d_dqs_mode : 1; /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t reserved9 : 23; /*reserved*/
};
uint32_t val;
} dout_mode;
union {
struct {
uint32_t reserved0: 18; /*reserved*/
uint32_t outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
uint32_t reserved2 : 16; /*reserved*/
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
@@ -202,9 +205,9 @@ typedef volatile struct {
uint32_t reserved22 : 5; /*reserved*/
uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
uint32_t rx_afifo_rst: 1; /*Set this bit to reset RX AFIFO which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo_rst: 1; /*Set this bit to reset BUF TX AFIFO which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
uint32_t dma_afifo_rst: 1; /*Set this bit to reset DMA TX AFIFO which is used to send data out in SPI slave DMA controlled mode transfer.*/
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
};
uint32_t val;
} dma_conf;
@@ -227,12 +230,11 @@ typedef volatile struct {
uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t rx_afifo_wfull_err: 1; /*The enable bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/
uint32_t mst_rx_afifo_wfull_err: 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/
uint32_t buf_tx_afifo_rerr: 1; /*The enable bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/
uint32_t dma_tx_afifo_rerr: 1; /*The enable bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/
uint32_t mst_tx_afifo_rerr: 1; /*The enable bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/
uint32_t reserved22: 10; /*reserved*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_ena;
@@ -255,18 +257,17 @@ typedef volatile struct {
uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t rx_afifo_wfull_err: 1; /*The clear bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/
uint32_t mst_rx_afifo_wfull_err: 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/
uint32_t buf_tx_afifo_rerr: 1; /*The clear bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/
uint32_t dma_tx_afifo_rerr: 1; /*The clear bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/
uint32_t mst_tx_afifo_rerr: 1; /*The clear bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/
uint32_t reserved22: 10; /*reserved*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_clr;
union {
struct {
uint32_t infifo_full_err: 1; /*1: The current data rate of DMA Rx is smaller than that of SPI which will lose the receive data. 0: Others.*/
uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */
uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */
uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
@@ -281,14 +282,13 @@ typedef volatile struct {
uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */
uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
uint32_t buf_addr_err: 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
uint32_t rx_afifo_wfull_err: 1; /*The raw bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt. 1: SPI AFIFO overflow when SPI slave reads data in CPU/DMA controlled mode. 0: Others.*/
uint32_t mst_rx_afifo_wfull_err: 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: SPI AFIFO overflow when SPI master reads data in CPU/DMA controlled mode. 0: Others.*/
uint32_t buf_tx_afifo_rerr: 1; /*The raw bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI slave sent data out in CPU controlled mode 0: Others.*/
uint32_t dma_tx_afifo_rerr: 1; /*The raw bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI slave sent data out in DMA controlled mode 0: Others.*/
uint32_t mst_tx_afifo_rerr: 1; /*The raw bit for SPI_MST_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI master sends data out in CPU/DMA controlled mode. 0: Others.*/
uint32_t reserved22: 10; /*SPI interrupt raw register. Can be configured in CONF state.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_raw;
@@ -311,16 +311,41 @@ typedef volatile struct {
uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t rx_afifo_wfull_err: 1; /*The status bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/
uint32_t mst_rx_afifo_wfull_err: 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/
uint32_t buf_tx_afifo_rerr: 1; /*The status bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/
uint32_t dma_tx_afifo_rerr: 1; /*The status bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/
uint32_t mst_tx_afifo_rerr: 1; /*The status bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/
uint32_t reserved22: 10; /*reserved*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_st;
uint32_t reserved_44;
union {
struct {
uint32_t infifo_full_err_int_set : 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi_int_set : 1; /*The software set bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7_int_set : 1; /*The software set bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8_int_set : 1; /*The software set bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9_int_set : 1; /*The software set bit for SPI slave CMD9 interrupt.*/
uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done_int_set : 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done_int_set : 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done_int_set : 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err_int_set : 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err_int_set : 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/
uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_set;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
@@ -341,13 +366,13 @@ typedef volatile struct {
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t data_buf[16]; /*data buffer*/
uint32_t data_buf[16]; /*SPI CPU-controlled buffer0*/
uint32_t reserved_d8;
uint32_t reserved_dc;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */
uint32_t reserved4 : 4; /*reserved*/
uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
@@ -357,8 +382,8 @@ typedef volatile struct {
uint32_t reserved12 : 10; /*reserved*/
uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/
uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
uint32_t soft_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
uint32_t usr_conf: 1; /*1: Enable the DMA CONF phase of current seg-trans operation which means seg-trans will start. 0: This is not seg-trans mode.*/
uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
@@ -389,10 +414,10 @@ typedef volatile struct {
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2;
extern spi_dev_t GPSPI3;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SPI_STRUCT_H_ */

380
components/soc/esp32s3/include/soc/sys_timer_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,410 +11,464 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SYS_TIMER_REG_H_
#define _SOC_SYS_TIMER_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000)
#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0)
/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating*/
/*description: register file clk gating.*/
#define SYS_TIMER_CLK_EN (BIT(31))
#define SYS_TIMER_CLK_EN_M (BIT(31))
#define SYS_TIMER_CLK_EN_V 0x1
#define SYS_TIMER_CLK_EN_S 31
/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: timer unit0 work enable*/
/*description: timer unit0 work enable.*/
#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30
/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer unit1 work enable*/
/*description: timer unit1 work enable.*/
#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29
/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core0 stalled*/
/*description: If timer unit0 is stalled when core0 stalled.*/
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28))
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core1 stalled*/
/*description: If timer unit0 is stalled when core1 stalled.*/
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27))
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core0 stalled*/
/*description: If timer unit1 is stalled when core0 stalled.*/
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26))
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core1 stalled*/
/*description: If timer unit1 is stalled when core1 stalled.*/
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25))
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: target0 work enable*/
/*description: target0 work enable.*/
#define SYS_TIMER_TARGET0_WORK_EN (BIT(24))
#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24))
#define SYS_TIMER_TARGET0_WORK_EN_V 0x1
#define SYS_TIMER_TARGET0_WORK_EN_S 24
/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: target1 work enable*/
/*description: target1 work enable.*/
#define SYS_TIMER_TARGET1_WORK_EN (BIT(23))
#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23))
#define SYS_TIMER_TARGET1_WORK_EN_V 0x1
#define SYS_TIMER_TARGET1_WORK_EN_S 23
/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: target2 work enable*/
/*description: target2 work enable.*/
#define SYS_TIMER_TARGET2_WORK_EN (BIT(22))
#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22))
#define SYS_TIMER_TARGET2_WORK_EN_V 0x1
#define SYS_TIMER_TARGET2_WORK_EN_S 22
/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: systimer clock force on*/
/*description: systimer clock force on.*/
#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0))
#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1
#define SYS_TIMER_SYSTIMER_CLK_FO_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004)
/* SYS_TIMER_TIMER_UNIT0_UPDATE : WO ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer_unit0*/
#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x4)
/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer_unit0.*/
#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1
#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30
/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: .*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29
#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008)
/* SYS_TIMER_TIMER_UNIT1_UPDATE : WO ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer unit1*/
#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x8)
/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer unit1.*/
#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1
#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30
/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : RO ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer value is sync and valid*/
/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer value is sync and valid.*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C)
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0xC)
/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit0 load high 32 bit*/
/*description: timer unit0 load high 32 bit.*/
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S))
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010)
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x10)
/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit0 load low 32 bit*/
/*description: timer unit0 load low 32 bit.*/
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S))
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014)
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x14)
/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit1 load high 32 bit*/
/*description: timer unit1 load high 32 bit.*/
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S))
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018)
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x18)
/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit1 load low 32 bit*/
/*description: timer unit1 load low 32 bit.*/
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S))
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C)
#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x1C)
/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget0 high 32 bit*/
/*description: timer taget0 high 32 bit.*/
#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S))
#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET0_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020)
#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x20)
/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget0 low 32 bit*/
/*description: timer taget0 low 32 bit.*/
#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S))
#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET0_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024)
#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x24)
/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget1 high 32 bit*/
/*description: timer taget1 high 32 bit.*/
#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S))
#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET1_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028)
#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x28)
/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget1 low 32 bit*/
/*description: timer taget1 low 32 bit.*/
#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S))
#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET1_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C)
#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x2C)
/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget2 high 32 bit*/
/*description: timer taget2 high 32 bit.*/
#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S))
#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET2_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030)
#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x30)
/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget2 low 32 bit*/
/*description: timer taget2 low 32 bit.*/
#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S))
#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET2_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034)
#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x34)
/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
/*description: select which unit to compare.*/
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target0 to period mode*/
/*description: Set target0 to period mode.*/
#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target0 period*/
/*description: target0 period.*/
#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S))
#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET0_PERIOD_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038)
#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x38)
/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
/*description: select which unit to compare.*/
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target1 to period mode*/
/*description: Set target1 to period mode.*/
#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target1 period*/
/*description: target1 period.*/
#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S))
#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET1_PERIOD_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C)
#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x3C)
/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
/*description: select which unit to compare.*/
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target2 to period mode*/
/*description: Set target2 to period mode.*/
#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target2 period*/
/*description: target2 period.*/
#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S))
#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET2_PERIOD_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040)
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x40)
/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 32bit*/
/*description: timer read value high 32bit.*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S))
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044)
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x44)
/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bit*/
/*description: timer read value low 32bit.*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S))
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048)
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x48)
/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 32bit*/
/*description: timer read value high 32bit.*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S))
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C)
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x4C)
/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bit*/
/*description: timer read value low 32bit.*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S))
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0
#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050)
/* SYS_TIMER_TIMER_COMP0_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp0 load value*/
#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x50)
/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp0 load value.*/
#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP0_LOAD_S 0
#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054)
/* SYS_TIMER_TIMER_COMP1_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp1 load value*/
#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x54)
/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp1 load value.*/
#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP1_LOAD_S 0
#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058)
/* SYS_TIMER_TIMER_COMP2_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp2 load value*/
#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x58)
/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp2 load value.*/
#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP2_LOAD_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C)
/* SYS_TIMER_TIMER_UNIT0_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit0 load value*/
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x5C)
/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit0 load value.*/
#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1
#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060)
/* SYS_TIMER_TIMER_UNIT1_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit1 load value*/
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x60)
/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit1 load value.*/
#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1
#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0
#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064)
/* SYS_TIMER_SYSTIMER_INT2_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 enable*/
#define SYS_TIMER_SYSTIMER_INT2_ENA (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_ENA_M (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_ENA_V 0x1
#define SYS_TIMER_SYSTIMER_INT2_ENA_S 2
/* SYS_TIMER_SYSTIMER_INT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 enable*/
#define SYS_TIMER_SYSTIMER_INT1_ENA (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_ENA_M (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_ENA_V 0x1
#define SYS_TIMER_SYSTIMER_INT1_ENA_S 1
/* SYS_TIMER_SYSTIMER_INT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 enable*/
#define SYS_TIMER_SYSTIMER_INT0_ENA (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_ENA_M (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_ENA_V 0x1
#define SYS_TIMER_SYSTIMER_INT0_ENA_S 0
#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x64)
/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 enable.*/
#define SYS_TIMER_TARGET2_INT_ENA (BIT(2))
#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_ENA_V 0x1
#define SYS_TIMER_TARGET2_INT_ENA_S 2
/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 enable.*/
#define SYS_TIMER_TARGET1_INT_ENA (BIT(1))
#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_ENA_V 0x1
#define SYS_TIMER_TARGET1_INT_ENA_S 1
/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 enable.*/
#define SYS_TIMER_TARGET0_INT_ENA (BIT(0))
#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_ENA_V 0x1
#define SYS_TIMER_TARGET0_INT_ENA_S 0
#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068)
/* SYS_TIMER_SYSTIMER_INT2_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 raw*/
#define SYS_TIMER_SYSTIMER_INT2_RAW (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_RAW_M (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_RAW_V 0x1
#define SYS_TIMER_SYSTIMER_INT2_RAW_S 2
/* SYS_TIMER_SYSTIMER_INT1_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 raw*/
#define SYS_TIMER_SYSTIMER_INT1_RAW (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_RAW_M (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_RAW_V 0x1
#define SYS_TIMER_SYSTIMER_INT1_RAW_S 1
/* SYS_TIMER_SYSTIMER_INT0_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 raw*/
#define SYS_TIMER_SYSTIMER_INT0_RAW (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_RAW_M (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_RAW_V 0x1
#define SYS_TIMER_SYSTIMER_INT0_RAW_S 0
#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x68)
/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 raw.*/
#define SYS_TIMER_TARGET2_INT_RAW (BIT(2))
#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_RAW_V 0x1
#define SYS_TIMER_TARGET2_INT_RAW_S 2
/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 raw.*/
#define SYS_TIMER_TARGET1_INT_RAW (BIT(1))
#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_RAW_V 0x1
#define SYS_TIMER_TARGET1_INT_RAW_S 1
/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 raw.*/
#define SYS_TIMER_TARGET0_INT_RAW (BIT(0))
#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_RAW_V 0x1
#define SYS_TIMER_TARGET0_INT_RAW_S 0
#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c)
/* SYS_TIMER_SYSTIMER_INT2_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 clear*/
#define SYS_TIMER_SYSTIMER_INT2_CLR (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_CLR_M (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_CLR_V 0x1
#define SYS_TIMER_SYSTIMER_INT2_CLR_S 2
/* SYS_TIMER_SYSTIMER_INT1_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 clear*/
#define SYS_TIMER_SYSTIMER_INT1_CLR (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_CLR_M (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_CLR_V 0x1
#define SYS_TIMER_SYSTIMER_INT1_CLR_S 1
/* SYS_TIMER_SYSTIMER_INT0_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 clear*/
#define SYS_TIMER_SYSTIMER_INT0_CLR (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_CLR_M (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_CLR_V 0x1
#define SYS_TIMER_SYSTIMER_INT0_CLR_S 0
#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x6C)
/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 clear.*/
#define SYS_TIMER_TARGET2_INT_CLR (BIT(2))
#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_CLR_V 0x1
#define SYS_TIMER_TARGET2_INT_CLR_S 2
/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 clear.*/
#define SYS_TIMER_TARGET1_INT_CLR (BIT(1))
#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_CLR_V 0x1
#define SYS_TIMER_TARGET1_INT_CLR_S 1
/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 clear.*/
#define SYS_TIMER_TARGET0_INT_CLR (BIT(0))
#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_CLR_V 0x1
#define SYS_TIMER_TARGET0_INT_CLR_S 0
#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070)
/* SYS_TIMER_SYSTIMER_INT2_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_SYSTIMER_INT2_ST (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_ST_M (BIT(2))
#define SYS_TIMER_SYSTIMER_INT2_ST_V 0x1
#define SYS_TIMER_SYSTIMER_INT2_ST_S 2
/* SYS_TIMER_SYSTIMER_INT1_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_SYSTIMER_INT1_ST (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_ST_M (BIT(1))
#define SYS_TIMER_SYSTIMER_INT1_ST_V 0x1
#define SYS_TIMER_SYSTIMER_INT1_ST_S 1
/* SYS_TIMER_SYSTIMER_INT0_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_SYSTIMER_INT0_ST (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_ST_M (BIT(0))
#define SYS_TIMER_SYSTIMER_INT0_ST_V 0x1
#define SYS_TIMER_SYSTIMER_INT0_ST_S 0
#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x70)
/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: .*/
#define SYS_TIMER_TARGET2_INT_ST (BIT(2))
#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_ST_V 0x1
#define SYS_TIMER_TARGET2_INT_ST_S 2
/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define SYS_TIMER_TARGET1_INT_ST (BIT(1))
#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_ST_V 0x1
#define SYS_TIMER_TARGET1_INT_ST_S 1
/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define SYS_TIMER_TARGET0_INT_ST (BIT(0))
#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_ST_V 0x1
#define SYS_TIMER_TARGET0_INT_ST_S 0
#define SYS_TIMER_SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x74)
/* SYS_TIMER_TARGET0_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define SYS_TIMER_TARGET0_LO_RO 0xFFFFFFFF
#define SYS_TIMER_TARGET0_LO_RO_M ((SYS_TIMER_TARGET0_LO_RO_V)<<(SYS_TIMER_TARGET0_LO_RO_S))
#define SYS_TIMER_TARGET0_LO_RO_V 0xFFFFFFFF
#define SYS_TIMER_TARGET0_LO_RO_S 0
#define SYS_TIMER_SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x78)
/* SYS_TIMER_TARGET0_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: .*/
#define SYS_TIMER_TARGET0_HI_RO 0x000FFFFF
#define SYS_TIMER_TARGET0_HI_RO_M ((SYS_TIMER_TARGET0_HI_RO_V)<<(SYS_TIMER_TARGET0_HI_RO_S))
#define SYS_TIMER_TARGET0_HI_RO_V 0xFFFFF
#define SYS_TIMER_TARGET0_HI_RO_S 0
#define SYS_TIMER_SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x7C)
/* SYS_TIMER_TARGET1_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define SYS_TIMER_TARGET1_LO_RO 0xFFFFFFFF
#define SYS_TIMER_TARGET1_LO_RO_M ((SYS_TIMER_TARGET1_LO_RO_V)<<(SYS_TIMER_TARGET1_LO_RO_S))
#define SYS_TIMER_TARGET1_LO_RO_V 0xFFFFFFFF
#define SYS_TIMER_TARGET1_LO_RO_S 0
#define SYS_TIMER_SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x80)
/* SYS_TIMER_TARGET1_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: .*/
#define SYS_TIMER_TARGET1_HI_RO 0x000FFFFF
#define SYS_TIMER_TARGET1_HI_RO_M ((SYS_TIMER_TARGET1_HI_RO_V)<<(SYS_TIMER_TARGET1_HI_RO_S))
#define SYS_TIMER_TARGET1_HI_RO_V 0xFFFFF
#define SYS_TIMER_TARGET1_HI_RO_S 0
#define SYS_TIMER_SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x84)
/* SYS_TIMER_TARGET2_LO_RO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: .*/
#define SYS_TIMER_TARGET2_LO_RO 0xFFFFFFFF
#define SYS_TIMER_TARGET2_LO_RO_M ((SYS_TIMER_TARGET2_LO_RO_V)<<(SYS_TIMER_TARGET2_LO_RO_S))
#define SYS_TIMER_TARGET2_LO_RO_V 0xFFFFFFFF
#define SYS_TIMER_TARGET2_LO_RO_S 0
#define SYS_TIMER_SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x88)
/* SYS_TIMER_TARGET2_HI_RO : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: .*/
#define SYS_TIMER_TARGET2_HI_RO 0x000FFFFF
#define SYS_TIMER_TARGET2_HI_RO_M ((SYS_TIMER_TARGET2_HI_RO_V)<<(SYS_TIMER_TARGET2_HI_RO_S))
#define SYS_TIMER_TARGET2_HI_RO_V 0xFFFFF
#define SYS_TIMER_TARGET2_HI_RO_S 0
#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0xFC)
/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2012251 ; */
/*description: .*/
#define SYS_TIMER_DATE 0xFFFFFFFF
#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S))
#define SYS_TIMER_DATE_V 0xFFFFFFFF
#define SYS_TIMER_DATE_S 0
#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc)
/* SYS_TIMER_SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2003071 ; */
/*description: */
#define SYS_TIMER_SYSTIMER_DATE 0xFFFFFFFF
#define SYS_TIMER_SYSTIMER_DATE_M ((SYS_TIMER_SYSTIMER_DATE_V) << (SYS_TIMER_SYSTIMER_DATE_S))
#define SYS_TIMER_SYSTIMER_DATE_V 0xFFFFFFFF
#define SYS_TIMER_SYSTIMER_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYS_TIMER_REG_H_ */

78
components/soc/esp32s3/include/soc/sys_timer_struct.h
View File

@@ -11,8 +11,8 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SYS_TIMER_STRUCT_H_
#define _SOC_SYS_TIMER_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
@@ -62,7 +62,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_unit0_load_hi;
uint32_t systimer_unit0_load_lo; /*timer unit0 load low 32 bit*/
uint32_t systimer_unit0_load_lo;
union {
struct {
uint32_t timer_unit1_load_hi : 20; /*timer unit1 load high 32 bit*/
@@ -70,7 +70,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_unit1_load_hi;
uint32_t systimer_unit1_load_lo; /*timer unit1 load low 32 bit*/
uint32_t systimer_unit1_load_lo;
union {
struct {
uint32_t timer_target0_hi : 20; /*timer taget0 high 32 bit*/
@@ -78,7 +78,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_target0_hi;
uint32_t systimer_target0_lo; /*timer taget0 low 32 bit*/
uint32_t systimer_target0_lo;
union {
struct {
uint32_t timer_target1_hi : 20; /*timer taget1 high 32 bit*/
@@ -86,7 +86,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_target1_hi;
uint32_t systimer_target1_lo; /*timer taget1 low 32 bit*/
uint32_t systimer_target1_lo;
union {
struct {
uint32_t timer_target2_hi : 20; /*timer taget2 high 32 bit*/
@@ -94,7 +94,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_target2_hi;
uint32_t systimer_target2_lo; /*timer taget2 low 32 bit*/
uint32_t systimer_target2_lo;
union {
struct {
uint32_t target0_period : 26; /*target0 period*/
@@ -129,7 +129,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_unit0_value_hi;
uint32_t systimer_unit0_value_lo; /*timer read value low 32bit*/
uint32_t systimer_unit0_value_lo;
union {
struct {
uint32_t timer_unit1_value_hi : 20; /*timer read value high 32bit*/
@@ -137,7 +137,7 @@ typedef volatile struct {
};
uint32_t val;
} systimer_unit1_value_hi;
uint32_t systimer_unit1_value_lo; /*timer read value low 32bit*/
uint32_t systimer_unit1_value_lo;
union {
struct {
uint32_t timer_comp0_load : 1; /*timer comp0 load value*/
@@ -175,46 +175,64 @@ typedef volatile struct {
} systimer_unit1_load;
union {
struct {
uint32_t systimer_int0_ena: 1; /*interupt0 enable*/
uint32_t systimer_int1_ena: 1; /*interupt1 enable*/
uint32_t systimer_int2_ena: 1; /*interupt2 enable*/
uint32_t target0 : 1; /*interupt0 enable*/
uint32_t target1 : 1; /*interupt1 enable*/
uint32_t target2 : 1; /*interupt2 enable*/
uint32_t reserved3 : 29;
};
uint32_t val;
} systimer_int_ena;
union {
struct {
uint32_t systimer_int0_raw: 1; /*interupt0 raw*/
uint32_t systimer_int1_raw: 1; /*interupt1 raw*/
uint32_t systimer_int2_raw: 1; /*interupt2 raw*/
uint32_t target0 : 1; /*interupt0 raw*/
uint32_t target1 : 1; /*interupt1 raw*/
uint32_t target2 : 1; /*interupt2 raw*/
uint32_t reserved3 : 29;
};
uint32_t val;
} systimer_int_raw;
union {
struct {
uint32_t systimer_int0_clr: 1; /*interupt0 clear*/
uint32_t systimer_int1_clr: 1; /*interupt1 clear*/
uint32_t systimer_int2_clr: 1; /*interupt2 clear*/
uint32_t target0 : 1; /*interupt0 clear*/
uint32_t target1 : 1; /*interupt1 clear*/
uint32_t target2 : 1; /*interupt2 clear*/
uint32_t reserved3 : 29;
};
uint32_t val;
} systimer_int_clr;
union {
struct {
uint32_t systimer_int0_st: 1;
uint32_t systimer_int1_st: 1;
uint32_t systimer_int2_st: 1;
uint32_t target0 : 1;
uint32_t target1 : 1;
uint32_t target2 : 1;
uint32_t reserved3 : 29;
};
uint32_t val;
} systimer_int_st;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t systimer_real_target0_lo;
union {
struct {
uint32_t target0_hi_ro : 20;
uint32_t reserved20 : 12;
};
uint32_t val;
} systimer_real_target0_hi;
uint32_t systimer_real_target1_lo;
union {
struct {
uint32_t target1_hi_ro : 20;
uint32_t reserved20 : 12;
};
uint32_t val;
} systimer_real_target1_hi;
uint32_t systimer_real_target2_lo;
union {
struct {
uint32_t target2_hi_ro : 20;
uint32_t reserved20 : 12;
};
uint32_t val;
} systimer_real_target2_hi;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
@@ -243,11 +261,11 @@ typedef volatile struct {
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t systimer_date; /**/
uint32_t systimer_date;
} sys_timer_dev_t;
extern sys_timer_dev_t SYS_TIMER;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SYS_TIMER_STRUCT_H_ */

298
components/soc/esp32s3/include/soc/syscon_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,21 +11,16 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SYSCON_REG_H_
#define _SOC_SYSCON_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
/*description: */
#define SYSCON_SOC_CLK_SEL 0x00000003
#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V) << (SYSCON_SOC_CLK_SEL_S))
#define SYSCON_SOC_CLK_SEL_V 0x3
#define SYSCON_SOC_CLK_SEL_S 14
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RST_TICK_CNT (BIT(12))
@@ -174,24 +169,24 @@ extern "C" {
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN 0xFFFFFFFF
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S))
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSTEM_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
Bit15 not included here because of the bit now can't be cleared */
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN 0x003807cf
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V) << (SYSTEM_WIFI_CLK_WIFI_EN_S))
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x7cf
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define SYSTEM_WIFI_CLK_BT_EN 0x0
#define SYSTEM_WIFI_CLK_BT_EN 0x61
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V) << (SYSTEM_WIFI_CLK_BT_EN_S))
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
#define SYSTEM_WIFI_CLK_BT_EN_S 0
#define SYSTEM_WIFI_CLK_BT_EN_V 0x61
#define SYSTEM_WIFI_CLK_BT_EN_S 11
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
/* Digital team to check */
//bluetooth baseband bit11
@@ -244,39 +239,48 @@ extern "C" {
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x024)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x024)
/* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set 1 to bypass cache writeback request to external memory so
that spi will not check its attribute.*/
#define SYSCON_WRITEBACK_BYPASS (BIT(0))
#define SYSCON_WRITEBACK_BYPASS_M (BIT(0))
#define SYSCON_WRITEBACK_BYPASS_V 0x1
#define SYSCON_WRITEBACK_BYPASS_S 0
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE0_ATTR 0x000000FF
#define SYSCON_FLASH_ACE0_ATTR 0x000001FF
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
#define SYSCON_FLASH_ACE0_ATTR_V 0xFF
#define SYSCON_FLASH_ACE0_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE0_ATTR_S 0
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C)
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE1_ATTR 0x000000FF
#define SYSCON_FLASH_ACE1_ATTR 0x000001FF
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
#define SYSCON_FLASH_ACE1_ATTR_V 0xFF
#define SYSCON_FLASH_ACE1_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE1_ATTR_S 0
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030)
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE2_ATTR 0x000000FF
#define SYSCON_FLASH_ACE2_ATTR 0x000001FF
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
#define SYSCON_FLASH_ACE2_ATTR_V 0xFF
#define SYSCON_FLASH_ACE2_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE2_ATTR_S 0
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x030)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034)
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_FLASH_ACE3_ATTR 0x000000FF
#define SYSCON_FLASH_ACE3_ATTR 0x000001FF
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
#define SYSCON_FLASH_ACE3_ATTR_V 0xFF
#define SYSCON_FLASH_ACE3_ATTR_V 0x1FF
#define SYSCON_FLASH_ACE3_ATTR_S 0
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x034)
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038)
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
@@ -284,7 +288,7 @@ extern "C" {
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x038)
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C)
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
@@ -292,7 +296,7 @@ extern "C" {
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C)
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040)
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
@@ -300,7 +304,7 @@ extern "C" {
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x040)
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044)
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
@@ -308,7 +312,7 @@ extern "C" {
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x044)
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048)
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
@@ -316,7 +320,7 @@ extern "C" {
#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE0_SIZE_S 0
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x048)
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C)
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
@@ -324,7 +328,7 @@ extern "C" {
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE1_SIZE_S 0
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C)
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050)
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
@@ -332,7 +336,7 @@ extern "C" {
#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE2_SIZE_S 0
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x050)
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054)
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
@@ -340,39 +344,39 @@ extern "C" {
#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF
#define SYSCON_FLASH_ACE3_SIZE_S 0
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x054)
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x058)
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE0_ATTR 0x000000FF
#define SYSCON_SRAM_ACE0_ATTR 0x000001FF
#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
#define SYSCON_SRAM_ACE0_ATTR_V 0xFF
#define SYSCON_SRAM_ACE0_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE0_ATTR_S 0
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x058)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C)
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE1_ATTR 0x000000FF
#define SYSCON_SRAM_ACE1_ATTR 0x000001FF
#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
#define SYSCON_SRAM_ACE1_ATTR_V 0xFF
#define SYSCON_SRAM_ACE1_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE1_ATTR_S 0
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C)
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x060)
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE2_ATTR 0x000000FF
#define SYSCON_SRAM_ACE2_ATTR 0x000001FF
#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
#define SYSCON_SRAM_ACE2_ATTR_V 0xFF
#define SYSCON_SRAM_ACE2_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE2_ATTR_S 0
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x060)
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x064)
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
/*description: */
#define SYSCON_SRAM_ACE3_ATTR 0x000000FF
#define SYSCON_SRAM_ACE3_ATTR 0x000001FF
#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
#define SYSCON_SRAM_ACE3_ATTR_V 0xFF
#define SYSCON_SRAM_ACE3_ATTR_V 0x1FF
#define SYSCON_SRAM_ACE3_ATTR_S 0
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x064)
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x068)
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
@@ -380,7 +384,7 @@ extern "C" {
#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE0_ADDR_S_S 0
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x068)
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C)
/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
@@ -388,7 +392,7 @@ extern "C" {
#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE1_ADDR_S_S 0
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C)
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x070)
/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
@@ -396,7 +400,7 @@ extern "C" {
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x070)
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x074)
/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
@@ -404,7 +408,7 @@ extern "C" {
#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
#define SYSCON_SRAM_ACE3_ADDR_S_S 0
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x074)
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x078)
/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
@@ -412,7 +416,7 @@ extern "C" {
#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE0_SIZE_S 0
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x078)
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C)
/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
@@ -420,7 +424,7 @@ extern "C" {
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE1_SIZE_S 0
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C)
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x080)
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
@@ -428,7 +432,7 @@ extern "C" {
#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE2_SIZE_S 0
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x080)
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x084)
/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
/*description: */
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
@@ -436,7 +440,7 @@ extern "C" {
#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF
#define SYSCON_SRAM_ACE3_SIZE_S 0
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x084)
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088)
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
/*description: */
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
@@ -456,7 +460,7 @@ extern "C" {
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
#define SYSCON_SPI_MEM_REJECT_INT_S 0
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x088)
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C)
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
@@ -464,7 +468,7 @@ extern "C" {
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x08C)
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090)
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
@@ -472,7 +476,7 @@ extern "C" {
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x090)
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094)
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_ANDOR (BIT(31))
@@ -486,7 +490,7 @@ extern "C" {
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG0_S 0
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x094)
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098)
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSCON_REDCY_NANDOR (BIT(31))
@@ -500,7 +504,19 @@ extern "C" {
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
#define SYSCON_REDCY_SIG1_S 0
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098)
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C)
/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define SYSCON_FREQ_MEM_FORCE_PD (BIT(7))
#define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7))
#define SYSCON_FREQ_MEM_FORCE_PD_V 0x1
#define SYSCON_FREQ_MEM_FORCE_PD_S 7
/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_FREQ_MEM_FORCE_PU (BIT(6))
#define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6))
#define SYSCON_FREQ_MEM_FORCE_PU_V 0x1
#define SYSCON_FREQ_MEM_FORCE_PU_S 6
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
@@ -538,9 +554,141 @@ extern "C" {
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
#define SYSCON_AGC_MEM_FORCE_PU_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907100 ; */
#define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0)
/* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes.
1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
#define SYSCON_SRAM_PAGE_SIZE 0x00000003
#define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S))
#define SYSCON_SRAM_PAGE_SIZE_V 0x3
#define SYSCON_SRAM_PAGE_SIZE_S 20
/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512
bytes. 2: 1024 bytes. 3: 2048 bytes.*/
#define SYSCON_FLASH_PAGE_SIZE 0x00000003
#define SYSCON_FLASH_PAGE_SIZE_M ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S))
#define SYSCON_FLASH_PAGE_SIZE_V 0x3
#define SYSCON_FLASH_PAGE_SIZE_S 18
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A8)
/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
/*description: */
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x7FF
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3
/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: */
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007
#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0AC)
/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
/*description: */
#define SYSCON_SRAM_POWER_DOWN 0x000007FF
#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
#define SYSCON_SRAM_POWER_DOWN_V 0x7FF
#define SYSCON_SRAM_POWER_DOWN_S 3
/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: */
#define SYSCON_ROM_POWER_DOWN 0x00000007
#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
#define SYSCON_ROM_POWER_DOWN_V 0x7
#define SYSCON_ROM_POWER_DOWN_S 0
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0B0)
/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
/*description: */
#define SYSCON_SRAM_POWER_UP 0x000007FF
#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
#define SYSCON_SRAM_POWER_UP_V 0x7FF
#define SYSCON_SRAM_POWER_UP_S 3
/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
/*description: */
#define SYSCON_ROM_POWER_UP 0x00000007
#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
#define SYSCON_ROM_POWER_UP_V 0x7
#define SYSCON_ROM_POWER_UP_S 0
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0B4)
/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
/* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: */
#define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_CPU_LINK_ADDR_M ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S))
#define SYSCON_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_CPU_LINK_ADDR_S 0
#define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0x0B8)
/* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: */
#define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S))
#define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_TAG_LINK_ADDR_S 0
#define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0x0BC)
/* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RET_ICACHE_ENABLE (BIT(31))
#define SYSCON_RET_ICACHE_ENABLE_M (BIT(31))
#define SYSCON_RET_ICACHE_ENABLE_V 0x1
#define SYSCON_RET_ICACHE_ENABLE_S 31
/* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
/*description: */
#define SYSCON_RET_ICACHE_START_POINT 0x000000FF
#define SYSCON_RET_ICACHE_START_POINT_M ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S))
#define SYSCON_RET_ICACHE_START_POINT_V 0xFF
#define SYSCON_RET_ICACHE_START_POINT_S 22
/* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
/*description: */
#define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF
#define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S))
#define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF
#define SYSCON_RET_ICACHE_VLD_SIZE_S 13
/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
/*description: */
#define SYSCON_RET_ICACHE_SIZE 0x000000FF
#define SYSCON_RET_ICACHE_SIZE_M ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S))
#define SYSCON_RET_ICACHE_SIZE_V 0xFF
#define SYSCON_RET_ICACHE_SIZE_S 4
#define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0x0C0)
/* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RET_DCACHE_ENABLE (BIT(31))
#define SYSCON_RET_DCACHE_ENABLE_M (BIT(31))
#define SYSCON_RET_DCACHE_ENABLE_V 0x1
#define SYSCON_RET_DCACHE_ENABLE_S 31
/* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
/*description: */
#define SYSCON_RET_DCACHE_START_POINT 0x000001FF
#define SYSCON_RET_DCACHE_START_POINT_M ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S))
#define SYSCON_RET_DCACHE_START_POINT_V 0x1FF
#define SYSCON_RET_DCACHE_START_POINT_S 22
/* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
/*description: */
#define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF
#define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S))
#define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF
#define SYSCON_RET_DCACHE_VLD_SIZE_S 13
/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
/*description: */
#define SYSCON_RET_DCACHE_SIZE 0x000001FF
#define SYSCON_RET_DCACHE_SIZE_M ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S))
#define SYSCON_RET_DCACHE_SIZE_V 0x1FF
#define SYSCON_RET_DCACHE_SIZE_S 4
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h21010400 ; */
/*description: Version control*/
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
#define SYSCON_DATE_V 0xFFFFFFFF
@@ -549,3 +697,7 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSCON_REG_H_ */

163
components/soc/esp32s3/include/soc/syscon_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,32 +11,28 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SYSCON_STRUCT_H_
#define _SOC_SYSCON_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t pre_div: 10;
uint32_t clk_320m_en: 1;
uint32_t apb_ctrl_pre_div_cnt: 10;
uint32_t apb_ctrl_clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick: 1;
uint32_t reserved13: 1;
uint32_t soc_clk_sel: 2;
uint32_t reserved16: 16;
uint32_t apb_ctrl_rst_tick_cnt: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
union {
struct {
uint32_t xtal_tick: 8;
uint32_t ck8m_tick: 8;
uint32_t tick_enable: 1;
uint32_t apb_ctrl_xtal_tick_num: 8;
uint32_t apb_ctrl_ck8m_tick_num: 8;
uint32_t apb_ctrl_tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
@@ -58,6 +54,10 @@ typedef volatile struct {
};
uint32_t val;
} apb_ctrl_clk_out_en;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
union {
struct {
uint32_t peri_io_swap: 8;
@@ -74,29 +74,36 @@ typedef volatile struct {
} ext_mem_pms_lock;
union {
struct {
uint32_t flash_ace0_attr: 3;
uint32_t reserved3: 29;
uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
uint32_t reserved1: 31;
};
uint32_t val;
} ext_mem_writeback_bypass;
union {
struct {
uint32_t flash_ace0_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} flash_ace0_attr;
union {
struct {
uint32_t flash_ace1_attr: 3;
uint32_t reserved3: 29;
uint32_t flash_ace1_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} flash_ace1_attr;
union {
struct {
uint32_t flash_ace2_attr: 3;
uint32_t reserved3: 29;
uint32_t flash_ace2_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} flash_ace2_attr;
union {
struct {
uint32_t flash_ace3_attr: 3;
uint32_t reserved3: 29;
uint32_t flash_ace3_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} flash_ace3_attr;
@@ -134,29 +141,29 @@ typedef volatile struct {
} flash_ace3_size;
union {
struct {
uint32_t sram_ace0_attr: 3;
uint32_t reserved3: 29;
uint32_t sram_ace0_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} sram_ace0_attr;
union {
struct {
uint32_t sram_ace1_attr: 3;
uint32_t reserved3: 29;
uint32_t sram_ace1_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} sram_ace1_attr;
union {
struct {
uint32_t sram_ace2_attr: 3;
uint32_t reserved3: 29;
uint32_t sram_ace2_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} sram_ace2_attr;
union {
struct {
uint32_t sram_ace3_attr: 3;
uint32_t reserved3: 29;
uint32_t sram_ace3_attr: 9;
uint32_t reserved9: 23;
};
uint32_t val;
} sram_ace3_attr;
@@ -208,7 +215,7 @@ typedef volatile struct {
uint32_t reserved1: 31;
};
uint32_t val;
} sdio_ctrl;
} apb_ctrl_sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
@@ -223,10 +230,6 @@ typedef volatile struct {
};
uint32_t val;
} redcy_sig1;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
union {
struct {
uint32_t agc_mem_force_pu: 1;
@@ -235,20 +238,84 @@ typedef volatile struct {
uint32_t pbus_mem_force_pd: 1;
uint32_t dc_mem_force_pu: 1;
uint32_t dc_mem_force_pd: 1;
uint32_t reserved6: 26;
uint32_t freq_mem_force_pu: 1;
uint32_t freq_mem_force_pd: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} front_end_mem_pd;
uint32_t reserved_9c;
uint32_t reserved_a0;
union {
struct {
uint32_t reserved0: 18; /*reserved*/
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
uint32_t reserved22: 10; /*reserved*/
};
uint32_t val;
} spi_mem_ecc_ctrl;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
union {
struct {
uint32_t rom_clkgate_force_on: 3;
uint32_t sram_clkgate_force_on:11;
uint32_t reserved14: 18;
};
uint32_t val;
} clkgate_force_on;
union {
struct {
uint32_t rom_power_down: 3;
uint32_t sram_power_down:11;
uint32_t reserved14: 18;
};
uint32_t val;
} mem_power_down;
union {
struct {
uint32_t rom_power_up: 3;
uint32_t sram_power_up:11;
uint32_t reserved14: 18;
};
uint32_t val;
} mem_power_up;
union {
struct {
uint32_t retention_cpu_link_addr:27;
uint32_t nobypass_cpu_iso_rst: 1;
uint32_t reserved28: 4;
};
uint32_t val;
} retention_ctrl;
union {
struct {
uint32_t retention_tag_link_addr:27;
uint32_t reserved27: 5;
};
uint32_t val;
} retention_ctrl1;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_icache_size: 8;
uint32_t reserved12: 1;
uint32_t ret_icache_vld_size: 8;
uint32_t reserved21: 1;
uint32_t ret_icache_start_point: 8;
uint32_t reserved30: 1;
uint32_t ret_icache_enable: 1;
};
uint32_t val;
} retention_ctrl2;
union {
struct {
uint32_t reserved0: 4;
uint32_t ret_dcache_size: 9;
uint32_t ret_dcache_vld_size: 9;
uint32_t ret_dcache_start_point: 9;
uint32_t ret_dcache_enable: 1;
};
uint32_t val;
} retention_ctrl3;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
@@ -455,11 +522,11 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date; /**/
uint32_t apb_ctrl_date; /*Version control*/
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_SYSCON_STRUCT_H_ */

651
components/soc/esp32s3/include/soc/system_reg.h
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220
components/soc/esp32s3/include/soc/system_struct.h
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@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,54 +11,16 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_SYSTEM_STRUCT_H_
#define _SOC_SYSTEM_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t rom_iram0_clkgate_force_on: 2;
uint32_t rom_iram0_dram0_clkgate_force_on: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} rom_ctrl_0;
union {
struct {
uint32_t rom_iram0_power_down: 2;
uint32_t rom_iram0_power_up: 2;
uint32_t rom_iram0_dram0_power_down: 1;
uint32_t rom_iram0_dram0_power_up: 1;
uint32_t reserved6: 26;
};
uint32_t val;
} rom_ctrl_1;
union {
struct {
uint32_t sram_clkgate_force_on: 11;
uint32_t reserved11: 21;
};
uint32_t val;
} sram_ctrl_0;
union {
struct {
uint32_t sram_power_down: 11;
uint32_t reserved11: 21;
};
uint32_t val;
} sram_ctrl_1;
union {
struct {
uint32_t sram_power_up: 11;
uint32_t reserved11: 21;
};
uint32_t val;
} sram_ctrl_2;
union {
struct {
uint32_t control_core_1_runstall : 1;
@@ -68,7 +30,7 @@ typedef volatile struct {
};
uint32_t val;
} core_1_control_0;
uint32_t core_1_control_1; /**/
uint32_t core_1_control_1;
union {
struct {
uint32_t reserved0 : 6;
@@ -97,14 +59,14 @@ typedef volatile struct {
};
uint32_t val;
} cpu_per_conf;
uint32_t jtag_ctrl_0; /**/
uint32_t jtag_ctrl_1; /**/
uint32_t jtag_ctrl_2; /**/
uint32_t jtag_ctrl_3; /**/
uint32_t jtag_ctrl_4; /**/
uint32_t jtag_ctrl_5; /**/
uint32_t jtag_ctrl_6; /**/
uint32_t jtag_ctrl_7; /**/
uint32_t jtag_ctrl_0;
uint32_t jtag_ctrl_1;
uint32_t jtag_ctrl_2;
uint32_t jtag_ctrl_3;
uint32_t jtag_ctrl_4;
uint32_t jtag_ctrl_5;
uint32_t jtag_ctrl_6;
uint32_t jtag_ctrl_7;
union {
struct {
uint32_t lslp_mem_pd_mask : 1;
@@ -151,7 +113,7 @@ typedef volatile struct {
} perip_clk_en0;
union {
struct {
uint32_t reserved0: 1;
uint32_t peri_backup_clk_en : 1;
uint32_t crypto_aes_clk_en : 1;
uint32_t crypto_sha_clk_en : 1;
uint32_t crypto_rsa_clk_en : 1;
@@ -161,7 +123,8 @@ typedef volatile struct {
uint32_t sdio_host_clk_en : 1;
uint32_t lcd_cam_clk_en : 1;
uint32_t uart2_clk_en : 1;
uint32_t reserved10: 22;
uint32_t usb_device_clk_en : 1;
uint32_t reserved11 : 21;
};
uint32_t val;
} perip_clk_en1;
@@ -204,7 +167,7 @@ typedef volatile struct {
} perip_rst_en0;
union {
struct {
uint32_t reserved0: 1;
uint32_t peri_backup_rst : 1;
uint32_t crypto_aes_rst : 1;
uint32_t crypto_sha_rst : 1;
uint32_t crypto_rsa_rst : 1;
@@ -214,7 +177,8 @@ typedef volatile struct {
uint32_t sdio_host_rst : 1;
uint32_t lcd_cam_rst : 1;
uint32_t uart2_rst : 1;
uint32_t reserved10: 22;
uint32_t usb_device_rst : 1;
uint32_t reserved11 : 21;
};
uint32_t val;
} perip_rst_en1;
@@ -313,7 +277,7 @@ typedef volatile struct {
};
uint32_t val;
} rtc_fastmem_config;
uint32_t rtc_fastmem_crc; /**/
uint32_t rtc_fastmem_crc;
union {
struct {
uint32_t redundant_eco_drive : 1;
@@ -345,29 +309,125 @@ typedef volatile struct {
uint32_t mem_err_cnt_clr : 1;
uint32_t mem_pvt_monitor_en : 1;
uint32_t mem_timing_err_cnt : 16;
uint32_t reserved22: 10;
uint32_t mem_vt_sel : 2;
uint32_t reserved24 : 8;
};
uint32_t val;
} mem_pvt;
union {
struct {
uint32_t comb_path_len: 5;
uint32_t comb_err_cnt_clr: 1;
uint32_t comb_pvt_monitor_en: 1;
uint32_t comb_timing_err_cnt: 16;
uint32_t reserved23: 9;
uint32_t comb_path_len_lvt : 5;
uint32_t comb_err_cnt_clr_lvt : 1;
uint32_t comb_pvt_monitor_en_lvt : 1;
uint32_t reserved7 : 18;
uint32_t reserved25 : 7;
};
uint32_t val;
} comb_pvt;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
} comb_pvt_lvt_conf;
union {
struct {
uint32_t comb_path_len_nvt : 5;
uint32_t comb_err_cnt_clr_nvt : 1;
uint32_t comb_pvt_monitor_en_nvt : 1;
uint32_t reserved7 : 18;
uint32_t reserved25 : 7;
};
uint32_t val;
} comb_pvt_nvt_conf;
union {
struct {
uint32_t comb_path_len_hvt : 5;
uint32_t comb_err_cnt_clr_hvt : 1;
uint32_t comb_pvt_monitor_en_hvt : 1;
uint32_t reserved7 : 18;
uint32_t reserved25 : 7;
};
uint32_t val;
} comb_pvt_hvt_conf;
union {
struct {
uint32_t comb_timing_err_cnt_lvt_site0 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_lvt_site0;
union {
struct {
uint32_t comb_timing_err_cnt_nvt_site0 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_nvt_site0;
union {
struct {
uint32_t comb_timing_err_cnt_hvt_site0 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_hvt_site0;
union {
struct {
uint32_t comb_timing_err_cnt_lvt_site1 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_lvt_site1;
union {
struct {
uint32_t comb_timing_err_cnt_nvt_site1 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_nvt_site1;
union {
struct {
uint32_t comb_timing_err_cnt_hvt_site1 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_hvt_site1;
union {
struct {
uint32_t comb_timing_err_cnt_lvt_site2 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_lvt_site2;
union {
struct {
uint32_t comb_timing_err_cnt_nvt_site2 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_nvt_site2;
union {
struct {
uint32_t comb_timing_err_cnt_hvt_site2 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_hvt_site2;
union {
struct {
uint32_t comb_timing_err_cnt_lvt_site3 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_lvt_site3;
union {
struct {
uint32_t comb_timing_err_cnt_nvt_site3 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_nvt_site3;
union {
struct {
uint32_t comb_timing_err_cnt_hvt_site3 : 16;
uint32_t reserved16 : 16;
};
uint32_t val;
} comb_pvt_err_hvt_site3;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
@@ -383,13 +443,7 @@ typedef volatile struct {
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t reserved_fc;
union {
struct {
uint32_t retention_link_addr: 27;
uint32_t reserved27: 5;
};
uint32_t val;
} retention_bus_ctrl;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
@@ -1356,9 +1410,11 @@ typedef volatile struct {
uint32_t val;
} date;
} system_dev_t;
extern system_dev_t SYSTEM;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYSTEM_STRUCT_H_ */

17
components/soc/esp32s3/include/soc/timer_group_caps.h Normal file
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@@ -0,0 +1,17 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_TIMER_GROUP_SUPPORT_XTAL

217
components/soc/esp32s3/include/soc/timer_group_reg.h
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@@ -11,7 +11,9 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_TIMG_REG_H_
#define _SOC_TIMG_REG_H_
#ifdef __cplusplus
extern "C" {
@@ -38,490 +40,495 @@ extern "C" {
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
/*description: .*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
/*description: .*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
/*description: .*/
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (BIT(9))
#define TIMG_T0_USE_XTAL_V 0x1
#define TIMG_T0_USE_XTAL_S 9
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_HI 0x003FFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0x3FFFFF
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xC)
/* TIMG_T0_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (BIT(31))
#define TIMG_T0_UPDATE_V 0x1
#define TIMG_T0_UPDATE_S 31
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_ALARM_HI 0x003FFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0x3FFFFF
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1C)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_LOAD_HI 0x003FFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0x3FFFFF
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
#define TIMG_T0_LOAD_S 0
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024)
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (BIT(31))
#define TIMG_T1_EN_V 0x1
#define TIMG_T1_EN_S 31
/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
/*description: .*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (BIT(30))
#define TIMG_T1_INCREASE_V 0x1
#define TIMG_T1_INCREASE_S 30
/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
/*description: .*/
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (BIT(29))
#define TIMG_T1_AUTORELOAD_V 0x1
#define TIMG_T1_AUTORELOAD_S 29
/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
/*description: .*/
#define TIMG_T1_DIVIDER 0x0000FFFF
#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
#define TIMG_T1_DIVIDER_V 0xFFFF
#define TIMG_T1_DIVIDER_S 13
/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (BIT(10))
#define TIMG_T1_ALARM_EN_V 0x1
#define TIMG_T1_ALARM_EN_S 10
/* TIMG_T1_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_USE_XTAL (BIT(9))
#define TIMG_T1_USE_XTAL_M (BIT(9))
#define TIMG_T1_USE_XTAL_V 0x1
#define TIMG_T1_USE_XTAL_S 9
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028)
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_LO 0xFFFFFFFF
#define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
#define TIMG_T1_LO_V 0xFFFFFFFF
#define TIMG_T1_LO_S 0
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c)
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2C)
/* TIMG_T1_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_HI 0x003FFFFF
#define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
#define TIMG_T1_HI_V 0x3FFFFF
#define TIMG_T1_HI_S 0
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030)
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
/* TIMG_T1_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_UPDATE (BIT(31))
#define TIMG_T1_UPDATE_M (BIT(31))
#define TIMG_T1_UPDATE_V 0x1
#define TIMG_T1_UPDATE_S 31
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034)
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_ALARM_LO 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF
#define TIMG_T1_ALARM_LO_S 0
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038)
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
/* TIMG_T1_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_ALARM_HI 0x003FFFFF
#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
#define TIMG_T1_ALARM_HI_V 0x3FFFFF
#define TIMG_T1_ALARM_HI_S 0
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c)
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3C)
/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_LOAD_LO 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF
#define TIMG_T1_LOAD_LO_S 0
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040)
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
/* TIMG_T1_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_LOAD_HI 0x003FFFFF
#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
#define TIMG_T1_LOAD_HI_V 0x3FFFFF
#define TIMG_T1_LOAD_HI_S 0
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044)
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_LOAD 0xFFFFFFFF
#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
#define TIMG_T1_LOAD_V 0xFFFFFFFF
#define TIMG_T1_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_V 0x1
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_V 0x1
#define TIMG_WDT_APPCPU_RESET_EN_S 12
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4C)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5C)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
/*description: .*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
#define TIMG_RTC_CALI_START_CYCLING_S 12
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6C)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070)
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_INT_ENA (BIT(2))
#define TIMG_WDT_INT_ENA_M (BIT(2))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 2
/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (BIT(1))
#define TIMG_T1_INT_ENA_V 0x1
#define TIMG_T1_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
#define TIMG_T0_INT_ENA_S 0
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074)
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_INT_RAW (BIT(2))
#define TIMG_WDT_INT_RAW_M (BIT(2))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 2
/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (BIT(1))
#define TIMG_T1_INT_RAW_V 0x1
#define TIMG_T1_INT_RAW_S 1
/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
#define TIMG_T0_INT_RAW_S 0
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078)
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_INT_ST (BIT(2))
#define TIMG_WDT_INT_ST_M (BIT(2))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 2
/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (BIT(1))
#define TIMG_T1_INT_ST_V 0x1
#define TIMG_T1_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
#define TIMG_T0_INT_ST_S 0
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c)
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7C)
/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_WDT_INT_CLR (BIT(2))
#define TIMG_WDT_INT_CLR_M (BIT(2))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 2
/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (BIT(1))
#define TIMG_T1_INT_CLR_V 0x1
#define TIMG_T1_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
#define TIMG_T0_INT_CLR_S 0
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080)
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
/*description: timeout if cali value counts over threshold*/
/*description: timeout if cali value counts over threshold.*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
/*description: Cycles that release calibration timeout reset*/
/*description: Cycles that release calibration timeout reset.*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: timeout indicator*/
/*description: timeout indicator.*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_V 0x1
#define TIMG_RTC_CALI_TIMEOUT_S 0
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xF8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003071 ; */
/*description: */
/*description: .*/
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xFC)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif
#endif /*_SOC_TIMG_REG_H_ */

30
components/soc/esp32s3/include/soc/timer_group_struct.h
View File

@@ -11,8 +11,8 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
@@ -35,7 +35,7 @@ typedef volatile struct {
};
uint32_t val;
} config;
uint32_t cnt_low; /**/
uint32_t cnt_low;
union {
struct {
uint32_t hi : 22;
@@ -50,7 +50,7 @@ typedef volatile struct {
};
uint32_t val;
} update;
uint32_t alarm_low; /**/
uint32_t alarm_low;
union {
struct {
uint32_t alarm_hi : 22;
@@ -58,7 +58,7 @@ typedef volatile struct {
};
uint32_t val;
} alarm_high;
uint32_t load_low; /**/
uint32_t load_low;
union {
struct {
uint32_t load_hi : 22;
@@ -66,7 +66,7 @@ typedef volatile struct {
};
uint32_t val;
} load_high;
uint32_t reload; /**/
uint32_t reload;
} hw_timer[2];
union {
struct {
@@ -93,12 +93,12 @@ typedef volatile struct {
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
uint32_t wdt_config5; /**/
uint32_t wdt_feed; /**/
uint32_t wdt_wprotect; /**/
uint32_t wdt_config2;
uint32_t wdt_config3;
uint32_t wdt_config4;
uint32_t wdt_config5;
uint32_t wdt_feed;
uint32_t wdt_wprotect;
union {
struct {
uint32_t reserved0 : 12;
@@ -202,15 +202,15 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0 : 31;
uint32_t en: 1;
uint32_t clk_en : 1;
};
uint32_t val;
} clk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_TIMG_STRUCT_H_ */

4
components/soc/esp32s3/include/soc/twai_struct.h
View File

@@ -22,7 +22,7 @@ extern "C" {
/* ---------------------------- Register Layout ------------------------------ */
/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access
/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access
* peripheral registers every 32bits. Therefore each TWAI register is mapped to
* the least significant byte of every 32bits.
*/
@@ -61,7 +61,7 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved24: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */

568
components/soc/esp32s3/include/soc/uart_reg.h
View File

File diff suppressed because it is too large Load Diff

433
components/soc/esp32s3/include/soc/uart_struct.h
View File

@@ -11,392 +11,401 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_UART_STRUCT_H_
#define _SOC_UART_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
typedef volatile struct {
union {
struct {
uint32_t rw_byte;
uint32_t rw_byte; /*UART $n accesses FIFO via this register.*/
};
uint32_t val;
} ahb_fifo;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
uint32_t rxfifo_full : 1; /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
uint32_t txfifo_empty : 1; /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
uint32_t parity_err : 1; /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
uint32_t frm_err : 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
uint32_t rxfifo_ovf : 1; /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
uint32_t dsr_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
uint32_t cts_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
uint32_t brk_det : 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
uint32_t rxfifo_tout : 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
uint32_t sw_xoff : 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
uint32_t glitch_det : 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
uint32_t tx_brk_done : 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.*/
uint32_t tx_brk_idle_done : 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.*/
uint32_t tx_done : 1; /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
uint32_t rs485_parity_err : 1; /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
uint32_t rs485_frm_err : 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
uint32_t rs485_clash : 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
uint32_t at_cmd_char_det : 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
uint32_t wakeup : 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
uint32_t rxfifo_full : 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
uint32_t txfifo_empty : 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
uint32_t parity_err : 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
uint32_t frm_err : 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
uint32_t rxfifo_ovf : 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg : 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg : 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
uint32_t brk_det : 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
uint32_t rxfifo_tout : 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
uint32_t sw_xon : 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
uint32_t sw_xoff : 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
uint32_t glitch_det : 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
uint32_t tx_brk_done : 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done : 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint32_t tx_done : 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
uint32_t rs485_parity_err : 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
uint32_t rs485_frm_err : 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
uint32_t rs485_clash : 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
uint32_t at_cmd_char_det : 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
uint32_t wakeup : 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
uint32_t rxfifo_full : 1; /*This is the enable bit for rxfifo_full_int_st register.*/
uint32_t txfifo_empty : 1; /*This is the enable bit for txfifo_empty_int_st register.*/
uint32_t parity_err : 1; /*This is the enable bit for parity_err_int_st register.*/
uint32_t frm_err : 1; /*This is the enable bit for frm_err_int_st register.*/
uint32_t rxfifo_ovf : 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
uint32_t dsr_chg : 1; /*This is the enable bit for dsr_chg_int_st register.*/
uint32_t cts_chg : 1; /*This is the enable bit for cts_chg_int_st register.*/
uint32_t brk_det : 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout : 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon : 1; /*This is the enable bit for sw_xon_int_st register.*/
uint32_t sw_xoff : 1; /*This is the enable bit for sw_xoff_int_st register.*/
uint32_t glitch_det : 1; /*This is the enable bit for glitch_det_int_st register.*/
uint32_t tx_brk_done : 1; /*This is the enable bit for tx_brk_done_int_st register.*/
uint32_t tx_brk_idle_done : 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
uint32_t tx_done : 1; /*This is the enable bit for tx_done_int_st register.*/
uint32_t rs485_parity_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_frm_err : 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash : 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det : 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
uint32_t wakeup : 1; /*This is the enable bit for uart_wakeup_int_st register.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t rxfifo_full: 1;
uint32_t txfifo_empty: 1;
uint32_t parity_err: 1;
uint32_t frm_err: 1;
uint32_t rxfifo_ovf: 1;
uint32_t dsr_chg: 1;
uint32_t cts_chg: 1;
uint32_t brk_det: 1;
uint32_t rxfifo_tout: 1;
uint32_t sw_xon: 1;
uint32_t sw_xoff: 1;
uint32_t glitch_det: 1;
uint32_t tx_brk_done: 1;
uint32_t tx_brk_idle_done: 1;
uint32_t tx_done: 1;
uint32_t rs485_parity_err: 1;
uint32_t rs485_frm_err: 1;
uint32_t rs485_clash: 1;
uint32_t at_cmd_char_det: 1;
uint32_t wakeup: 1;
uint32_t reserved20: 12;
uint32_t rxfifo_full : 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
uint32_t txfifo_empty : 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
uint32_t parity_err : 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
uint32_t frm_err : 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
uint32_t rxfifo_ovf : 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg : 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg : 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
uint32_t brk_det : 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
uint32_t rxfifo_tout : 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
uint32_t sw_xon : 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
uint32_t sw_xoff : 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
uint32_t glitch_det : 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
uint32_t tx_brk_done : 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
uint32_t tx_brk_idle_done : 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done : 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err : 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
uint32_t rs485_frm_err : 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
uint32_t rs485_clash : 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
uint32_t at_cmd_char_det : 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
uint32_t wakeup : 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t div_int: 12;
uint32_t div_int : 12; /*The integral part of the frequency divider factor.*/
uint32_t reserved12 : 8;
uint32_t div_frag: 4;
uint32_t reserved24: 8;
uint32_t div_frag : 4; /*The decimal part of the frequency divider factor.*/
uint32_t reserved24 : 8; /*Reserved*/
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t glitch_filt: 8;
uint32_t glitch_filt_en: 1;
uint32_t glitch_filt : 8; /*when input pulse width is lower than this value, the pulse is ignored.*/
uint32_t glitch_filt_en : 1; /*Set this bit to enable Rx signal filter.*/
uint32_t reserved9 : 23;
};
uint32_t val;
} rx_filt;
union {
struct {
uint32_t rxfifo_cnt: 10;
uint32_t rxfifo_cnt : 10; /*Stores the byte number of valid data in Rx-FIFO.*/
uint32_t reserved10 : 3;
uint32_t dsrn: 1;
uint32_t ctsn: 1;
uint32_t rxd: 1;
uint32_t txfifo_cnt: 10;
uint32_t reserved26: 3;
uint32_t dtrn: 1;
uint32_t rtsn: 1;
uint32_t txd: 1;
uint32_t dsrn : 1; /*The register represent the level value of the internal uart dsr signal.*/
uint32_t ctsn : 1; /*This register represent the level value of the internal uart cts signal.*/
uint32_t rxd : 1; /*This register represent the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt : 10; /*Stores the byte number of data in Tx-FIFO.*/
uint32_t reserved26 : 3; /*Reserved*/
uint32_t dtrn : 1; /*This bit represents the level of the internal uart dtr signal.*/
uint32_t rtsn : 1; /*This bit represents the level of the internal uart rts signal.*/
uint32_t txd : 1; /*This bit represents the level of the internal uart txd signal.*/
};
uint32_t val;
} status;
union {
struct {
uint32_t parity: 1;
uint32_t parity_en: 1;
uint32_t bit_num: 2;
uint32_t stop_bit_num: 2;
uint32_t sw_rts: 1;
uint32_t sw_dtr: 1;
uint32_t txd_brk: 1;
uint32_t irda_dplx: 1;
uint32_t irda_tx_en: 1;
uint32_t irda_wctl: 1;
uint32_t irda_tx_inv: 1;
uint32_t irda_rx_inv: 1;
uint32_t loopback: 1;
uint32_t tx_flow_en: 1;
uint32_t irda_en: 1;
uint32_t rxfifo_rst: 1;
uint32_t txfifo_rst: 1;
uint32_t rxd_inv: 1;
uint32_t cts_inv: 1;
uint32_t dsr_inv: 1;
uint32_t txd_inv: 1;
uint32_t rts_inv: 1;
uint32_t dtr_inv: 1;
uint32_t clk_en: 1;
uint32_t err_wr_mask: 1;
uint32_t en: 1;
uint32_t mem_clk_en: 1;
uint32_t parity : 1; /*This register is used to configure the parity check mode.*/
uint32_t parity_en : 1; /*Set this bit to enable uart parity check.*/
uint32_t bit_num : 2; /*This register is used to set the length of data.*/
uint32_t stop_bit_num : 2; /*This register is used to set the length of stop bit.*/
uint32_t sw_rts : 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr : 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/
uint32_t txd_brk : 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/
uint32_t irda_dplx : 1; /*Set this bit to enable IrDA loopback mode.*/
uint32_t irda_tx_en : 1; /*This is the start enable bit for IrDA transmitter.*/
uint32_t irda_wctl : 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
uint32_t irda_tx_inv : 1; /*Set this bit to invert the level of IrDA transmitter.*/
uint32_t irda_rx_inv : 1; /*Set this bit to invert the level of IrDA receiver.*/
uint32_t loopback : 1; /*Set this bit to enable uart loopback test mode.*/
uint32_t tx_flow_en : 1; /*Set this bit to enable flow control function for transmitter.*/
uint32_t irda_en : 1; /*Set this bit to enable IrDA protocol.*/
uint32_t rxfifo_rst : 1; /*Set this bit to reset the uart receive-FIFO.*/
uint32_t txfifo_rst : 1; /*Set this bit to reset the uart transmit-FIFO.*/
uint32_t rxd_inv : 1; /*Set this bit to inverse the level value of uart rxd signal.*/
uint32_t cts_inv : 1; /*Set this bit to inverse the level value of uart cts signal.*/
uint32_t dsr_inv : 1; /*Set this bit to inverse the level value of uart dsr signal.*/
uint32_t txd_inv : 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv : 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv : 1; /*Set this bit to inverse the level value of uart dtr signal.*/
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
uint32_t err_wr_mask : 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/
uint32_t autobaud_en : 1; /*This is the enable bit for detecting baudrate.*/
uint32_t mem_clk_en : 1; /*UART memory clock gate enable signal.*/
uint32_t reserved29 : 3;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t rxfifo_full_thrhd: 9;
uint32_t txfifo_empty_thrhd: 9;
uint32_t dis_rx_dat_ovf: 1;
uint32_t rx_tout_flow_dis: 1;
uint32_t rx_flow_en: 1;
uint32_t rx_tout_en: 1;
uint32_t rxfifo_full_thrhd : 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
uint32_t txfifo_empty_thrhd : 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
uint32_t dis_rx_dat_ovf : 1; /*Disable UART Rx data overflow detect. */
uint32_t rx_tout_flow_dis : 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/
uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/
uint32_t reserved22 : 10;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t min_cnt: 12;
uint32_t reserved12: 20;
uint32_t min_cnt : 12; /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} lowpulse;
union {
struct {
uint32_t min_cnt: 12;
uint32_t reserved12: 20;
uint32_t min_cnt : 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10;
uint32_t reserved10: 22;
uint32_t edge_cnt : 10; /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} rxd_cnt;
union {
struct {
uint32_t sw_flow_con_en: 1;
uint32_t xonoff_del: 1;
uint32_t force_xon: 1;
uint32_t force_xoff: 1;
uint32_t send_xon: 1;
uint32_t send_xoff: 1;
uint32_t reserved6: 26;
uint32_t sw_flow_con_en : 1; /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
uint32_t xonoff_del : 1; /*Set this bit to remove flow control char from the received data.*/
uint32_t force_xon : 1; /*Set this bit to enable the transmitter to go on sending data.*/
uint32_t force_xoff : 1; /*Set this bit to stop the transmitter from sending data.*/
uint32_t send_xon : 1; /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
uint32_t send_xoff : 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
uint32_t reserved6 : 26; /*Reserved*/
};
uint32_t val;
} flow_conf;
union {
struct {
uint32_t active_threshold: 10;
uint32_t reserved10: 22;
uint32_t active_threshold : 10; /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} sleep_conf;
union {
struct {
uint32_t xoff_threshold: 9;
uint32_t xoff_char: 8;
uint32_t reserved17: 15;
uint32_t xoff_threshold : 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/
uint32_t xoff_char : 8; /*This register stores the Xoff flow control char.*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} swfc_conf0;
union {
struct {
uint32_t xon_threshold: 9;
uint32_t xon_char: 8;
uint32_t reserved17: 15;
uint32_t xon_threshold : 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/
uint32_t xon_char : 8; /*This register stores the Xon flow control char.*/
uint32_t reserved17 : 15; /*Reserved*/
};
uint32_t val;
} swfc_conf1;
union {
struct {
uint32_t tx_brk_num: 8;
uint32_t tx_brk_num : 8; /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
uint32_t reserved8 : 24;
};
uint32_t val;
} txbrk_conf;
union {
struct {
uint32_t rx_idle_thrhd: 10;
uint32_t tx_idle_num: 10;
uint32_t reserved20: 12;
uint32_t rx_idle_thrhd : 10; /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
uint32_t tx_idle_num : 10; /*This register is used to configure the duration time between transfers.*/
uint32_t reserved20 : 12; /*Reserved*/
};
uint32_t val;
} idle_conf;
union {
struct {
uint32_t en: 1;
uint32_t dl0_en: 1;
uint32_t dl1_en: 1;
uint32_t tx_rx_en: 1;
uint32_t rx_busy_tx_en: 1;
uint32_t rx_dly_num: 1;
uint32_t tx_dly_num: 4;
uint32_t reserved10: 22;
uint32_t en : 1; /*Set this bit to choose the rs485 mode.*/
uint32_t dl0_en : 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en : 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en : 1; /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. */
uint32_t rx_busy_tx_en : 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
uint32_t rx_dly_num : 1; /*This register is used to delay the receiver's internal data signal.*/
uint32_t tx_dly_num : 4; /*This register is used to delay the transmitter's internal data signal.*/
uint32_t reserved10 : 22; /*Reserved*/
};
uint32_t val;
} rs485_conf;
union {
struct {
uint32_t pre_idle_num: 16;
uint32_t reserved16: 16;
uint32_t pre_idle_num : 16; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num: 16;
uint32_t reserved16: 16;
uint32_t post_idle_num : 16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_postcnt;
union {
struct {
uint32_t rx_gap_tout: 16;
uint32_t reserved16: 16;
uint32_t rx_gap_tout : 16; /*This register is used to configure the duration time between the at_cmd chars.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_gaptout;
union {
struct {
uint32_t data: 8;
uint32_t char_num: 8;
uint32_t reserved16: 16;
uint32_t data : 8; /*This register is used to configure the content of at_cmd char.*/
uint32_t char_num : 8; /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
uint32_t reserved16 : 16; /*Reserved*/
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t reserved0 : 1;
uint32_t rx_size: 3;
uint32_t tx_size: 3;
uint32_t rx_flow_thrhd: 9;
uint32_t rx_tout_thrhd: 10;
uint32_t force_pd: 1;
uint32_t force_pu: 1;
uint32_t rx_size : 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
uint32_t tx_size : 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
uint32_t rx_flow_thrhd : 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/
uint32_t rx_tout_thrhd : 10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
uint32_t force_pd : 1; /*Set this bit to force power down UART memory.*/
uint32_t force_pu : 1; /*Set this bit to force power up UART memory.*/
uint32_t reserved28 : 4;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t apb_tx_waddr: 10; /*TXFIFO address write by apb bus or hci. Default value is 10'h0 for uart0 10'h80 for uart1 10'h100 for uart2.*/
uint32_t reserved10: 1;
uint32_t tx_raddr: 10; /*TXFIFO address for uart tx read data. Default value is 10'h0 for uart0 10'h80 for uart1 10'h100 for uart2.*/
uint32_t reserved21: 11;
uint32_t apb_tx_waddr : 10; /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
uint32_t reserved10 : 1; /*Reserved*/
uint32_t tx_raddr : 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} mem_tx_status;
union {
struct {
uint32_t apb_rx_raddr: 10; /*RXFIFO address read by apb bus or hci. Default value is 10'h200 for uart0 10'h280 for uart1 10'h300 for uart2.*/
uint32_t reserved10: 1;
uint32_t rx_waddr: 10; /*RXFIFO address for uart rx write data. Default value is 10'h200 for uart0 10'h280 for uart1 10'h300 for uart2.*/
uint32_t reserved21: 11;
uint32_t apb_rx_raddr : 10; /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.*/
uint32_t reserved10 : 1; /*Reserved*/
uint32_t rx_waddr : 10; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.*/
uint32_t reserved21 : 11; /*Reserved*/
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t st_urx_out: 4;
uint32_t st_utx_out: 4;
uint32_t reserved8: 24;
uint32_t st_urx_out : 4; /*This is the status register of receiver.*/
uint32_t st_utx_out : 4; /*This is the status register of transmitter.*/
uint32_t reserved8 : 24; /*Reserved*/
};
uint32_t val;
} fsm_status;
union {
struct {
uint32_t min_cnt: 12;
uint32_t reserved12: 20;
uint32_t min_cnt : 12; /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} pospulse;
union {
struct {
uint32_t min_cnt: 12;
uint32_t reserved12: 20;
uint32_t min_cnt : 12; /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
uint32_t reserved12 : 20; /*Reserved*/
};
uint32_t val;
} negpulse;
union {
struct {
uint32_t sclk_div_b: 6;
uint32_t sclk_div_a: 6;
uint32_t sclk_div_num: 8;
uint32_t sclk_sel: 2;
uint32_t sclk_en: 1;
uint32_t rst_core: 1;
uint32_t tx_sclk_en: 1;
uint32_t rx_sclk_en: 1;
uint32_t tx_rst_core: 1;
uint32_t rx_rst_core: 1;
uint32_t sclk_div_b : 6; /*The denominator of the frequency divider factor.*/
uint32_t sclk_div_a : 6; /*The numerator of the frequency divider factor.*/
uint32_t sclk_div_num : 8; /*The integral part of the frequency divider factor.*/
uint32_t sclk_sel : 2; /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/
uint32_t sclk_en : 1; /*Set this bit to enable UART Tx/Rx clock.*/
uint32_t rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/
uint32_t tx_sclk_en : 1; /*Set this bit to enable UART Tx clock.*/
uint32_t rx_sclk_en : 1; /*Set this bit to enable UART Rx clock.*/
uint32_t tx_rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Tx.*/
uint32_t rx_rst_core : 1; /*Write 1 then write 0 to this bit, reset UART Rx.*/
uint32_t reserved28 : 4;
};
uint32_t val;
} clk_conf;
uint32_t date; /**/
uint32_t id; /**/
uint32_t date;
union {
struct {
uint32_t id : 30; /*This register is used to configure the uart_id.*/
uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
uint32_t update : 1; /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
};
uint32_t val;
} id;
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t UART2;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_UART_STRUCT_H_ */

358
components/soc/esp32s3/include/soc/uhci_reg.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,650 +11,754 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_UHCI_REG_H_
#define _SOC_UHCI_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_UART_RX_BRK_EOF_EN (BIT(12))
#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12))
#define UHCI_UART_RX_BRK_EOF_EN_V 0x1
#define UHCI_UART_RX_BRK_EOF_EN_S 12
/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_CLK_EN (BIT(11))
#define UHCI_CLK_EN_M (BIT(11))
#define UHCI_CLK_EN_V 0x1
#define UHCI_CLK_EN_S 11
/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_ENCODE_CRC_EN (BIT(10))
#define UHCI_ENCODE_CRC_EN_M (BIT(10))
#define UHCI_ENCODE_CRC_EN_V 0x1
#define UHCI_ENCODE_CRC_EN_S 10
/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_LEN_EOF_EN (BIT(9))
#define UHCI_LEN_EOF_EN_M (BIT(9))
#define UHCI_LEN_EOF_EN_V 0x1
#define UHCI_LEN_EOF_EN_S 9
/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
#define UHCI_UART_IDLE_EOF_EN_M (BIT(8))
#define UHCI_UART_IDLE_EOF_EN_V 0x1
#define UHCI_UART_IDLE_EOF_EN_S 8
/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_CRC_REC_EN (BIT(7))
#define UHCI_CRC_REC_EN_M (BIT(7))
#define UHCI_CRC_REC_EN_V 0x1
#define UHCI_CRC_REC_EN_S 7
/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_HEAD_EN (BIT(6))
#define UHCI_HEAD_EN_M (BIT(6))
#define UHCI_HEAD_EN_V 0x1
#define UHCI_HEAD_EN_S 6
/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_SEPER_EN (BIT(5))
#define UHCI_SEPER_EN_M (BIT(5))
#define UHCI_SEPER_EN_V 0x1
#define UHCI_SEPER_EN_S 5
/* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_UART2_CE (BIT(4))
#define UHCI_UART2_CE_M (BIT(4))
#define UHCI_UART2_CE_V 0x1
#define UHCI_UART2_CE_S 4
/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_UART1_CE (BIT(3))
#define UHCI_UART1_CE_M (BIT(3))
#define UHCI_UART1_CE_V 0x1
#define UHCI_UART1_CE_S 3
/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define UHCI_UART0_CE (BIT(2))
#define UHCI_UART0_CE_M (BIT(2))
#define UHCI_UART0_CE_V 0x1
#define UHCI_UART0_CE_S 2
/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_RST (BIT(1))
#define UHCI_RX_RST_M (BIT(1))
#define UHCI_RX_RST_V 0x1
#define UHCI_RX_RST_S 1
/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_RST (BIT(0))
#define UHCI_TX_RST_M (BIT(0))
#define UHCI_TX_RST_V 0x1
#define UHCI_TX_RST_S 0
#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4)
/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL1_INT_RAW (BIT(8))
#define UHCI_APP_CTRL1_INT_RAW_M (BIT(8))
#define UHCI_APP_CTRL1_INT_RAW_V 0x1
#define UHCI_APP_CTRL1_INT_RAW_S 8
/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL0_INT_RAW (BIT(7))
#define UHCI_APP_CTRL0_INT_RAW_M (BIT(7))
#define UHCI_APP_CTRL0_INT_RAW_V 0x1
#define UHCI_APP_CTRL0_INT_RAW_S 7
/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6
/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_A_Q_INT_RAW (BIT(5))
#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5))
#define UHCI_SEND_A_Q_INT_RAW_V 0x1
#define UHCI_SEND_A_Q_INT_RAW_S 5
/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_S_Q_INT_RAW (BIT(4))
#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4))
#define UHCI_SEND_S_Q_INT_RAW_V 0x1
#define UHCI_SEND_S_Q_INT_RAW_S 4
/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_HUNG_INT_RAW (BIT(3))
#define UHCI_TX_HUNG_INT_RAW_M (BIT(3))
#define UHCI_TX_HUNG_INT_RAW_V 0x1
#define UHCI_TX_HUNG_INT_RAW_S 3
/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_HUNG_INT_RAW (BIT(2))
#define UHCI_RX_HUNG_INT_RAW_M (BIT(2))
#define UHCI_RX_HUNG_INT_RAW_V 0x1
#define UHCI_RX_HUNG_INT_RAW_S 2
/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_START_INT_RAW (BIT(1))
#define UHCI_TX_START_INT_RAW_M (BIT(1))
#define UHCI_TX_START_INT_RAW_V 0x1
#define UHCI_TX_START_INT_RAW_S 1
/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_START_INT_RAW (BIT(0))
#define UHCI_RX_START_INT_RAW_M (BIT(0))
#define UHCI_RX_START_INT_RAW_V 0x1
#define UHCI_RX_START_INT_RAW_S 0
#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8)
/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL1_INT_ST (BIT(8))
#define UHCI_APP_CTRL1_INT_ST_M (BIT(8))
#define UHCI_APP_CTRL1_INT_ST_V 0x1
#define UHCI_APP_CTRL1_INT_ST_S 8
/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL0_INT_ST (BIT(7))
#define UHCI_APP_CTRL0_INT_ST_M (BIT(7))
#define UHCI_APP_CTRL0_INT_ST_V 0x1
#define UHCI_APP_CTRL0_INT_ST_S 7
/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1
#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6
/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_A_Q_INT_ST (BIT(5))
#define UHCI_SEND_A_Q_INT_ST_M (BIT(5))
#define UHCI_SEND_A_Q_INT_ST_V 0x1
#define UHCI_SEND_A_Q_INT_ST_S 5
/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_S_Q_INT_ST (BIT(4))
#define UHCI_SEND_S_Q_INT_ST_M (BIT(4))
#define UHCI_SEND_S_Q_INT_ST_V 0x1
#define UHCI_SEND_S_Q_INT_ST_S 4
/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_HUNG_INT_ST (BIT(3))
#define UHCI_TX_HUNG_INT_ST_M (BIT(3))
#define UHCI_TX_HUNG_INT_ST_V 0x1
#define UHCI_TX_HUNG_INT_ST_S 3
/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_HUNG_INT_ST (BIT(2))
#define UHCI_RX_HUNG_INT_ST_M (BIT(2))
#define UHCI_RX_HUNG_INT_ST_V 0x1
#define UHCI_RX_HUNG_INT_ST_S 2
/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_START_INT_ST (BIT(1))
#define UHCI_TX_START_INT_ST_M (BIT(1))
#define UHCI_TX_START_INT_ST_V 0x1
#define UHCI_TX_START_INT_ST_S 1
/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_START_INT_ST (BIT(0))
#define UHCI_RX_START_INT_ST_M (BIT(0))
#define UHCI_RX_START_INT_ST_V 0x1
#define UHCI_RX_START_INT_ST_S 0
#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC)
/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL1_INT_ENA (BIT(8))
#define UHCI_APP_CTRL1_INT_ENA_M (BIT(8))
#define UHCI_APP_CTRL1_INT_ENA_V 0x1
#define UHCI_APP_CTRL1_INT_ENA_S 8
/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL0_INT_ENA (BIT(7))
#define UHCI_APP_CTRL0_INT_ENA_M (BIT(7))
#define UHCI_APP_CTRL0_INT_ENA_V 0x1
#define UHCI_APP_CTRL0_INT_ENA_S 7
/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6
/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_A_Q_INT_ENA (BIT(5))
#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5))
#define UHCI_SEND_A_Q_INT_ENA_V 0x1
#define UHCI_SEND_A_Q_INT_ENA_S 5
/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_S_Q_INT_ENA (BIT(4))
#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4))
#define UHCI_SEND_S_Q_INT_ENA_V 0x1
#define UHCI_SEND_S_Q_INT_ENA_S 4
/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_HUNG_INT_ENA (BIT(3))
#define UHCI_TX_HUNG_INT_ENA_M (BIT(3))
#define UHCI_TX_HUNG_INT_ENA_V 0x1
#define UHCI_TX_HUNG_INT_ENA_S 3
/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_HUNG_INT_ENA (BIT(2))
#define UHCI_RX_HUNG_INT_ENA_M (BIT(2))
#define UHCI_RX_HUNG_INT_ENA_V 0x1
#define UHCI_RX_HUNG_INT_ENA_S 2
/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_START_INT_ENA (BIT(1))
#define UHCI_TX_START_INT_ENA_M (BIT(1))
#define UHCI_TX_START_INT_ENA_V 0x1
#define UHCI_TX_START_INT_ENA_S 1
/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_START_INT_ENA (BIT(0))
#define UHCI_RX_START_INT_ENA_M (BIT(0))
#define UHCI_RX_START_INT_ENA_V 0x1
#define UHCI_RX_START_INT_ENA_S 0
#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10)
/* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL1_INT_CLR (BIT(8))
#define UHCI_APP_CTRL1_INT_CLR_M (BIT(8))
#define UHCI_APP_CTRL1_INT_CLR_V 0x1
#define UHCI_APP_CTRL1_INT_CLR_S 8
/* UHCI_APP_CTRL0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL0_INT_CLR (BIT(7))
#define UHCI_APP_CTRL0_INT_CLR_M (BIT(7))
#define UHCI_APP_CTRL0_INT_CLR_V 0x1
#define UHCI_APP_CTRL0_INT_CLR_S 7
/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6))
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6
/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_A_Q_INT_CLR (BIT(5))
#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5))
#define UHCI_SEND_A_Q_INT_CLR_V 0x1
#define UHCI_SEND_A_Q_INT_CLR_S 5
/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_S_Q_INT_CLR (BIT(4))
#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4))
#define UHCI_SEND_S_Q_INT_CLR_V 0x1
#define UHCI_SEND_S_Q_INT_CLR_S 4
/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_HUNG_INT_CLR (BIT(3))
#define UHCI_TX_HUNG_INT_CLR_M (BIT(3))
#define UHCI_TX_HUNG_INT_CLR_V 0x1
#define UHCI_TX_HUNG_INT_CLR_S 3
/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_HUNG_INT_CLR (BIT(2))
#define UHCI_RX_HUNG_INT_CLR_M (BIT(2))
#define UHCI_RX_HUNG_INT_CLR_V 0x1
#define UHCI_RX_HUNG_INT_CLR_S 2
/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_START_INT_CLR (BIT(1))
#define UHCI_TX_START_INT_CLR_M (BIT(1))
#define UHCI_TX_START_INT_CLR_V 0x1
#define UHCI_TX_START_INT_CLR_S 1
/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_START_INT_CLR (BIT(0))
#define UHCI_RX_START_INT_CLR_M (BIT(0))
#define UHCI_RX_START_INT_CLR_V 0x1
#define UHCI_RX_START_INT_CLR_S 0
#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14)
#define UHCI_APP_INT_SET_REG(i) (REG_UHCI_BASE(i) + 0x14)
/* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL1_INT_SET (BIT(1))
#define UHCI_APP_CTRL1_INT_SET_M (BIT(1))
#define UHCI_APP_CTRL1_INT_SET_V 0x1
#define UHCI_APP_CTRL1_INT_SET_S 1
/* UHCI_APP_CTRL0_INT_SET : WO ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define UHCI_APP_CTRL0_INT_SET (BIT(0))
#define UHCI_APP_CTRL0_INT_SET_M (BIT(0))
#define UHCI_APP_CTRL0_INT_SET_V 0x1
#define UHCI_APP_CTRL0_INT_SET_S 0
#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x18)
/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SW_START (BIT(8))
#define UHCI_SW_START_M (BIT(8))
#define UHCI_SW_START_V 0x1
#define UHCI_SW_START_S 8
/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_WAIT_SW_START (BIT(7))
#define UHCI_WAIT_SW_START_M (BIT(7))
#define UHCI_WAIT_SW_START_V 0x1
#define UHCI_WAIT_SW_START_S 7
/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_TX_ACK_NUM_RE (BIT(5))
#define UHCI_TX_ACK_NUM_RE_M (BIT(5))
#define UHCI_TX_ACK_NUM_RE_V 0x1
#define UHCI_TX_ACK_NUM_RE_S 5
/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_TX_CHECK_SUM_RE (BIT(4))
#define UHCI_TX_CHECK_SUM_RE_M (BIT(4))
#define UHCI_TX_CHECK_SUM_RE_V 0x1
#define UHCI_TX_CHECK_SUM_RE_S 4
/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SAVE_HEAD (BIT(3))
#define UHCI_SAVE_HEAD_M (BIT(3))
#define UHCI_SAVE_HEAD_V 0x1
#define UHCI_SAVE_HEAD_S 3
/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_CRC_DISABLE (BIT(2))
#define UHCI_CRC_DISABLE_M (BIT(2))
#define UHCI_CRC_DISABLE_V 0x1
#define UHCI_CRC_DISABLE_S 2
/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_CHECK_SEQ_EN (BIT(1))
#define UHCI_CHECK_SEQ_EN_M (BIT(1))
#define UHCI_CHECK_SEQ_EN_V 0x1
#define UHCI_CHECK_SEQ_EN_S 1
/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_CHECK_SUM_EN (BIT(0))
#define UHCI_CHECK_SUM_EN_M (BIT(0))
#define UHCI_CHECK_SUM_EN_V 0x1
#define UHCI_CHECK_SUM_EN_S 0
#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18)
#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x1C)
/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
/*description: */
/*description: .*/
#define UHCI_DECODE_STATE 0x00000007
#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
#define UHCI_DECODE_STATE_V 0x7
#define UHCI_DECODE_STATE_S 3
/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_ERR_CAUSE 0x00000007
#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
#define UHCI_RX_ERR_CAUSE_V 0x7
#define UHCI_RX_ERR_CAUSE_S 0
#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1C)
#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x20)
/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
/*description: */
/*description: .*/
#define UHCI_ENCODE_STATE 0x00000007
#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
#define UHCI_ENCODE_STATE_V 0x7
#define UHCI_ENCODE_STATE_S 0
#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20)
#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24)
/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_13_ESC_EN (BIT(7))
#define UHCI_RX_13_ESC_EN_M (BIT(7))
#define UHCI_RX_13_ESC_EN_V 0x1
#define UHCI_RX_13_ESC_EN_S 7
/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_11_ESC_EN (BIT(6))
#define UHCI_RX_11_ESC_EN_M (BIT(6))
#define UHCI_RX_11_ESC_EN_V 0x1
#define UHCI_RX_11_ESC_EN_S 6
/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_RX_DB_ESC_EN (BIT(5))
#define UHCI_RX_DB_ESC_EN_M (BIT(5))
#define UHCI_RX_DB_ESC_EN_V 0x1
#define UHCI_RX_DB_ESC_EN_S 5
/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_RX_C0_ESC_EN (BIT(4))
#define UHCI_RX_C0_ESC_EN_M (BIT(4))
#define UHCI_RX_C0_ESC_EN_V 0x1
#define UHCI_RX_C0_ESC_EN_S 4
/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_13_ESC_EN (BIT(3))
#define UHCI_TX_13_ESC_EN_M (BIT(3))
#define UHCI_TX_13_ESC_EN_V 0x1
#define UHCI_TX_13_ESC_EN_S 3
/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TX_11_ESC_EN (BIT(2))
#define UHCI_TX_11_ESC_EN_M (BIT(2))
#define UHCI_TX_11_ESC_EN_V 0x1
#define UHCI_TX_11_ESC_EN_S 2
/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_TX_DB_ESC_EN (BIT(1))
#define UHCI_TX_DB_ESC_EN_M (BIT(1))
#define UHCI_TX_DB_ESC_EN_V 0x1
#define UHCI_TX_DB_ESC_EN_S 1
/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_TX_C0_ESC_EN (BIT(0))
#define UHCI_TX_C0_ESC_EN_M (BIT(0))
#define UHCI_TX_C0_ESC_EN_V 0x1
#define UHCI_TX_C0_ESC_EN_S 0
#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24)
#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x28)
/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23))
#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1
#define UHCI_RXFIFO_TIMEOUT_ENA_S 23
/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
/*description: */
/*description: .*/
#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007
#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
/*description: */
/*description: .*/
#define UHCI_RXFIFO_TIMEOUT 0x000000FF
#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
#define UHCI_RXFIFO_TIMEOUT_V 0xFF
#define UHCI_RXFIFO_TIMEOUT_S 12
/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
/*description: */
/*description: .*/
#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11))
#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1
#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
/*description: */
/*description: .*/
#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007
#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7
#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
/*description: */
/*description: .*/
#define UHCI_TXFIFO_TIMEOUT 0x000000FF
#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
#define UHCI_TXFIFO_TIMEOUT_V 0xFF
#define UHCI_TXFIFO_TIMEOUT_S 0
#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28)
#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x2C)
/* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */
/*description: .*/
#define UHCI_ACK_NUM_LOAD (BIT(3))
#define UHCI_ACK_NUM_LOAD_M (BIT(3))
#define UHCI_ACK_NUM_LOAD_V 0x1
#define UHCI_ACK_NUM_LOAD_S 3
/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
/*description: .*/
#define UHCI_ACK_NUM 0x00000007
#define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
#define UHCI_ACK_NUM_V 0x7
#define UHCI_ACK_NUM_S 0
#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2C)
#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x30)
/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_RX_HEAD 0xFFFFFFFF
#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
#define UHCI_RX_HEAD_V 0xFFFFFFFF
#define UHCI_RX_HEAD_S 0
#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30)
#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x34)
/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_ALWAYS_SEND_EN (BIT(7))
#define UHCI_ALWAYS_SEND_EN_M (BIT(7))
#define UHCI_ALWAYS_SEND_EN_V 0x1
#define UHCI_ALWAYS_SEND_EN_S 7
/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
/*description: */
/*description: .*/
#define UHCI_ALWAYS_SEND_NUM 0x00000007
#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
#define UHCI_ALWAYS_SEND_NUM_V 0x7
#define UHCI_ALWAYS_SEND_NUM_S 4
/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
/*description: .*/
#define UHCI_SINGLE_SEND_EN (BIT(3))
#define UHCI_SINGLE_SEND_EN_M (BIT(3))
#define UHCI_SINGLE_SEND_EN_V 0x1
#define UHCI_SINGLE_SEND_EN_S 3
/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SINGLE_SEND_NUM 0x00000007
#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
#define UHCI_SINGLE_SEND_NUM_V 0x7
#define UHCI_SINGLE_SEND_NUM_S 0
#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34)
#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x38)
/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q0_WORD0_S 0
#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38)
#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x3C)
/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q0_WORD1_S 0
#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3C)
#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x40)
/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q1_WORD0_S 0
#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40)
#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x44)
/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q1_WORD1_S 0
#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44)
#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x48)
/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q2_WORD0_S 0
#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48)
#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x4C)
/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q2_WORD1_S 0
#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4C)
#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x50)
/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q3_WORD0_S 0
#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50)
#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x54)
/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q3_WORD1_S 0
#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54)
#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x58)
/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q4_WORD0_S 0
#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58)
#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x5C)
/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q4_WORD1_S 0
#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5C)
#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x60)
/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q5_WORD0_S 0
#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60)
#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x64)
/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q5_WORD1_S 0
#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64)
#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x68)
/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF
#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF
#define UHCI_SEND_Q6_WORD0_S 0
#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68)
#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x6C)
/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
/*description: .*/
#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF
#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF
#define UHCI_SEND_Q6_WORD1_S 0
#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6C)
#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x70)
/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
/*description: */
/*description: .*/
#define UHCI_SEPER_ESC_CHAR1 0x000000FF
#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
#define UHCI_SEPER_ESC_CHAR1_V 0xFF
#define UHCI_SEPER_ESC_CHAR1_S 16
/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
/*description: */
/*description: .*/
#define UHCI_SEPER_ESC_CHAR0 0x000000FF
#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
#define UHCI_SEPER_ESC_CHAR0_V 0xFF
#define UHCI_SEPER_ESC_CHAR0_S 8
/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
/*description: */
/*description: .*/
#define UHCI_SEPER_CHAR 0x000000FF
#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
#define UHCI_SEPER_CHAR_V 0xFF
#define UHCI_SEPER_CHAR_S 0
#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70)
#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x74)
/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ0_CHAR1 0x000000FF
#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
#define UHCI_ESC_SEQ0_CHAR1_V 0xFF
#define UHCI_ESC_SEQ0_CHAR1_S 16
/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ0_CHAR0 0x000000FF
#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
#define UHCI_ESC_SEQ0_CHAR0_V 0xFF
#define UHCI_ESC_SEQ0_CHAR0_S 8
/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ0 0x000000FF
#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
#define UHCI_ESC_SEQ0_V 0xFF
#define UHCI_ESC_SEQ0_S 0
#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74)
#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x78)
/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ1_CHAR1 0x000000FF
#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
#define UHCI_ESC_SEQ1_CHAR1_V 0xFF
#define UHCI_ESC_SEQ1_CHAR1_S 16
/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ1_CHAR0 0x000000FF
#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
#define UHCI_ESC_SEQ1_CHAR0_V 0xFF
#define UHCI_ESC_SEQ1_CHAR0_S 8
/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ1 0x000000FF
#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
#define UHCI_ESC_SEQ1_V 0xFF
#define UHCI_ESC_SEQ1_S 0
#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78)
#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x7C)
/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ2_CHAR1 0x000000FF
#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
#define UHCI_ESC_SEQ2_CHAR1_V 0xFF
#define UHCI_ESC_SEQ2_CHAR1_S 16
/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ2_CHAR0 0x000000FF
#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
#define UHCI_ESC_SEQ2_CHAR0_V 0xFF
#define UHCI_ESC_SEQ2_CHAR0_S 8
/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
/*description: */
/*description: .*/
#define UHCI_ESC_SEQ2 0x000000FF
#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
#define UHCI_ESC_SEQ2_V 0xFF
#define UHCI_ESC_SEQ2_S 0
#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7C)
#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x80)
/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
/*description: */
/*description: .*/
#define UHCI_PKT_THRS 0x00001FFF
#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
#define UHCI_PKT_THRS_V 0x1FFF
#define UHCI_PKT_THRS_S 0
#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80)
/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2001182 ; */
/*description: */
#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x84)
/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2010090 ; */
/*description: .*/
#define UHCI_DATE 0xFFFFFFFF
#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S))
#define UHCI_DATE_V 0xFFFFFFFF
#define UHCI_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_UHCI_REG_H_ */

58
components/soc/esp32s3/include/soc/uhci_struct.h
View File

@@ -1,4 +1,4 @@
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@@ -11,13 +11,14 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifndef _SOC_UHCI_STRUCT_H_
#define _SOC_UHCI_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc.h"
typedef volatile struct {
union {
@@ -47,7 +48,10 @@ typedef volatile struct {
uint32_t tx_hung : 1;
uint32_t send_s_q : 1;
uint32_t send_a_q : 1;
uint32_t reserved6: 26;
uint32_t outlink_eof_err : 1;
uint32_t app_ctrl0 : 1;
uint32_t app_ctrl1 : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} int_raw;
@@ -59,7 +63,10 @@ typedef volatile struct {
uint32_t tx_hung : 1;
uint32_t send_s_q : 1;
uint32_t send_a_q : 1;
uint32_t reserved6: 26;
uint32_t outlink_eof_err : 1;
uint32_t app_ctrl0 : 1;
uint32_t app_ctrl1 : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} int_st;
@@ -71,7 +78,10 @@ typedef volatile struct {
uint32_t tx_hung : 1;
uint32_t send_s_q : 1;
uint32_t send_a_q : 1;
uint32_t reserved6: 26;
uint32_t outlink_eof_err : 1;
uint32_t app_ctrl0 : 1;
uint32_t app_ctrl1 : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} int_ena;
@@ -83,10 +93,21 @@ typedef volatile struct {
uint32_t tx_hung : 1;
uint32_t send_s_q : 1;
uint32_t send_a_q : 1;
uint32_t reserved6: 26;
uint32_t outlink_eof_err : 1;
uint32_t app_ctrl0 : 1;
uint32_t app_ctrl1 : 1;
uint32_t reserved9 : 23;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t app_ctrl0_int_set : 1;
uint32_t app_ctrl1_int_set : 1;
uint32_t reserved2 : 30;
};
uint32_t val;
} app_int_set;
union {
struct {
uint32_t check_sum_en : 1;
@@ -144,8 +165,15 @@ typedef volatile struct {
};
uint32_t val;
} hung_conf;
uint32_t ack_num; /**/
uint32_t rx_head; /**/
union {
struct {
uint32_t ack_num : 3;
uint32_t ack_num_load : 1;
uint32_t reserved4 : 28;
};
uint32_t val;
} ack_num;
uint32_t rx_head;
union {
struct {
uint32_t single_send_num : 3;
@@ -157,7 +185,7 @@ typedef volatile struct {
uint32_t val;
} quick_sent;
struct {
uint32_t w_data[2]; /**/
uint32_t word[2];
} q_data[7];
union {
struct {
@@ -202,12 +230,14 @@ typedef volatile struct {
};
uint32_t val;
} pkt_thres;
uint32_t date; /**/
uint32_t date;
} uhci_dev_t;
extern uhci_dev_t UHCI0;
extern uhci_dev_t UHCI1;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_UHCI_STRUCT_H_ */

17
components/soc/esp32s3/include/soc/usb_caps.h Normal file
View File

@@ -0,0 +1,17 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_USB_PERIPH_NUM 1

737
components/soc/esp32s3/include/soc/usb_device_reg.h Normal file
View File

@@ -0,0 +1,737 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_USB_DEVICE_REG_H_
#define _SOC_USB_DEVICE_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
/* USB_DEVICE_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB
_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is rece
ived, then read data from UART Rx FIFO..*/
#define USB_DEVICE_RDWR_BYTE 0x000000FF
#define USB_DEVICE_RDWR_BYTE_M ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S))
#define USB_DEVICE_RDWR_BYTE_V 0xFF
#define USB_DEVICE_RDWR_BYTE_S 0
#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
/* USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2))
#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_V 0x1
#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_S 2
/* USB_DEVICE_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin
g USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
USB Host..*/
#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE (BIT(1))
#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_M (BIT(1))
#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_V 0x1
#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_S 1
/* USB_DEVICE_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/
#define USB_DEVICE_WR_DONE (BIT(0))
#define USB_DEVICE_WR_DONE_M (BIT(0))
#define USB_DEVICE_WR_DONE_V 0x1
#define USB_DEVICE_WR_DONE_S 0
#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
th zero palyload..*/
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi
th zero palyload..*/
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x1
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
/* USB_DEVICE_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/
#define USB_DEVICE_USB_BUS_RESET_INT_RAW (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_RAW_M (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_RAW_V 0x1
#define USB_DEVICE_USB_BUS_RESET_INT_RAW_S 9
/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec
eived..*/
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
/* USB_DEVICE_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when stuff error is detected..*/
#define USB_DEVICE_STUFF_ERR_INT_RAW (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_RAW_M (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_RAW_V 0x1
#define USB_DEVICE_STUFF_ERR_INT_RAW_S 7
/* USB_DEVICE_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/
#define USB_DEVICE_CRC16_ERR_INT_RAW (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_RAW_M (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_RAW_V 0x1
#define USB_DEVICE_CRC16_ERR_INT_RAW_S 6
/* USB_DEVICE_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/
#define USB_DEVICE_CRC5_ERR_INT_RAW (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_RAW_M (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_RAW_V 0x1
#define USB_DEVICE_CRC5_ERR_INT_RAW_S 5
/* USB_DEVICE_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when pid error is detected..*/
#define USB_DEVICE_PID_ERR_INT_RAW (BIT(4))
#define USB_DEVICE_PID_ERR_INT_RAW_M (BIT(4))
#define USB_DEVICE_PID_ERR_INT_RAW_V 0x1
#define USB_DEVICE_PID_ERR_INT_RAW_S 4
/* USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */
/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_M (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_V 0x1
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_S 3
/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
one packet..*/
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
/* USB_DEVICE_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when SOF frame is received..*/
#define USB_DEVICE_SOF_INT_RAW (BIT(1))
#define USB_DEVICE_SOF_INT_RAW_M (BIT(1))
#define USB_DEVICE_SOF_INT_RAW_V 0x1
#define USB_DEVICE_SOF_INT_RAW_S 1
/* USB_DEVICE_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp
oint 2 of JTAG..*/
#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_M (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_V 0x1
#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_S 0
#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xC)
/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interru
pt..*/
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interru
pt..*/
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x1
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
/* USB_DEVICE_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/
#define USB_DEVICE_USB_BUS_RESET_INT_ST (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_ST_M (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_ST_V 0x1
#define USB_DEVICE_USB_BUS_RESET_INT_ST_S 9
/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrup
t..*/
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
/* USB_DEVICE_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/
#define USB_DEVICE_STUFF_ERR_INT_ST (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_ST_M (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_ST_V 0x1
#define USB_DEVICE_STUFF_ERR_INT_ST_S 7
/* USB_DEVICE_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/
#define USB_DEVICE_CRC16_ERR_INT_ST (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_ST_M (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_ST_V 0x1
#define USB_DEVICE_CRC16_ERR_INT_ST_S 6
/* USB_DEVICE_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/
#define USB_DEVICE_CRC5_ERR_INT_ST (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_ST_M (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_ST_V 0x1
#define USB_DEVICE_CRC5_ERR_INT_ST_S 5
/* USB_DEVICE_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt..*/
#define USB_DEVICE_PID_ERR_INT_ST (BIT(4))
#define USB_DEVICE_PID_ERR_INT_ST_M (BIT(4))
#define USB_DEVICE_PID_ERR_INT_ST_V 0x1
#define USB_DEVICE_PID_ERR_INT_ST_S 4
/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_M (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_V 0x1
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_S 3
/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrup
t..*/
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_S 2
/* USB_DEVICE_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt..*/
#define USB_DEVICE_SOF_INT_ST (BIT(1))
#define USB_DEVICE_SOF_INT_ST_M (BIT(1))
#define USB_DEVICE_SOF_INT_ST_V 0x1
#define USB_DEVICE_SOF_INT_ST_S 1
/* USB_DEVICE_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_M (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_V 0x1
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_S 0
#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x1
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
/* USB_DEVICE_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/
#define USB_DEVICE_USB_BUS_RESET_INT_ENA (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_ENA_M (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_ENA_V 0x1
#define USB_DEVICE_USB_BUS_RESET_INT_ENA_S 9
/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt..*/
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
/* USB_DEVICE_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/
#define USB_DEVICE_STUFF_ERR_INT_ENA (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_ENA_M (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_ENA_V 0x1
#define USB_DEVICE_STUFF_ERR_INT_ENA_S 7
/* USB_DEVICE_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/
#define USB_DEVICE_CRC16_ERR_INT_ENA (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_ENA_M (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_ENA_V 0x1
#define USB_DEVICE_CRC16_ERR_INT_ENA_S 6
/* USB_DEVICE_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/
#define USB_DEVICE_CRC5_ERR_INT_ENA (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_ENA_M (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_ENA_V 0x1
#define USB_DEVICE_CRC5_ERR_INT_ENA_S 5
/* USB_DEVICE_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt..*/
#define USB_DEVICE_PID_ERR_INT_ENA (BIT(4))
#define USB_DEVICE_PID_ERR_INT_ENA_M (BIT(4))
#define USB_DEVICE_PID_ERR_INT_ENA_V 0x1
#define USB_DEVICE_PID_ERR_INT_ENA_S 4
/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_M (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_V 0x1
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_S 3
/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
/* USB_DEVICE_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt..*/
#define USB_DEVICE_SOF_INT_ENA (BIT(1))
#define USB_DEVICE_SOF_INT_ENA_M (BIT(1))
#define USB_DEVICE_SOF_INT_ENA_V 0x1
#define USB_DEVICE_SOF_INT_ENA_S 1
/* USB_DEVICE_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_M (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_V 0x1
#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_S 0
#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11))
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1
#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (BIT(10))
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x1
#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
/* USB_DEVICE_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/
#define USB_DEVICE_USB_BUS_RESET_INT_CLR (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_CLR_M (BIT(9))
#define USB_DEVICE_USB_BUS_RESET_INT_CLR_V 0x1
#define USB_DEVICE_USB_BUS_RESET_INT_CLR_S 9
/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt..*/
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8))
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1
#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
/* USB_DEVICE_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt..*/
#define USB_DEVICE_STUFF_ERR_INT_CLR (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_CLR_M (BIT(7))
#define USB_DEVICE_STUFF_ERR_INT_CLR_V 0x1
#define USB_DEVICE_STUFF_ERR_INT_CLR_S 7
/* USB_DEVICE_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt..*/
#define USB_DEVICE_CRC16_ERR_INT_CLR (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_CLR_M (BIT(6))
#define USB_DEVICE_CRC16_ERR_INT_CLR_V 0x1
#define USB_DEVICE_CRC16_ERR_INT_CLR_S 6
/* USB_DEVICE_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt..*/
#define USB_DEVICE_CRC5_ERR_INT_CLR (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_CLR_M (BIT(5))
#define USB_DEVICE_CRC5_ERR_INT_CLR_V 0x1
#define USB_DEVICE_CRC5_ERR_INT_CLR_S 5
/* USB_DEVICE_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt..*/
#define USB_DEVICE_PID_ERR_INT_CLR (BIT(4))
#define USB_DEVICE_PID_ERR_INT_CLR_M (BIT(4))
#define USB_DEVICE_PID_ERR_INT_CLR_V 0x1
#define USB_DEVICE_PID_ERR_INT_CLR_S 4
/* USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_M (BIT(3))
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_V 0x1
#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_S 3
/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2))
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1
#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
/* USB_DEVICE_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt..*/
#define USB_DEVICE_SOF_INT_CLR (BIT(1))
#define USB_DEVICE_SOF_INT_CLR_M (BIT(1))
#define USB_DEVICE_SOF_INT_CLR_V 0x1
#define USB_DEVICE_SOF_INT_CLR_S 1
/* USB_DEVICE_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/
#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_M (BIT(0))
#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_V 0x1
#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_S 0
#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
/* USB_DEVICE_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/
#define USB_DEVICE_PHY_TX_EDGE_SEL (BIT(15))
#define USB_DEVICE_PHY_TX_EDGE_SEL_M (BIT(15))
#define USB_DEVICE_PHY_TX_EDGE_SEL_V 0x1
#define USB_DEVICE_PHY_TX_EDGE_SEL_S 15
/* USB_DEVICE_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */
/*description: Enable USB pad function..*/
#define USB_DEVICE_USB_PAD_ENABLE (BIT(14))
#define USB_DEVICE_USB_PAD_ENABLE_M (BIT(14))
#define USB_DEVICE_USB_PAD_ENABLE_V 0x1
#define USB_DEVICE_USB_PAD_ENABLE_S 14
/* USB_DEVICE_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: Control pull up value..*/
#define USB_DEVICE_PULLUP_VALUE (BIT(13))
#define USB_DEVICE_PULLUP_VALUE_M (BIT(13))
#define USB_DEVICE_PULLUP_VALUE_V 0x1
#define USB_DEVICE_PULLUP_VALUE_S 13
/* USB_DEVICE_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: Control USB D- pull down..*/
#define USB_DEVICE_DM_PULLDOWN (BIT(12))
#define USB_DEVICE_DM_PULLDOWN_M (BIT(12))
#define USB_DEVICE_DM_PULLDOWN_V 0x1
#define USB_DEVICE_DM_PULLDOWN_S 12
/* USB_DEVICE_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: Control USB D- pull up..*/
#define USB_DEVICE_DM_PULLUP (BIT(11))
#define USB_DEVICE_DM_PULLUP_M (BIT(11))
#define USB_DEVICE_DM_PULLUP_V 0x1
#define USB_DEVICE_DM_PULLUP_S 11
/* USB_DEVICE_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: Control USB D+ pull down..*/
#define USB_DEVICE_DP_PULLDOWN (BIT(10))
#define USB_DEVICE_DP_PULLDOWN_M (BIT(10))
#define USB_DEVICE_DP_PULLDOWN_V 0x1
#define USB_DEVICE_DP_PULLDOWN_S 10
/* USB_DEVICE_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: Control USB D+ pull up..*/
#define USB_DEVICE_DP_PULLUP (BIT(9))
#define USB_DEVICE_DP_PULLUP_M (BIT(9))
#define USB_DEVICE_DP_PULLUP_V 0x1
#define USB_DEVICE_DP_PULLUP_S 9
/* USB_DEVICE_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Enable software control USB D+ D- pullup pulldown.*/
#define USB_DEVICE_PAD_PULL_OVERRIDE (BIT(8))
#define USB_DEVICE_PAD_PULL_OVERRIDE_M (BIT(8))
#define USB_DEVICE_PAD_PULL_OVERRIDE_V 0x1
#define USB_DEVICE_PAD_PULL_OVERRIDE_S 8
/* USB_DEVICE_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Enable software control input threshold.*/
#define USB_DEVICE_VREF_OVERRIDE (BIT(7))
#define USB_DEVICE_VREF_OVERRIDE_M (BIT(7))
#define USB_DEVICE_VREF_OVERRIDE_V 0x1
#define USB_DEVICE_VREF_OVERRIDE_S 7
/* USB_DEVICE_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
#define USB_DEVICE_VREFL 0x00000003
#define USB_DEVICE_VREFL_M ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S))
#define USB_DEVICE_VREFL_V 0x3
#define USB_DEVICE_VREFL_S 5
/* USB_DEVICE_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
#define USB_DEVICE_VREFH 0x00000003
#define USB_DEVICE_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
#define USB_DEVICE_VREFH_V 0x3
#define USB_DEVICE_VREFH_S 3
/* USB_DEVICE_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: USB D+ D- exchange.*/
#define USB_DEVICE_EXCHG_PINS (BIT(2))
#define USB_DEVICE_EXCHG_PINS_M (BIT(2))
#define USB_DEVICE_EXCHG_PINS_V 0x1
#define USB_DEVICE_EXCHG_PINS_S 2
/* USB_DEVICE_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Enable software control USB D+ D- exchange.*/
#define USB_DEVICE_EXCHG_PINS_OVERRIDE (BIT(1))
#define USB_DEVICE_EXCHG_PINS_OVERRIDE_M (BIT(1))
#define USB_DEVICE_EXCHG_PINS_OVERRIDE_V 0x1
#define USB_DEVICE_EXCHG_PINS_OVERRIDE_S 1
/* USB_DEVICE_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Select internal/external PHY.*/
#define USB_DEVICE_PHY_SEL (BIT(0))
#define USB_DEVICE_PHY_SEL_M (BIT(0))
#define USB_DEVICE_PHY_SEL_V 0x1
#define USB_DEVICE_PHY_SEL_S 0
#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1C)
/* USB_DEVICE_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
/*description: USB D- rx value in test.*/
#define USB_DEVICE_TEST_RX_DM (BIT(6))
#define USB_DEVICE_TEST_RX_DM_M (BIT(6))
#define USB_DEVICE_TEST_RX_DM_V 0x1
#define USB_DEVICE_TEST_RX_DM_S 6
/* USB_DEVICE_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: USB D+ rx value in test.*/
#define USB_DEVICE_TEST_RX_DP (BIT(5))
#define USB_DEVICE_TEST_RX_DP_M (BIT(5))
#define USB_DEVICE_TEST_RX_DP_V 0x1
#define USB_DEVICE_TEST_RX_DP_S 5
/* USB_DEVICE_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
/*description: USB differential rx value in test.*/
#define USB_DEVICE_TEST_RX_RCV (BIT(4))
#define USB_DEVICE_TEST_RX_RCV_M (BIT(4))
#define USB_DEVICE_TEST_RX_RCV_V 0x1
#define USB_DEVICE_TEST_RX_RCV_S 4
/* USB_DEVICE_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: USB D- tx value in test.*/
#define USB_DEVICE_TEST_TX_DM (BIT(3))
#define USB_DEVICE_TEST_TX_DM_M (BIT(3))
#define USB_DEVICE_TEST_TX_DM_V 0x1
#define USB_DEVICE_TEST_TX_DM_S 3
/* USB_DEVICE_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: USB D+ tx value in test.*/
#define USB_DEVICE_TEST_TX_DP (BIT(2))
#define USB_DEVICE_TEST_TX_DP_M (BIT(2))
#define USB_DEVICE_TEST_TX_DP_V 0x1
#define USB_DEVICE_TEST_TX_DP_S 2
/* USB_DEVICE_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: USB pad oen in test.*/
#define USB_DEVICE_TEST_USB_OE (BIT(1))
#define USB_DEVICE_TEST_USB_OE_M (BIT(1))
#define USB_DEVICE_TEST_USB_OE_V 0x1
#define USB_DEVICE_TEST_USB_OE_S 1
/* USB_DEVICE_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Enable test of the USB pad.*/
#define USB_DEVICE_TEST_ENABLE (BIT(0))
#define USB_DEVICE_TEST_ENABLE_M (BIT(0))
#define USB_DEVICE_TEST_ENABLE_V 0x1
#define USB_DEVICE_TEST_ENABLE_S 0
#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
/* USB_DEVICE_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: Write 1 to reset JTAG out fifo..*/
#define USB_DEVICE_OUT_FIFO_RESET (BIT(9))
#define USB_DEVICE_OUT_FIFO_RESET_M (BIT(9))
#define USB_DEVICE_OUT_FIFO_RESET_V 0x1
#define USB_DEVICE_OUT_FIFO_RESET_S 9
/* USB_DEVICE_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: Write 1 to reset JTAG in fifo..*/
#define USB_DEVICE_IN_FIFO_RESET (BIT(8))
#define USB_DEVICE_IN_FIFO_RESET_M (BIT(8))
#define USB_DEVICE_IN_FIFO_RESET_V 0x1
#define USB_DEVICE_IN_FIFO_RESET_S 8
/* USB_DEVICE_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: 1: JTAG out fifo is full..*/
#define USB_DEVICE_OUT_FIFO_FULL (BIT(7))
#define USB_DEVICE_OUT_FIFO_FULL_M (BIT(7))
#define USB_DEVICE_OUT_FIFO_FULL_V 0x1
#define USB_DEVICE_OUT_FIFO_FULL_S 7
/* USB_DEVICE_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */
/*description: 1: JTAG out fifo is empty..*/
#define USB_DEVICE_OUT_FIFO_EMPTY (BIT(6))
#define USB_DEVICE_OUT_FIFO_EMPTY_M (BIT(6))
#define USB_DEVICE_OUT_FIFO_EMPTY_V 0x1
#define USB_DEVICE_OUT_FIFO_EMPTY_S 6
/* USB_DEVICE_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */
/*description: JTAT out fifo counter..*/
#define USB_DEVICE_OUT_FIFO_CNT 0x00000003
#define USB_DEVICE_OUT_FIFO_CNT_M ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S))
#define USB_DEVICE_OUT_FIFO_CNT_V 0x3
#define USB_DEVICE_OUT_FIFO_CNT_S 4
/* USB_DEVICE_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: 1: JTAG in fifo is full..*/
#define USB_DEVICE_IN_FIFO_FULL (BIT(3))
#define USB_DEVICE_IN_FIFO_FULL_M (BIT(3))
#define USB_DEVICE_IN_FIFO_FULL_V 0x1
#define USB_DEVICE_IN_FIFO_FULL_S 3
/* USB_DEVICE_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
/*description: 1: JTAG in fifo is empty..*/
#define USB_DEVICE_IN_FIFO_EMPTY (BIT(2))
#define USB_DEVICE_IN_FIFO_EMPTY_M (BIT(2))
#define USB_DEVICE_IN_FIFO_EMPTY_V 0x1
#define USB_DEVICE_IN_FIFO_EMPTY_S 2
/* USB_DEVICE_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: JTAT in fifo counter..*/
#define USB_DEVICE_IN_FIFO_CNT 0x00000003
#define USB_DEVICE_IN_FIFO_CNT_M ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S))
#define USB_DEVICE_IN_FIFO_CNT_V 0x3
#define USB_DEVICE_IN_FIFO_CNT_S 0
#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
/* USB_DEVICE_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
/*description: Frame index of received SOF frame..*/
#define USB_DEVICE_SOF_FRAME_INDEX 0x000007FF
#define USB_DEVICE_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
#define USB_DEVICE_SOF_FRAME_INDEX_V 0x7FF
#define USB_DEVICE_SOF_FRAME_INDEX_S 0
#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
/* USB_DEVICE_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of IN endpoint 0..*/
#define USB_DEVICE_IN_EP0_RD_ADDR 0x0000007F
#define USB_DEVICE_IN_EP0_RD_ADDR_M ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S))
#define USB_DEVICE_IN_EP0_RD_ADDR_V 0x7F
#define USB_DEVICE_IN_EP0_RD_ADDR_S 9
/* USB_DEVICE_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of IN endpoint 0..*/
#define USB_DEVICE_IN_EP0_WR_ADDR 0x0000007F
#define USB_DEVICE_IN_EP0_WR_ADDR_M ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S))
#define USB_DEVICE_IN_EP0_WR_ADDR_V 0x7F
#define USB_DEVICE_IN_EP0_WR_ADDR_S 2
/* USB_DEVICE_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
/*description: State of IN Endpoint 0..*/
#define USB_DEVICE_IN_EP0_STATE 0x00000003
#define USB_DEVICE_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
#define USB_DEVICE_IN_EP0_STATE_V 0x3
#define USB_DEVICE_IN_EP0_STATE_S 0
#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2C)
/* USB_DEVICE_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of IN endpoint 1..*/
#define USB_DEVICE_IN_EP1_RD_ADDR 0x0000007F
#define USB_DEVICE_IN_EP1_RD_ADDR_M ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S))
#define USB_DEVICE_IN_EP1_RD_ADDR_V 0x7F
#define USB_DEVICE_IN_EP1_RD_ADDR_S 9
/* USB_DEVICE_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of IN endpoint 1..*/
#define USB_DEVICE_IN_EP1_WR_ADDR 0x0000007F
#define USB_DEVICE_IN_EP1_WR_ADDR_M ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S))
#define USB_DEVICE_IN_EP1_WR_ADDR_V 0x7F
#define USB_DEVICE_IN_EP1_WR_ADDR_S 2
/* USB_DEVICE_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
/*description: State of IN Endpoint 1..*/
#define USB_DEVICE_IN_EP1_STATE 0x00000003
#define USB_DEVICE_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
#define USB_DEVICE_IN_EP1_STATE_V 0x3
#define USB_DEVICE_IN_EP1_STATE_S 0
#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
/* USB_DEVICE_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of IN endpoint 2..*/
#define USB_DEVICE_IN_EP2_RD_ADDR 0x0000007F
#define USB_DEVICE_IN_EP2_RD_ADDR_M ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S))
#define USB_DEVICE_IN_EP2_RD_ADDR_V 0x7F
#define USB_DEVICE_IN_EP2_RD_ADDR_S 9
/* USB_DEVICE_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of IN endpoint 2..*/
#define USB_DEVICE_IN_EP2_WR_ADDR 0x0000007F
#define USB_DEVICE_IN_EP2_WR_ADDR_M ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S))
#define USB_DEVICE_IN_EP2_WR_ADDR_V 0x7F
#define USB_DEVICE_IN_EP2_WR_ADDR_S 2
/* USB_DEVICE_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
/*description: State of IN Endpoint 2..*/
#define USB_DEVICE_IN_EP2_STATE 0x00000003
#define USB_DEVICE_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
#define USB_DEVICE_IN_EP2_STATE_V 0x3
#define USB_DEVICE_IN_EP2_STATE_S 0
#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
/* USB_DEVICE_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of IN endpoint 3..*/
#define USB_DEVICE_IN_EP3_RD_ADDR 0x0000007F
#define USB_DEVICE_IN_EP3_RD_ADDR_M ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S))
#define USB_DEVICE_IN_EP3_RD_ADDR_V 0x7F
#define USB_DEVICE_IN_EP3_RD_ADDR_S 9
/* USB_DEVICE_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of IN endpoint 3..*/
#define USB_DEVICE_IN_EP3_WR_ADDR 0x0000007F
#define USB_DEVICE_IN_EP3_WR_ADDR_M ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S))
#define USB_DEVICE_IN_EP3_WR_ADDR_V 0x7F
#define USB_DEVICE_IN_EP3_WR_ADDR_S 2
/* USB_DEVICE_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
/*description: State of IN Endpoint 3..*/
#define USB_DEVICE_IN_EP3_STATE 0x00000003
#define USB_DEVICE_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
#define USB_DEVICE_IN_EP3_STATE_V 0x3
#define USB_DEVICE_IN_EP3_STATE_S 0
#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
/* USB_DEVICE_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of OUT endpoint 0..*/
#define USB_DEVICE_OUT_EP0_RD_ADDR 0x0000007F
#define USB_DEVICE_OUT_EP0_RD_ADDR_M ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S))
#define USB_DEVICE_OUT_EP0_RD_ADDR_V 0x7F
#define USB_DEVICE_OUT_EP0_RD_ADDR_S 9
/* USB_DEVICE_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/
#define USB_DEVICE_OUT_EP0_WR_ADDR 0x0000007F
#define USB_DEVICE_OUT_EP0_WR_ADDR_M ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S))
#define USB_DEVICE_OUT_EP0_WR_ADDR_V 0x7F
#define USB_DEVICE_OUT_EP0_WR_ADDR_S 2
/* USB_DEVICE_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: State of OUT Endpoint 0..*/
#define USB_DEVICE_OUT_EP0_STATE 0x00000003
#define USB_DEVICE_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
#define USB_DEVICE_OUT_EP0_STATE_V 0x3
#define USB_DEVICE_OUT_EP0_STATE_S 0
#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3C)
/* USB_DEVICE_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
/*description: Data count in OUT endpoint 1 when one packet is received..*/
#define USB_DEVICE_OUT_EP1_REC_DATA_CNT 0x0000007F
#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_M ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S))
#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_V 0x7F
#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_S 16
/* USB_DEVICE_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of OUT endpoint 1..*/
#define USB_DEVICE_OUT_EP1_RD_ADDR 0x0000007F
#define USB_DEVICE_OUT_EP1_RD_ADDR_M ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S))
#define USB_DEVICE_OUT_EP1_RD_ADDR_V 0x7F
#define USB_DEVICE_OUT_EP1_RD_ADDR_S 9
/* USB_DEVICE_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
#define USB_DEVICE_OUT_EP1_WR_ADDR 0x0000007F
#define USB_DEVICE_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
#define USB_DEVICE_OUT_EP1_WR_ADDR_V 0x7F
#define USB_DEVICE_OUT_EP1_WR_ADDR_S 2
/* USB_DEVICE_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: State of OUT Endpoint 1..*/
#define USB_DEVICE_OUT_EP1_STATE 0x00000003
#define USB_DEVICE_OUT_EP1_STATE_M ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S))
#define USB_DEVICE_OUT_EP1_STATE_V 0x3
#define USB_DEVICE_OUT_EP1_STATE_S 0
#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
/* USB_DEVICE_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
/*description: Read data address of OUT endpoint 2..*/
#define USB_DEVICE_OUT_EP2_RD_ADDR 0x0000007F
#define USB_DEVICE_OUT_EP2_RD_ADDR_M ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S))
#define USB_DEVICE_OUT_EP2_RD_ADDR_V 0x7F
#define USB_DEVICE_OUT_EP2_RD_ADDR_S 9
/* USB_DEVICE_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
/*description: Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
#define USB_DEVICE_OUT_EP2_WR_ADDR 0x0000007F
#define USB_DEVICE_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
#define USB_DEVICE_OUT_EP2_WR_ADDR_V 0x7F
#define USB_DEVICE_OUT_EP2_WR_ADDR_S 2
/* USB_DEVICE_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: State of OUT Endpoint 2..*/
#define USB_DEVICE_OUT_EP2_STATE 0x00000003
#define USB_DEVICE_OUT_EP2_STATE_M ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S))
#define USB_DEVICE_OUT_EP2_STATE_V 0x3
#define USB_DEVICE_OUT_EP2_STATE_S 0
#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
/* USB_DEVICE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
tes registers..*/
#define USB_DEVICE_CLK_EN (BIT(0))
#define USB_DEVICE_CLK_EN_M (BIT(0))
#define USB_DEVICE_CLK_EN_V 0x1
#define USB_DEVICE_CLK_EN_S 0
#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
/* USB_DEVICE_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: 1: Force clock on for usb memory..*/
#define USB_DEVICE_USB_MEM_CLK_EN (BIT(1))
#define USB_DEVICE_USB_MEM_CLK_EN_M (BIT(1))
#define USB_DEVICE_USB_MEM_CLK_EN_V 0x1
#define USB_DEVICE_USB_MEM_CLK_EN_S 1
/* USB_DEVICE_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: 1: power down usb memory..*/
#define USB_DEVICE_USB_MEM_PD (BIT(0))
#define USB_DEVICE_USB_MEM_PD_M (BIT(0))
#define USB_DEVICE_USB_MEM_PD_V 0x1
#define USB_DEVICE_USB_MEM_PD_S 0
#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
/* USB_DEVICE_DATE : R/W ;bitpos:[31:0] ;default: 32'h2011190 ; */
/*description: register version..*/
#define USB_DEVICE_DATE 0xFFFFFFFF
#define USB_DEVICE_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
#define USB_DEVICE_DATE_V 0xFFFFFFFF
#define USB_DEVICE_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_USB_DEVICE_REG_H_ */

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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/* GPIOs used to connect an external USB PHY */
#define USBPHY_VP_NUM 33
#define USBPHY_VM_NUM 34
#define USBPHY_RCV_NUM 35
#define USBPHY_OEN_NUM 36
#define USBPHY_VPO_NUM 37
#define USBPHY_VMO_NUM 38
/* GPIOs corresponding to the pads of the internal USB PHY */
#define USBPHY_DP_NUM 20
#define USBPHY_DM_NUM 19

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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include "usb_types.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct usb_reg {
volatile uint32_t gotgctl; /*!< 0x0 */
volatile uint32_t gotgint;
volatile uint32_t gahbcfg;
volatile uint32_t gusbcfg;
volatile uint32_t grstctl; /*!< 0x10 */
volatile uint32_t gintsts;
volatile uint32_t gintmsk;
volatile uint32_t grxstsr;
volatile uint32_t grxstsp; /*!< 0x20 */
volatile uint32_t grxfsiz;
volatile uint32_t gnptxfsiz;
volatile uint32_t gnptxsts;
volatile uint32_t reserved0x2c;
volatile uint32_t gpvndctl; /*!< 0x30 */
volatile uint32_t ggpio;
volatile uint32_t guid;
volatile uint32_t gsnpsid;
volatile uint32_t ghwcfg1; /*!< 0x40 */
volatile uint32_t ghwcfg2;
volatile uint32_t ghwcfg3;
volatile uint32_t ghwcfg4; /*!< 0x50 */
volatile uint32_t glpmcfg; /*!< 0x54 */
volatile uint32_t gpwrdn; /*!< 0x58 */
volatile uint32_t gdfifocfg; /*!< 0x5c */
volatile uint32_t gadpctl; /*!< 0x60 */
uint32_t reserved0x64[39];
volatile uint32_t hptxfsiz; /*!< 0x100 */
volatile uint32_t dieptxf[15]; /*!< 0x104 */
uint32_t reserved0x140[176]; /*!< 0x140 */
/**
* The Host Global Registers structure defines the size and relative
* field offsets for the Host Mode Global Registers. Host Global
* Registers offsets 400h-7FFh.
*/
volatile uint32_t hcfg; /*!< Host Configuration Register. <i>Offset: 400h</i> */
volatile uint32_t hfir; /*!< Host Frame Interval Register. <i>Offset: 404h</i> */
volatile uint32_t hfnum; /*!< Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
uint32_t reserved0x40C; /*!< Reserved. <i>Offset: 40Ch</i> */
volatile uint32_t hptxsts; /*!< Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
volatile uint32_t haint; /*!< Host All Channels Interrupt Register. <i>Offset: 414h</i> */
volatile uint32_t haintmsk; /*!< Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
volatile uint32_t hflbaddr; /*!< Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
uint32_t reserved0x420[7];
volatile uint32_t hprt; //0x440
uint32_t reserved0x444[240];
volatile uint32_t dcfg; /*!< Device Configuration Register. <i>Offset 800h</i> */
volatile uint32_t dctl; /*!< Device Control Register. <i>Offset: 804h</i> */
volatile uint32_t dsts; /*!< Device Status Register (Read Only). <i>Offset: 808h</i> */
uint32_t reserved0x80c; /*!< Reserved. <i>Offset: 80Ch</i> */
volatile uint32_t diepmsk; /*!< Device IN Endpoint Common Interrupt Mask Register. <i>Offset: 810h</i> */
volatile uint32_t doepmsk; /*!< Device OUT Endpoint Common Interrupt Mask Register. <i>Offset: 814h</i> */
volatile uint32_t daint; /*!< Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
volatile uint32_t daintmsk; /*!< Device All Endpoints Interrupt Mask Register. <i>Offset: 81Ch</i> */
volatile uint32_t dtknqr1; /*!< Device IN Token Queue Read Register-1 (Read Only). <i>Offset: 820h</i> */
volatile uint32_t dtknqr2; /*!< Device IN Token Queue Read Register-2 (Read Only). <i>Offset: 824h</i> */
volatile uint32_t dvbusdis; /*!< Device VBUS discharge Register. <i>Offset: 828h</i> */
volatile uint32_t dvbuspulse; /*!< Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
volatile uint32_t dtknqr3_dthrctl; /*!< Device IN Token Queue Read Register-3 (Read Only). Device Thresholding control register (Read/Write) <i>Offset: 830h</i> */
volatile uint32_t dtknqr4_fifoemptymsk; /*!< Device IN Token Queue Read Register-4 (Read Only). Device IN EPs empty Inr. Mask Register (Read/Write)<i>Offset: 834h</i> */
volatile uint32_t deachint; /*!< Device Each Endpoint Interrupt Register (Read Only). <i>Offset: 838h</i> */
volatile uint32_t deachintmsk; /*!< Device Each Endpoint Interrupt mask Register (Read/Write). <i>Offset: 83Ch</i> */
volatile uint32_t diepeachintmsk[16]; /*!< Device Each In Endpoint Interrupt mask Register (Read/Write). <i>Offset: 840h</i> */
volatile uint32_t doepeachintmsk[16]; /*!< Device Each Out Endpoint Interrupt mask Register (Read/Write). <i>Offset: 880h</i> */
uint32_t reserved0x8c0[16];
/* Input Endpoints*/
usb_in_endpoint_t in_ep_reg[USB_IN_EP_NUM]; /*!< 0x900*/
uint32_t reserved6[72];
/* Output Endpoints */
usb_out_endpoint_t out_ep_reg[USB_OUT_EP_NUM];
uint32_t reserved7[136];
uint32_t pcgctrl; /*!<0xe00*/
uint32_t pcgctrl1;
uint8_t reserved8[0x1000 - 0xe08]; /*!<0xd00*/
uint32_t fifo[16][0x400]; /*!<0x1000*/
uint8_t reserved0x11000[0x20000 - 0x11000];
uint32_t dbg_fifo[0x20000]; /*!< 0x20000*/
} usb_dev_t;
extern usb_dev_t USB0;
#ifdef __cplusplus
}
#endif

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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
/* USB IN EP index */
typedef enum {
USB_IN_EP_0 = 0,
USB_IN_EP_1,
USB_IN_EP_2,
USB_IN_EP_3,
USB_IN_EP_4,
USB_IN_EP_5,
USB_IN_EP_6,
USB_IN_EP_NUM
} usb_in_ep_idx_t;
/* USB OUT EP index */
typedef enum {
USB_OUT_EP_0 = 0,
USB_OUT_EP_1,
USB_OUT_EP_2,
USB_OUT_EP_3,
USB_OUT_EP_4,
USB_OUT_EP_5,
USB_OUT_EP_6,
USB_OUT_EP_NUM
} usb_out_ep_idx_t;
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
volatile uint32_t dtxfsts;
uint32_t reserved2;
} usb_in_endpoint_t;
/* USB OUT EP Register block type */
typedef struct usb_out_ep_reg {
volatile uint32_t doepctl;
uint32_t reserved;
volatile uint32_t doepint;
uint32_t reserved1;
volatile uint32_t doeptsiz;
volatile uint32_t doepdma;
uint32_t reserved2;
uint32_t reserved3;
} usb_out_endpoint_t;
#ifdef __cplusplus
}
#endif

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/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_WRAP_OTG_CONF_REG register
* PAD/DFIFO/PHY configuration register.
*/
#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
* This bit is used to enable the software override of srp session end signal.1'b0:
* the signal is controlled by the chip input.1'b1: the signal is controlled by the
* software.
*/
#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001
#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0
/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
* Software override value of srp session end signal.
*/
#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1))
#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001
#define USB_WRAP_SRP_SESSEND_VALUE_S 1
/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
* Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
*/
#define USB_WRAP_PHY_SEL (BIT(2))
#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
#define USB_WRAP_PHY_SEL_V 0x00000001
#define USB_WRAP_PHY_SEL_S 2
/** USB_WRAP_DFIFO_FORCE_PD : R/W; bitpos: [3]; default: 0;
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
*/
#define USB_WRAP_DFIFO_FORCE_PD (BIT(3))
#define USB_WRAP_DFIFO_FORCE_PD_M (USB_WRAP_DFIFO_FORCE_PD_V << USB_WRAP_DFIFO_FORCE_PD_S)
#define USB_WRAP_DFIFO_FORCE_PD_V 0x00000001
#define USB_WRAP_DFIFO_FORCE_PD_S 3
/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
* Bypass Debounce filters for avalid.
*/
#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4))
#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001
#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4
/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
* Enable software to control USB D+ D- exchange
*/
#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5))
#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001
#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5
/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
* USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
*/
#define USB_WRAP_EXCHG_PINS (BIT(6))
#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
#define USB_WRAP_EXCHG_PINS_V 0x00000001
#define USB_WRAP_EXCHG_PINS_S 6
/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
* Control single-end input high threshold.
*/
#define USB_WRAP_VREFH 0x00000003
#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
#define USB_WRAP_VREFH_V 0x00000003
#define USB_WRAP_VREFH_S 7
/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
* Control single-end input low threshold.
*/
#define USB_WRAP_VREFL 0x00000003
#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
#define USB_WRAP_VREFL_V 0x00000003
#define USB_WRAP_VREFL_S 9
/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
* Enable software to control input threshold.
*/
#define USB_WRAP_VREF_OVERRIDE (BIT(11))
#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
#define USB_WRAP_VREF_OVERRIDE_V 0x00000001
#define USB_WRAP_VREF_OVERRIDE_S 11
/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
* Enable software to control USB pad in pullup or pulldown mode.
*/
#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12))
#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001
#define USB_WRAP_PAD_PULL_OVERRIDE_S 12
/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
* Control USB D+ pullup.
*/
#define USB_WRAP_DP_PULLUP (BIT(13))
#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
#define USB_WRAP_DP_PULLUP_V 0x00000001
#define USB_WRAP_DP_PULLUP_S 13
/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
* Control USB D+ pulldown.
*/
#define USB_WRAP_DP_PULLDOWN (BIT(14))
#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
#define USB_WRAP_DP_PULLDOWN_V 0x00000001
#define USB_WRAP_DP_PULLDOWN_S 14
/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
* Control USB D+ pullup.
*/
#define USB_WRAP_DM_PULLUP (BIT(15))
#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
#define USB_WRAP_DM_PULLUP_V 0x00000001
#define USB_WRAP_DM_PULLUP_S 15
/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
* Control USB D+ pulldown.
*/
#define USB_WRAP_DM_PULLDOWN (BIT(16))
#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
#define USB_WRAP_DM_PULLDOWN_V 0x00000001
#define USB_WRAP_DM_PULLDOWN_S 16
/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
* Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
*/
#define USB_WRAP_PULLUP_VALUE (BIT(17))
#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
#define USB_WRAP_PULLUP_VALUE_V 0x00000001
#define USB_WRAP_PULLUP_VALUE_S 17
/** USB_WRAP_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
* Enable USB pad function.
*/
#define USB_WRAP_PAD_ENABLE (BIT(18))
#define USB_WRAP_PAD_ENABLE_M (USB_WRAP_PAD_ENABLE_V << USB_WRAP_PAD_ENABLE_S)
#define USB_WRAP_PAD_ENABLE_V 0x00000001
#define USB_WRAP_PAD_ENABLE_S 18
/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 1;
* Force AHB clock always on.
*/
#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19))
#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001
#define USB_WRAP_AHB_CLK_FORCE_ON_S 19
/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
* Force PHY clock always on.
*/
#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20))
#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001
#define USB_WRAP_PHY_CLK_FORCE_ON_S 20
/** USB_WRAP_PHY_TX_EDGE_SEL : R/W; bitpos: [21]; default: 0;
* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
*/
#define USB_WRAP_PHY_TX_EDGE_SEL (BIT(21))
#define USB_WRAP_PHY_TX_EDGE_SEL_M (USB_WRAP_PHY_TX_EDGE_SEL_V << USB_WRAP_PHY_TX_EDGE_SEL_S)
#define USB_WRAP_PHY_TX_EDGE_SEL_V 0x00000001
#define USB_WRAP_PHY_TX_EDGE_SEL_S 21
/** USB_WRAP_DFIFO_FORCE_PU : R/W; bitpos: [22]; default: 0;
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
*/
#define USB_WRAP_DFIFO_FORCE_PU (BIT(22))
#define USB_WRAP_DFIFO_FORCE_PU_M (USB_WRAP_DFIFO_FORCE_PU_V << USB_WRAP_DFIFO_FORCE_PU_S)
#define USB_WRAP_DFIFO_FORCE_PU_V 0x00000001
#define USB_WRAP_DFIFO_FORCE_PU_S 22
/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
* Disable auto clock gating of CSR registers.
*/
#define USB_WRAP_CLK_EN (BIT(31))
#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
#define USB_WRAP_CLK_EN_V 0x00000001
#define USB_WRAP_CLK_EN_S 31
/** USB_WRAP_TEST_CONF_REG register
* TEST relative configuration registers.
*/
#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4)
/** USB_WRAP_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
* Enable to test the USB pad.
*/
#define USB_WRAP_TEST_ENABLE (BIT(0))
#define USB_WRAP_TEST_ENABLE_M (USB_WRAP_TEST_ENABLE_V << USB_WRAP_TEST_ENABLE_S)
#define USB_WRAP_TEST_ENABLE_V 0x00000001
#define USB_WRAP_TEST_ENABLE_S 0
/** USB_WRAP_TEST_USB_WRAP_OE : R/W; bitpos: [1]; default: 0;
* USB pad oen in test.
*/
#define USB_WRAP_TEST_USB_WRAP_OE (BIT(1))
#define USB_WRAP_TEST_USB_WRAP_OE_M (USB_WRAP_TEST_USB_WRAP_OE_V << USB_WRAP_TEST_USB_WRAP_OE_S)
#define USB_WRAP_TEST_USB_WRAP_OE_V 0x00000001
#define USB_WRAP_TEST_USB_WRAP_OE_S 1
/** USB_WRAP_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test.
*/
#define USB_WRAP_TEST_TX_DP (BIT(2))
#define USB_WRAP_TEST_TX_DP_M (USB_WRAP_TEST_TX_DP_V << USB_WRAP_TEST_TX_DP_S)
#define USB_WRAP_TEST_TX_DP_V 0x00000001
#define USB_WRAP_TEST_TX_DP_S 2
/** USB_WRAP_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test.
*/
#define USB_WRAP_TEST_TX_DM (BIT(3))
#define USB_WRAP_TEST_TX_DM_M (USB_WRAP_TEST_TX_DM_V << USB_WRAP_TEST_TX_DM_S)
#define USB_WRAP_TEST_TX_DM_V 0x00000001
#define USB_WRAP_TEST_TX_DM_S 3
/** USB_WRAP_TEST_RX_RCV : RO; bitpos: [4]; default: 0;
* USB differential rx value in test.
*/
#define USB_WRAP_TEST_RX_RCV (BIT(4))
#define USB_WRAP_TEST_RX_RCV_M (USB_WRAP_TEST_RX_RCV_V << USB_WRAP_TEST_RX_RCV_S)
#define USB_WRAP_TEST_RX_RCV_V 0x00000001
#define USB_WRAP_TEST_RX_RCV_S 4
/** USB_WRAP_TEST_RX_DP : RO; bitpos: [5]; default: 0;
* USB D+ rx value in test.
*/
#define USB_WRAP_TEST_RX_DP (BIT(5))
#define USB_WRAP_TEST_RX_DP_M (USB_WRAP_TEST_RX_DP_V << USB_WRAP_TEST_RX_DP_S)
#define USB_WRAP_TEST_RX_DP_V 0x00000001
#define USB_WRAP_TEST_RX_DP_S 5
/** USB_WRAP_TEST_RX_DM : RO; bitpos: [6]; default: 0;
* USB D- rx value in test.
*/
#define USB_WRAP_TEST_RX_DM (BIT(6))
#define USB_WRAP_TEST_RX_DM_M (USB_WRAP_TEST_RX_DM_V << USB_WRAP_TEST_RX_DM_S)
#define USB_WRAP_TEST_RX_DM_V 0x00000001
#define USB_WRAP_TEST_RX_DM_S 6
/** USB_WRAP_DATE_REG register
* Version register.
*/
#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3fc)
/** USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 419631616;
* data register.
*/
#define USB_WRAP_DATE 0xFFFFFFFF
#define USB_WRAP_DATE_M (USB_WRAP_DATE_V << USB_WRAP_DATE_S)
#define USB_WRAP_DATE_V 0xFFFFFFFF
#define USB_WRAP_DATE_S 0
#ifdef __cplusplus
}
#endif

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/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Control/Status registers */
/** Type of otg_conf register
* PAD/DFIFO/PHY configuration register.
*/
typedef union {
struct {
/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
* This bit is used to enable the software override of srp session end signal.1'b0:
* the signal is controlled by the chip input.1'b1: the signal is controlled by the
* software.
*/
uint32_t srp_sessend_override:1;
/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
* Software override value of srp session end signal.
*/
uint32_t srp_sessend_value:1;
/** phy_sel : R/W; bitpos: [2]; default: 0;
* Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
*/
uint32_t phy_sel:1;
/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
*/
uint32_t dfifo_force_pd:1;
/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
* Bypass Debounce filters for avalid.
*/
uint32_t dbnce_fltr_bypass:1;
/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
* Enable software to control USB D+ D- exchange
*/
uint32_t exchg_pins_override:1;
/** exchg_pins : R/W; bitpos: [6]; default: 0;
* USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
*/
uint32_t exchg_pins:1;
/** vrefh : R/W; bitpos: [8:7]; default: 0;
* Control single-end input high threshold.
*/
uint32_t vrefh:2;
/** vrefl : R/W; bitpos: [10:9]; default: 0;
* Control single-end input low threshold.
*/
uint32_t vrefl:2;
/** vref_override : R/W; bitpos: [11]; default: 0;
* Enable software to control input threshold.
*/
uint32_t vref_override:1;
/** pad_pull_override : R/W; bitpos: [12]; default: 0;
* Enable software to control USB pad in pullup or pulldown mode.
*/
uint32_t pad_pull_override:1;
/** dp_pullup : R/W; bitpos: [13]; default: 0;
* Control USB D+ pullup.
*/
uint32_t dp_pullup:1;
/** dp_pulldown : R/W; bitpos: [14]; default: 0;
* Control USB D+ pulldown.
*/
uint32_t dp_pulldown:1;
/** dm_pullup : R/W; bitpos: [15]; default: 0;
* Control USB D+ pullup.
*/
uint32_t dm_pullup:1;
/** dm_pulldown : R/W; bitpos: [16]; default: 0;
* Control USB D+ pulldown.
*/
uint32_t dm_pulldown:1;
/** pullup_value : R/W; bitpos: [17]; default: 0;
* Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
*/
uint32_t pullup_value:1;
/** pad_enable : R/W; bitpos: [18]; default: 0;
* Enable USB pad function.
*/
uint32_t pad_enable:1;
/** ahb_clk_force_on : R/W; bitpos: [19]; default: 1;
* Force AHB clock always on.
*/
uint32_t ahb_clk_force_on:1;
/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
* Force PHY clock always on.
*/
uint32_t phy_clk_force_on:1;
/** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
*/
uint32_t phy_tx_edge_sel:1;
/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
*/
uint32_t dfifo_force_pu:1;
uint32_t reserved_23:8;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Disable auto clock gating of CSR registers.
*/
uint32_t clk_en:1;
};
uint32_t val;
} usb_wrap_otg_conf_reg_t;
/** Type of test_conf register
* TEST relative configuration registers.
*/
typedef union {
struct {
/** test_enable : R/W; bitpos: [0]; default: 0;
* Enable to test the USB pad.
*/
uint32_t test_enable:1;
/** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test.
*/
uint32_t test_usb_wrap_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test.
*/
uint32_t test_tx_dp:1;
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test.
*/
uint32_t test_tx_dm:1;
/** test_rx_rcv : RO; bitpos: [4]; default: 0;
* USB differential rx value in test.
*/
uint32_t test_rx_rcv:1;
/** test_rx_dp : RO; bitpos: [5]; default: 0;
* USB D+ rx value in test.
*/
uint32_t test_rx_dp:1;
/** test_rx_dm : RO; bitpos: [6]; default: 0;
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;
/** Status registers */
/** Type of date register
* Version register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 419631616;
* data register.
*/
uint32_t date:32;
};
uint32_t val;
} usb_wrap_date_reg_t;
typedef struct {
volatile usb_wrap_otg_conf_reg_t otg_conf;
volatile usb_wrap_test_conf_reg_t test_conf;
uint32_t reserved_008;
uint32_t reserved_00c;
uint32_t reserved_010;
uint32_t reserved_014;
uint32_t reserved_018;
uint32_t reserved_01c;
uint32_t reserved_020;
uint32_t reserved_024;
uint32_t reserved_028;
uint32_t reserved_02c;
uint32_t reserved_030;
uint32_t reserved_034;
uint32_t reserved_038;
uint32_t reserved_03c;
uint32_t reserved_040;
uint32_t reserved_044;
uint32_t reserved_048;
uint32_t reserved_04c;
uint32_t reserved_050;
uint32_t reserved_054;
uint32_t reserved_058;
uint32_t reserved_05c;
uint32_t reserved_060;
uint32_t reserved_064;
uint32_t reserved_068;
uint32_t reserved_06c;
uint32_t reserved_070;
uint32_t reserved_074;
uint32_t reserved_078;
uint32_t reserved_07c;
uint32_t reserved_080;
uint32_t reserved_084;
uint32_t reserved_088;
uint32_t reserved_08c;
uint32_t reserved_090;
uint32_t reserved_094;
uint32_t reserved_098;
uint32_t reserved_09c;
uint32_t reserved_0a0;
uint32_t reserved_0a4;
uint32_t reserved_0a8;
uint32_t reserved_0ac;
uint32_t reserved_0b0;
uint32_t reserved_0b4;
uint32_t reserved_0b8;
uint32_t reserved_0bc;
uint32_t reserved_0c0;
uint32_t reserved_0c4;
uint32_t reserved_0c8;
uint32_t reserved_0cc;
uint32_t reserved_0d0;
uint32_t reserved_0d4;
uint32_t reserved_0d8;
uint32_t reserved_0dc;
uint32_t reserved_0e0;
uint32_t reserved_0e4;
uint32_t reserved_0e8;
uint32_t reserved_0ec;
uint32_t reserved_0f0;
uint32_t reserved_0f4;
uint32_t reserved_0f8;
uint32_t reserved_0fc;
uint32_t reserved_100;
uint32_t reserved_104;
uint32_t reserved_108;
uint32_t reserved_10c;
uint32_t reserved_110;
uint32_t reserved_114;
uint32_t reserved_118;
uint32_t reserved_11c;
uint32_t reserved_120;
uint32_t reserved_124;
uint32_t reserved_128;
uint32_t reserved_12c;
uint32_t reserved_130;
uint32_t reserved_134;
uint32_t reserved_138;
uint32_t reserved_13c;
uint32_t reserved_140;
uint32_t reserved_144;
uint32_t reserved_148;
uint32_t reserved_14c;
uint32_t reserved_150;
uint32_t reserved_154;
uint32_t reserved_158;
uint32_t reserved_15c;
uint32_t reserved_160;
uint32_t reserved_164;
uint32_t reserved_168;
uint32_t reserved_16c;
uint32_t reserved_170;
uint32_t reserved_174;
uint32_t reserved_178;
uint32_t reserved_17c;
uint32_t reserved_180;
uint32_t reserved_184;
uint32_t reserved_188;
uint32_t reserved_18c;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
uint32_t reserved_1ac;
uint32_t reserved_1b0;
uint32_t reserved_1b4;
uint32_t reserved_1b8;
uint32_t reserved_1bc;
uint32_t reserved_1c0;
uint32_t reserved_1c4;
uint32_t reserved_1c8;
uint32_t reserved_1cc;
uint32_t reserved_1d0;
uint32_t reserved_1d4;
uint32_t reserved_1d8;
uint32_t reserved_1dc;
uint32_t reserved_1e0;
uint32_t reserved_1e4;
uint32_t reserved_1e8;
uint32_t reserved_1ec;
uint32_t reserved_1f0;
uint32_t reserved_1f4;
uint32_t reserved_1f8;
uint32_t reserved_1fc;
uint32_t reserved_200;
uint32_t reserved_204;
uint32_t reserved_208;
uint32_t reserved_20c;
uint32_t reserved_210;
uint32_t reserved_214;
uint32_t reserved_218;
uint32_t reserved_21c;
uint32_t reserved_220;
uint32_t reserved_224;
uint32_t reserved_228;
uint32_t reserved_22c;
uint32_t reserved_230;
uint32_t reserved_234;
uint32_t reserved_238;
uint32_t reserved_23c;
uint32_t reserved_240;
uint32_t reserved_244;
uint32_t reserved_248;
uint32_t reserved_24c;
uint32_t reserved_250;
uint32_t reserved_254;
uint32_t reserved_258;
uint32_t reserved_25c;
uint32_t reserved_260;
uint32_t reserved_264;
uint32_t reserved_268;
uint32_t reserved_26c;
uint32_t reserved_270;
uint32_t reserved_274;
uint32_t reserved_278;
uint32_t reserved_27c;
uint32_t reserved_280;
uint32_t reserved_284;
uint32_t reserved_288;
uint32_t reserved_28c;
uint32_t reserved_290;
uint32_t reserved_294;
uint32_t reserved_298;
uint32_t reserved_29c;
uint32_t reserved_2a0;
uint32_t reserved_2a4;
uint32_t reserved_2a8;
uint32_t reserved_2ac;
uint32_t reserved_2b0;
uint32_t reserved_2b4;
uint32_t reserved_2b8;
uint32_t reserved_2bc;
uint32_t reserved_2c0;
uint32_t reserved_2c4;
uint32_t reserved_2c8;
uint32_t reserved_2cc;
uint32_t reserved_2d0;
uint32_t reserved_2d4;
uint32_t reserved_2d8;
uint32_t reserved_2dc;
uint32_t reserved_2e0;
uint32_t reserved_2e4;
uint32_t reserved_2e8;
uint32_t reserved_2ec;
uint32_t reserved_2f0;
uint32_t reserved_2f4;
uint32_t reserved_2f8;
uint32_t reserved_2fc;
uint32_t reserved_300;
uint32_t reserved_304;
uint32_t reserved_308;
uint32_t reserved_30c;
uint32_t reserved_310;
uint32_t reserved_314;
uint32_t reserved_318;
uint32_t reserved_31c;
uint32_t reserved_320;
uint32_t reserved_324;
uint32_t reserved_328;
uint32_t reserved_32c;
uint32_t reserved_330;
uint32_t reserved_334;
uint32_t reserved_338;
uint32_t reserved_33c;
uint32_t reserved_340;
uint32_t reserved_344;
uint32_t reserved_348;
uint32_t reserved_34c;
uint32_t reserved_350;
uint32_t reserved_354;
uint32_t reserved_358;
uint32_t reserved_35c;
uint32_t reserved_360;
uint32_t reserved_364;
uint32_t reserved_368;
uint32_t reserved_36c;
uint32_t reserved_370;
uint32_t reserved_374;
uint32_t reserved_378;
uint32_t reserved_37c;
uint32_t reserved_380;
uint32_t reserved_384;
uint32_t reserved_388;
uint32_t reserved_38c;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
uint32_t reserved_39c;
uint32_t reserved_3a0;
uint32_t reserved_3a4;
uint32_t reserved_3a8;
uint32_t reserved_3ac;
uint32_t reserved_3b0;
uint32_t reserved_3b4;
uint32_t reserved_3b8;
uint32_t reserved_3bc;
uint32_t reserved_3c0;
uint32_t reserved_3c4;
uint32_t reserved_3c8;
uint32_t reserved_3cc;
uint32_t reserved_3d0;
uint32_t reserved_3d4;
uint32_t reserved_3d8;
uint32_t reserved_3dc;
uint32_t reserved_3e0;
uint32_t reserved_3e4;
uint32_t reserved_3e8;
uint32_t reserved_3ec;
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
volatile usb_wrap_date_reg_t date;
} usb_wrap_dev_t;
_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size");
extern usb_wrap_dev_t USB_WRAP;
#ifdef __cplusplus
}
#endif

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components/soc/esp32s3/include/soc/world_controller_reg.h Normal file
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