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test(ulp): added larger delay in ULP FSM I_WR_REG instruction test

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Test is flakey, could possibly be due to the ULP occasionally needing
a bit more time to start up.
This commit is contained in:
Marius Vikhammer
2025-11-17 16:03:15 +08:00
parent 803ea77932
commit fcafa0de5d
1 changed files with 1 additions and 1 deletions
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2
components/ulp/test_apps/ulp_fsm/main/test_ulp.c
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@@ -362,7 +362,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
TEST_ESP_OK(ulp_run(0));
/* Wait for the ULP co-processor to finish up */
vTaskDelay(10 / portTICK_PERIOD_MS);
vTaskDelay(50 / portTICK_PERIOD_MS);
/* Verify the test results */
uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);