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feat(hal): graudate the I2S hal driver into a new component

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This commit is contained in:
laokaiyao
2025-11-11 20:24:44 +08:00
parent bf9070c030
commit fd918efe43
47 changed files with 454 additions and 462 deletions
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3
components/bootloader_support/src/bootloader_random_esp32.c
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@@ -9,7 +9,8 @@
#include "soc/sens_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_reg.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/periph_defs.h"
#include "esp_log.h"
#include "soc/io_mux_reg.h"

1
components/bootloader_support/src/bootloader_random_esp32s2.c
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@@ -9,7 +9,6 @@
#include "soc/sens_reg.h"
#include "soc/dport_reg.h"
#include "soc/syscon_reg.h"
#include "soc/i2s_periph.h"
#include "esp_log.h"
#include "soc/apb_saradc_reg.h"
#include "esp_private/regi2c_ctrl.h"

2
components/esp_adc/CMakeLists.txt
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@@ -48,7 +48,7 @@ endif()
set(extra_requires)
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "esp32")
list(APPEND extra_requires esp_driver_i2s)
list(APPEND extra_requires esp_driver_i2s esp_hal_i2s)
endif()
if(${target} STREQUAL "esp32s2")
list(APPEND extra_requires esp_driver_spi)

2
components/esp_adc/esp32/adc_dma.c
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@@ -14,7 +14,7 @@
#include "hal/i2s_types.h"
#include "driver/i2s_types.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "esp_private/i2s_platform.h"
#include "esp_private/adc_dma.h"
#include "hal/i2s_ll.h"

2
components/esp_driver_dac/CMakeLists.txt
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@@ -6,7 +6,7 @@ set(priv_req esp_pm esp_driver_gpio)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
elseif(${target} STREQUAL "esp32")
list(APPEND priv_req esp_driver_i2s)
list(APPEND priv_req esp_driver_i2s esp_hal_i2s)
elseif(${target} STREQUAL "esp32s2")
list(APPEND priv_req esp_driver_spi)
endif()

2
components/esp_driver_dac/esp32/dac_dma.c
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@@ -18,7 +18,7 @@
#include "hal/i2s_hal.h"
#include "hal/i2s_types.h"
#include "hal/clk_tree_ll.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "../dac_priv_dma.h"
#include "esp_private/i2s_platform.h"
#include "esp_private/esp_clk.h"

2
components/esp_driver_dac/test_apps/dac/main/CMakeLists.txt
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@@ -8,6 +8,6 @@ endif()
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_pcnt esp_adc
PRIV_REQUIRES unity esp_driver_pcnt esp_adc esp_hal_i2s
esp_driver_dac esp_driver_gpio esp_driver_i2s esp_driver_spi
WHOLE_ARCHIVE)

2
components/esp_driver_dac/test_apps/dac/main/test_dac.c
View File

@@ -18,7 +18,7 @@
#if CONFIG_IDF_TARGET_ESP32
#include "esp_private/i2s_platform.h"
// Following headers are used to test the conversion frequency
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "driver/pulse_cnt.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp_private/spi_common_internal.h"

1
components/esp_driver_i2s/CMakeLists.txt
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@@ -37,5 +37,6 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${include}
PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
REQUIRES esp_hal_i2s
LDFRAGMENTS linker.lf
)

2
components/esp_driver_i2s/i2s_common.c
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@@ -21,7 +21,7 @@
#endif
#include "esp_log.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/soc_caps.h"
#include "soc/soc_caps_full.h"
#include "hal/i2s_hal.h"

2
components/esp_driver_i2s/lp_i2s.c
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@@ -28,7 +28,7 @@
#include "esp_private/i2s_platform.h"
#include "esp_private/lp_i2s_private.h"
#include "i2s_private.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#define LP_I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)

2
components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
View File

@@ -20,7 +20,7 @@
#include "unity.h"
#include "math.h"
#include "esp_rom_gpio.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "driver/i2s_std.h"
#if SOC_I2S_SUPPORTS_PDM
#include "driver/i2s_pdm.h"

40
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
View File

@@ -19,7 +19,6 @@
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "soc/soc_caps.h"
#include "soc/i2s_periph.h"
#include "soc/spi_periph.h"
#include "soc/parlio_periph.h"
#include "esp_attr.h"
@@ -96,20 +95,6 @@ static bool test_parlio_rx_timeout_callback(parlio_rx_unit_handle_t rx_unit, con
return false;
}
static void connect_signal_internally(uint32_t gpio, uint32_t sigo, uint32_t sigi)
{
gpio_config_t gpio_conf = {
.pin_bit_mask = BIT64(gpio),
.mode = GPIO_MODE_INPUT_OUTPUT,
.intr_type = GPIO_INTR_DISABLE,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
};
gpio_config(&gpio_conf);
esp_rom_gpio_connect_out_signal(gpio, sigo, false, false);
esp_rom_gpio_connect_in_signal(gpio, sigi, false);
}
#define TEST_EOF_DATA_LEN 64
static void pulse_delimiter_sender_task_i2s(void *args)
@@ -155,17 +140,6 @@ static void pulse_delimiter_sender_task_i2s(void *args)
// Transmission will start after enable the tx channel
TEST_ESP_OK(i2s_channel_enable(tx_chan));
// Connect GPIO signals
connect_signal_internally(TEST_CLK_GPIO,
i2s_periph_signal[TEST_I2S_PORT].m_tx_bck_sig,
parlio_periph_signals.groups[0].rx_units[0].clk_in_sig);
connect_signal_internally(TEST_VALID_GPIO,
i2s_periph_signal[TEST_I2S_PORT].m_tx_ws_sig,
parlio_periph_signals.groups[0].rx_units[0].data_sigs[TEST_VALID_SIG]);
connect_signal_internally(TEST_DATA0_GPIO,
i2s_periph_signal[TEST_I2S_PORT].data_out_sig,
parlio_periph_signals.groups[0].rx_units[0].data_sigs[0]);
while (!((*task_flags) & TEST_TASK_FINISHED_BIT)) {
vTaskDelay(pdMS_TO_TICKS(1));
*task_flags |= TEST_TASK_DATA_READY_BIT;
@@ -193,6 +167,20 @@ static void cs_low(spi_transaction_t *trans)
#define TEST_SPI_CLK_FREQ 100000
static void connect_signal_internally(uint32_t gpio, uint32_t sigo, uint32_t sigi)
{
gpio_config_t gpio_conf = {
.pin_bit_mask = BIT64(gpio),
.mode = GPIO_MODE_INPUT_OUTPUT,
.intr_type = GPIO_INTR_DISABLE,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
};
gpio_config(&gpio_conf);
esp_rom_gpio_connect_out_signal(gpio, sigo, false, false);
esp_rom_gpio_connect_in_signal(gpio, sigi, false);
}
static void level_delimiter_sender_task_spi(void *args)
{
uint32_t *task_flags = (uint32_t *)args;

25
components/esp_hal_i2s/CMakeLists.txt Normal file
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@@ -0,0 +1,25 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(srcs)
set(includes "include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
# I2S related source files
if(CONFIG_SOC_I2S_SUPPORTED)
list(APPEND srcs "i2s_hal.c" "${target}/i2s_periph.c")
endif()
if(CONFIG_SOC_LP_I2S_SUPPORTED)
list(APPEND srcs "lp_i2s_hal.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal)

48
components/esp_hal_i2s/README.md Normal file
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@@ -0,0 +1,48 @@
# ESP Hardware Abstraction Layer for I2S Peripheral(s)
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
## Overview
The `esp_hal_i2s` component provides a **Hardware Abstraction Layer** for Inter-IC Sound (I2S) controllers across all ESP-IDF supported targets. I2S is a serial bus interface standard used for connecting digital audio devices, enabling high-quality audio data transmission between integrated circuits.
## Architecture
The I2S HAL is structured in two main sub-layers:
1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control I2S peripherals (e.g., initialization, clock configuration, STD/TDM/PDM slot configuration, channel enable/disable).
2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
## Supported I2S Controllers
This HAL supports two I2S controller types depending on the ESP chip:
- **Standard I2S**: Traditional I2S interface supporting master/slave modes. And the different hardware versions are supported regarding different chips.
- **Low-Power I2S (LP I2S)**: Power-efficient I2S controller for low-power applications (on supported chips)
## Features
- **Multiple Audio Formats**:
- Standard I2S (STD) mode
- Pulse Density Modulation (PDM) mode
- Time Division Multiplexing (TDM) mode
- **Master/Slave Mode Support**: Configurable as master or slave device
- **Bidirectional Communication**: Independent TX and RX channel configuration
- **Clock Configuration**: Precise master clock (MCLK) and bit clock (BCLK) division
- **Slot Configuration**: Mono/stereo mode, slot selection, bit width configuration
- **PDM/PCM Converter Features**: PCM-to-PDM and PDM-to-PCM conversion, high-pass filtering (on supported chips)
- **TDM Features**: Multi-slot TDM support with configurable slot masks
- **Signal Connection Management**: GPIO signal mapping and interrupt configuration
## Usage
The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_driver_i2s`.
Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
## Dependencies
- `soc`: Provides chip-specific register definitions
- `hal`: Core hardware abstraction utilities and macros

2
components/soc/esp32/i2s_periph.c → components/esp_hal_i2s/esp32/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/gpio_sig_map.h"
/*

8
components/hal/esp32/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32/include/hal/i2s_ll.h
View File

@@ -16,7 +16,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/dport_reg.h"
#include "hal/i2s_types.h"
@@ -118,7 +118,6 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
i2s_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Reset the I2S module
*
@@ -916,8 +915,6 @@ static inline void i2s_ll_share_bck_ws(i2s_dev_t *hw, bool loopback_en)
hw->conf.sig_loopback = loopback_en;
}
/******************************I2S PDM Configurations*************************************/
/**
* @brief Configure RX PDM downsample
@@ -1095,9 +1092,6 @@ static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
return hw->pdm_freq_conf.tx_pdm_fs;
}
/****************************I2S ADC/DAC Configurations***********************************/
/**
* @brief Enable I2S LCD mode

2
components/soc/esp32c3/i2s_periph.c → components/esp_hal_i2s/esp32c3/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/gpio_sig_map.h"
/*

17
components/hal/esp32c3/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32c3/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/system_struct.h"
#include "hal/i2s_types.h"
@@ -39,7 +39,6 @@ extern "C" {
#define I2S_LL_DEFAULT_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_SUPPORT_XTAL 1 // Support XTAL as I2S clock source
/**
* @brief Enable the bus clock for I2S module
*
@@ -59,7 +58,6 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
i2s_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Reset the I2S module
*
@@ -231,8 +229,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
*/
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
hw->tx_clkm_conf.tx_clk_sel = 0;
break;
@@ -256,8 +253,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
*/
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
hw->rx_clkm_conf.rx_clk_sel = 0;
break;
@@ -629,8 +625,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -658,8 +653,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1049,7 +1043,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*

2
components/soc/esp32c5/i2s_periph.c → components/esp_hal_i2s/esp32c5/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"

48
components/hal/esp32c5/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32c5/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_struct.h"
@@ -52,7 +52,6 @@ extern "C" {
[I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_SENT, \
}}}[i2s_port][(chan_dir) - 1][event]
#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \
(uint32_t[SOC_I2S_ATTR(INST_NUM)][2][I2S_ETM_TASK_MAX]){{ \
[I2S_DIR_RX - 1] = { \
@@ -243,8 +242,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
break;
@@ -272,8 +270,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
break;
@@ -650,8 +647,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -679,8 +675,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1070,7 +1065,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*
@@ -1274,10 +1268,10 @@ static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st3.i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st3.i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1293,10 +1287,10 @@ static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st3.i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st3.i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1312,10 +1306,10 @@ static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st3.i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st3.i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
}
}
@@ -1331,10 +1325,10 @@ static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st3.i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st3.i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
}
}

2
components/soc/esp32c6/i2s_periph.c → components/esp_hal_i2s/esp32c6/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"

16
components/hal/esp32c6/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32c6/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_source.h"
@@ -51,7 +51,6 @@ extern "C" {
[I2S_ETM_EVENT_REACH_THRESH] = I2S_EVT_X_WORDS_SENT, \
}}}[i2s_port][(chan_dir) - 1][event]
#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \
(uint32_t[SOC_I2S_ATTR(INST_NUM)][2][I2S_ETM_TASK_MAX]){{ \
[I2S_DIR_RX - 1] = { \
@@ -241,8 +240,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
break;
@@ -270,8 +268,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
break;
@@ -648,8 +645,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -677,8 +673,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1068,7 +1063,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*

2
components/soc/esp32c61/i2s_periph.c → components/esp_hal_i2s/esp32c61/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"

48
components/hal/esp32c61/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32c61/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_struct.h"
@@ -53,7 +53,6 @@ extern "C" {
[I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_SENT, \
}}}[i2s_port][(chan_dir) - 1][event]
#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \
(uint32_t[SOC_I2S_ATTR(INST_NUM)][2][I2S_ETM_TASK_MAX]){{ \
[I2S_DIR_RX - 1] = { \
@@ -244,8 +243,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
break;
@@ -273,8 +271,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
break;
@@ -651,8 +648,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -680,8 +676,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1071,7 +1066,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*
@@ -1275,10 +1269,10 @@ static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st2.i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1294,10 +1288,10 @@ static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st2.i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1313,10 +1307,10 @@ static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
}
}
@@ -1332,10 +1326,10 @@ static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st2.i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
}
}

2
components/soc/esp32h2/i2s_periph.c → components/esp_hal_i2s/esp32h2/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"

16
components/hal/esp32h2/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32h2/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_source.h"
@@ -51,7 +51,6 @@ extern "C" {
[I2S_ETM_EVENT_REACH_THRESH] = I2S_EVT_X_WORDS_SENT, \
}}}[i2s_port][(chan_dir) - 1][event]
#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \
(uint32_t[SOC_I2S_ATTR(INST_NUM)][2][I2S_ETM_TASK_MAX]){{ \
[I2S_DIR_RX - 1] = { \
@@ -241,8 +240,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
break;
@@ -270,8 +268,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
break;
@@ -648,8 +645,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -677,8 +673,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1068,7 +1063,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*

2
components/soc/esp32h4/i2s_periph.c → components/esp_hal_i2s/esp32h4/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"

50
components/hal/esp32h4/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32h4/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/pcr_struct.h"
#include "soc/soc_etm_struct.h"
@@ -53,7 +53,6 @@ extern "C" {
[I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_SENT, \
}}}[i2s_port][(chan_dir) - 1][event]
#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \
(uint32_t[SOC_I2S_ATTR(INST_NUM)][2][I2S_ETM_TASK_MAX]){{ \
[I2S_DIR_RX - 1] = { \
@@ -245,8 +244,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
break;
@@ -274,8 +272,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void)hw;
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
break;
@@ -652,8 +649,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -681,8 +677,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1073,7 +1068,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*
@@ -1193,7 +1187,6 @@ static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t
hw->tx_pcm2pdm_conf.tx_pdm_dac_2out_en = line_mode != I2S_PDM_TX_ONE_LINE_DAC;
}
/**
* @brief Reset TX FIFO synchronization counter
*
@@ -1373,7 +1366,6 @@ static inline void i2s_ll_rx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
hw->etm_conf.etm_rx_receive_word_num = thresh;
}
/**
* @brief Get I2S ETM TX done event status
*
@@ -1386,10 +1378,10 @@ static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_tx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1405,10 +1397,10 @@ static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_rx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1424,10 +1416,10 @@ static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
}
}
@@ -1443,10 +1435,10 @@ static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.etm_evt_st4.etm_i2s0_evt_x_words_received_st;
default:
HAL_ASSERT(false);
}
}

2
components/soc/esp32p4/i2s_periph.c → components/esp_hal_i2s/esp32p4/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/lp_gpio_sig_map.h"

493
components/hal/esp32p4/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32p4/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/soc_etm_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -85,7 +85,6 @@ extern "C" {
}, \
}[i2s_port][(chan_dir) - 1][event]
#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task) \
(uint32_t[SOC_I2S_ATTR(INST_NUM)][2][I2S_ETM_TASK_MAX]){ \
[0] = { \
@@ -131,18 +130,18 @@ extern "C" {
static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
{
switch (i2s_id) {
case 0:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s0_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s0_mclk_en = enable;
return;
case 1:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s1_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s1_mclk_en = enable;
return;
case 2:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s2_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s2_mclk_en = enable;
return;
case 0:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s0_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s0_mclk_en = enable;
return;
case 1:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s1_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s1_mclk_en = enable;
return;
case 2:
HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s2_apb_clk_en = enable;
LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s2_mclk_en = enable;
return;
}
}
@@ -161,18 +160,18 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
static inline void i2s_ll_reset_register(int i2s_id)
{
switch (i2s_id) {
case 0:
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s0_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s0_apb = 0;
return;
case 1:
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s1_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s1_apb = 0;
return;
case 2:
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s2_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s2_apb = 0;
return;
case 0:
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s0_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s0_apb = 0;
return;
case 1:
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s1_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s1_apb = 0;
return;
case 2:
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s2_apb = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_i2s2_apb = 0;
return;
}
}
@@ -212,15 +211,15 @@ static inline void _i2s_ll_tx_enable_clock(i2s_dev_t *hw)
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_en = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_en = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_en = 1;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_en = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_en = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_en = 1;
return;
}
}
@@ -240,15 +239,15 @@ static inline void _i2s_ll_rx_enable_clock(i2s_dev_t *hw)
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_en = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_en = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_en = 1;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_en = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_en = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_en = 1;
return;
}
}
@@ -268,15 +267,15 @@ static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw)
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_en = 0;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_en = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_en = 0;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_en = 0;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_en = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_en = 0;
return;
}
}
@@ -296,15 +295,15 @@ static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_en = 0;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_en = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_en = 0;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_en = 0;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_en = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_en = 0;
return;
}
}
@@ -325,15 +324,15 @@ static inline void _i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
// Special on P4, set mst_clk_sel to 1 means attach the mclk signal to TX module
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_mst_clk_sel = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_mst_clk_sel = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_mst_clk_sel = 1;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_mst_clk_sel = 1;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_mst_clk_sel = 1;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_mst_clk_sel = 1;
return;
}
}
@@ -354,15 +353,15 @@ static inline void _i2s_ll_mclk_bind_to_rx_clk(i2s_dev_t *hw)
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
// Special on P4, set mst_clk_sel to 0 means attach the mclk signal to RX module
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_mst_clk_sel = 0;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_mst_clk_sel = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_mst_clk_sel = 0;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_mst_clk_sel = 0;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_mst_clk_sel = 0;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_mst_clk_sel = 0;
return;
}
}
@@ -441,26 +440,25 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
static inline uint32_t i2s_ll_get_clk_src(i2s_clock_src_t src)
{
switch (src)
{
case I2S_CLK_SRC_XTAL:
return 0;
case I2S_CLK_SRC_APLL:
return 1;
case I2S_CLK_SRC_EXTERNAL:
return 2;
case I2S_CLK_SRC_DEFAULT:
switch (src) {
case I2S_CLK_SRC_XTAL:
return 0;
case I2S_CLK_SRC_APLL:
return 1;
case I2S_CLK_SRC_EXTERNAL:
return 2;
case I2S_CLK_SRC_DEFAULT:
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
return 3;
// Only support PLL_160M on P4 ver3 and later
case I2S_CLK_SRC_PLL_160M:
return 3;
return 3;
// Only support PLL_160M on P4 ver3 and later
case I2S_CLK_SRC_PLL_160M:
return 3;
#else
return 0;
return 0;
#endif
default:
HAL_ASSERT(false && "unsupported clock source");
return -1;
default:
HAL_ASSERT(false && "unsupported clock source");
return -1;
}
}
@@ -475,15 +473,15 @@ static inline void _i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
uint32_t clk_src = i2s_ll_get_clk_src(src);
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_src_sel = clk_src;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_src_sel = clk_src;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_src_sel = clk_src;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_src_sel = clk_src;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_src_sel = clk_src;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_src_sel = clk_src;
return;
}
}
@@ -505,15 +503,15 @@ static inline void _i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
uint32_t clk_src = i2s_ll_get_clk_src(src);
switch (I2S_LL_GET_ID(hw)) {
case 0:
HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_src_sel = clk_src;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_src_sel = clk_src;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_src_sel = clk_src;
return;
case 0:
HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_src_sel = clk_src;
return;
case 1:
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_src_sel = clk_src;
return;
case 2:
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_src_sel = clk_src;
return;
}
}
@@ -549,54 +547,54 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, ui
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl13, reg_i2s0_tx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl13, reg_i2s0_tx_div_n, div_int);
return;
case 1:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl16, reg_i2s1_tx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl16, reg_i2s1_tx_div_n, div_int);
return;
case 2:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl18, reg_i2s2_tx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl18, reg_i2s2_tx_div_n, div_int);
return;
case 0:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl13, reg_i2s0_tx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s0_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl13, reg_i2s0_tx_div_n, div_int);
return;
case 1:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl16, reg_i2s1_tx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s1_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl16.reg_i2s1_tx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl16, reg_i2s1_tx_div_n, div_int);
return;
case 2:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl18, reg_i2s2_tx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl19.reg_i2s2_tx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl18, reg_i2s2_tx_div_n, div_int);
return;
}
}
@@ -614,54 +612,54 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, ui
{
// Note: this function involves HP_SYS_CLKRST register which is shared with other peripherals, need lock in upper layer
switch (I2S_LL_GET_ID(hw)) {
case 0:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl12, reg_i2s0_rx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl12, reg_i2s0_rx_div_n, div_int);
return;
case 1:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl14, reg_i2s1_rx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl14, reg_i2s1_rx_div_n, div_int);
return;
case 2:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl17, reg_i2s2_rx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl17, reg_i2s2_rx_div_n, div_int);
return;
case 0:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl12, reg_i2s0_rx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl12.reg_i2s0_rx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl12, reg_i2s0_rx_div_n, div_int);
return;
case 1:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl14, reg_i2s1_rx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_rx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl14, reg_i2s1_rx_div_n, div_int);
return;
case 2:
/* Workaround for the double division issue.
* The division coefficients must be set in particular sequence.
* And it has to switch to a small division first before setting the target division. */
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl17, reg_i2s2_rx_div_n, 2);
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_yn1 = 0;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_y = 1;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_z = 0;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_div_x = 0;
/* Set the target mclk division coefficients */
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_yn1 = yn1;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_z = z;
HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_rx_div_y = y;
HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_div_x = x;
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl17, reg_i2s2_rx_div_n, div_int);
return;
}
}
@@ -966,8 +964,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -995,8 +992,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1325,7 +1321,6 @@ static inline void i2s_ll_rx_set_pdm_amplify_num(i2s_dev_t *hw, uint32_t amp_num
hw->rx_pdm2pcm_conf.rx_pdm2pcm_amplify_num = amp_num;
}
/**
* @brief Set I2S RX PDM high pass filter param0
*
@@ -1359,7 +1354,6 @@ static inline void i2s_ll_rx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable)
hw->rx_pdm2pcm_conf.rx_pdm_hp_bypass = !enable;
}
/**
* @brief Configura TX a/u-law decompress or compress
*
@@ -1461,7 +1455,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*
@@ -1665,14 +1658,14 @@ static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st4.i2s0_evt_tx_done_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_tx_done_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_tx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st4.i2s0_evt_tx_done_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_tx_done_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_tx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1688,14 +1681,14 @@ static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st4.i2s0_evt_rx_done_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_rx_done_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_rx_done_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st4.i2s0_evt_rx_done_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_rx_done_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_rx_done_st;
default:
HAL_ASSERT(false);
}
}
@@ -1711,14 +1704,14 @@ static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st4.i2s0_evt_x_words_sent_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_x_words_sent_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st4.i2s0_evt_x_words_sent_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_x_words_sent_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_x_words_sent_st;
default:
HAL_ASSERT(false);
}
}
@@ -1734,14 +1727,14 @@ static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
{
uint32_t i2s_id = I2S_LL_GET_ID(hw);
switch (i2s_id) {
case 0:
return SOC_ETM.evt_st4.i2s0_evt_x_words_received_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_x_words_received_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_x_words_received_st;
default:
HAL_ASSERT(false);
case 0:
return SOC_ETM.evt_st4.i2s0_evt_x_words_received_st;
case 1:
return SOC_ETM.evt_st4.i2s1_evt_x_words_received_st;
case 2:
return SOC_ETM.evt_st4.i2s2_evt_x_words_received_st;
default:
HAL_ASSERT(false);
}
}

6
components/hal/esp32p4/include/hal/lp_i2s_ll.h → components/esp_hal_i2s/esp32p4/include/hal/lp_i2s_ll.h
View File

@@ -97,7 +97,6 @@ typedef enum {
LP_I2S_LL_RX_BIG_ENDIAN,
} lp_i2s_ll_rx_endian_t;
/*---------------------------------------------------------------
Mem
---------------------------------------------------------------*/
@@ -554,8 +553,7 @@ static inline void lp_i2s_ll_rx_select_std_chan(lp_i2s_dev_t *hw, i2s_std_slot_m
{
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1;
uint32_t mask = 0;
switch (chan_mask)
{
switch (chan_mask) {
case I2S_STD_SLOT_LEFT:
mask = 0x01;
break;
@@ -717,7 +715,7 @@ static inline uint32_t lp_i2s_ll_rx_get_interrupt_status(lp_i2s_dev_t *hw, bool
*/
static inline uint32_t lp_i2s_ll_get_intr_status_reg_addr(lp_i2s_dev_t *hw)
{
return (uint32_t)&(hw->int_st);
return (uint32_t) & (hw->int_st);
}
/**

2
components/soc/esp32s2/i2s_periph.c → components/esp_hal_i2s/esp32s2/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/gpio_sig_map.h"
/*

4
components/hal/esp32s2/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32s2/include/hal/i2s_ll.h
View File

@@ -16,7 +16,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
@@ -24,7 +24,6 @@
#include "hal/hal_utils.h"
#include "hal/assert.h"
#define I2S_LL_GET(_attr) I2S_LL_ ## _attr
#define I2S_LL_BUS_WIDTH 24
#define I2S_LL_INST_NUM 1
@@ -41,7 +40,6 @@ extern "C" {
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 64 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 6 bit-width
#define I2S_LL_EVENT_RX_EOF BIT(9)
#define I2S_LL_EVENT_TX_EOF BIT(12)
#define I2S_LL_EVENT_RX_DSCR_ERR BIT(13)

2
components/soc/esp32s3/i2s_periph.c → components/esp_hal_i2s/esp32s3/i2s_periph.c
View File

@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/gpio_sig_map.h"
/*

17
components/hal/esp32s3/include/hal/i2s_ll.h → components/esp_hal_i2s/esp32s3/include/hal/i2s_ll.h
View File

@@ -15,7 +15,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_struct.h"
#include "soc/system_struct.h"
#include "hal/i2s_types.h"
@@ -27,7 +27,6 @@
extern "C" {
#endif
#define I2S_LL_GET_HW(num) (((num) == 0) ? (&I2S0) : &I2S1)
#define I2S_LL_TDM_CH_MASK (0xffff)
@@ -40,7 +39,6 @@ extern "C" {
#define I2S_LL_DEFAULT_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_SUPPORT_XTAL 1 // Support XTAL as I2S clock source
/**
* @brief Enable the bus clock for I2S module
*
@@ -238,8 +236,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
*/
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
hw->tx_clkm_conf.tx_clk_sel = 0;
break;
@@ -266,8 +263,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
*/
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
switch (src)
{
switch (src) {
case I2S_CLK_SRC_XTAL:
hw->rx_clkm_conf.rx_clk_sel = 0;
break;
@@ -641,8 +637,7 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -670,8 +665,7 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
* Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
uint32_t chan_mask = 0;
switch (slot_mask)
{
switch (slot_mask) {
case I2S_STD_SLOT_LEFT:
chan_mask |= 0x01;
break;
@@ -1084,7 +1078,6 @@ static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
}
/**
* @brief Configure single data
*

5
components/hal/i2s_hal.c → components/esp_hal_i2s/i2s_hal.c
View File

@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for I2S (common part)
#include "soc/soc.h"
@@ -166,7 +165,7 @@ void i2s_hal_std_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
i2s_ll_tx_enable_mono_mode(hal->dev, is_copy_mono);
i2s_ll_tx_select_std_slot(hal->dev, is_copy_mono ? I2S_STD_SLOT_LEFT : slot_cfg->std.slot_mask);
i2s_ll_tx_set_skip_mask(hal->dev, (slot_cfg->std.slot_mask != I2S_STD_SLOT_BOTH) &&
(slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO));
(slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO));
i2s_ll_tx_set_half_sample_bit(hal->dev, slot_bit_width);
i2s_ll_tx_set_ws_idle_pol(hal->dev, slot_cfg->std.ws_pol);
i2s_ll_tx_set_bit_order(hal->dev, slot_cfg->std.bit_order_lsb);
@@ -292,7 +291,7 @@ void i2s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
i2s_ll_rx_enable_mono_mode(hal->dev, false);
#if SOC_I2S_PDM_MAX_RX_LINES > 1
uint32_t slot_mask = (slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO && slot_cfg->pdm_rx.slot_mask <= I2S_PDM_SLOT_BOTH) ?
I2S_PDM_SLOT_BOTH : slot_cfg->pdm_rx.slot_mask;
I2S_PDM_SLOT_BOTH : slot_cfg->pdm_rx.slot_mask;
#else
/* Set the channel mask to enable corresponding slots, always enable two slots for stereo mode */
uint32_t slot_mask = slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO ? I2S_PDM_SLOT_BOTH : slot_cfg->pdm_rx.slot_mask;

0
components/soc/include/soc/i2s_periph.h → components/esp_hal_i2s/include/hal/i2s_periph.h
View File

1
components/hal/include/hal/i2s_types.h → components/esp_hal_i2s/include/hal/i2s_types.h
View File

@@ -70,7 +70,6 @@ typedef soc_periph_i2s_clk_src_t i2s_clock_src_t; /*!< I2S clock source */
typedef int i2s_clock_src_t; /*!< Define a default type to avoid compiling warnings */
#endif
#if SOC_I2S_SUPPORTS_PCM
/**
* @brief A/U-law decompress or compress configuration.

0
components/hal/lp_i2s_hal.c → components/esp_hal_i2s/lp_i2s_hal.c
View File

2
components/esp_hal_lcd/CMakeLists.txt
View File

@@ -28,4 +28,4 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include}
REQUIRES soc hal)
REQUIRES soc hal esp_hal_i2s)

2
components/esp_hw_support/port/esp32/rtc_sleep.c
View File

@@ -8,7 +8,7 @@
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/dport_reg.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/bb_reg.h"
#include "soc/nrx_reg.h"
#include "soc/fe_reg.h"

16
components/hal/CMakeLists.txt
View File

@@ -3,6 +3,12 @@ idf_build_get_property(esp_tee_build ESP_TEE_BUILD)
set(srcs "hal_utils.c")
set(includes "platform_port/include")
set(requires soc esp_rom)
if(${target} STREQUAL "esp32")
# TODO: IDF-14079 remove this dependency when ADC hal is graduated from the common hal component
list(APPEND requires esp_hal_i2s)
endif()
# target specific include must be added before the generic one
# because of the "include_next" directive used by the efuse_hal.h
@@ -95,10 +101,6 @@ elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "isp_hal.c")
endif()
if(CONFIG_SOC_LP_I2S_SUPPORTED)
list(APPEND srcs "lp_i2s_hal.c")
endif()
if(CONFIG_SOC_RMT_SUPPORTED)
list(APPEND srcs "rmt_hal.c")
endif()
@@ -107,10 +109,6 @@ elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "uhci_hal.c")
endif()
if(CONFIG_SOC_I2S_SUPPORTED)
list(APPEND srcs "i2s_hal.c")
endif()
if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
list(APPEND srcs "sdmmc_hal.c")
endif()
@@ -238,7 +236,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
PRIV_INCLUDE_DIRS ${priv_include}
REQUIRES soc esp_rom
REQUIRES ${requires}
PRIV_REQUIRES esp_hal_gpio
LDFRAGMENTS linker.lf)

4
components/soc/CMakeLists.txt
View File

@@ -96,10 +96,6 @@ if(CONFIG_SOC_ISP_SUPPORTED)
list(APPEND srcs "${target}/isp_periph.c")
endif()
if(CONFIG_SOC_I2S_SUPPORTED)
list(APPEND srcs "${target_folder}/i2s_periph.c")
endif()
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "${target_folder}/i3c_master_periph.c")
endif()

3
docs/doxygen/Doxyfile
View File

@@ -168,6 +168,8 @@ INPUT = \
$(PROJECT_PATH)/components/esp_hal_gpio/include/hal/sdm_types.h \
$(PROJECT_PATH)/components/esp_hal_timg/include/hal/timer_types.h \
$(PROJECT_PATH)/components/esp_hal_i2c/include/hal/i2c_types.h \
$(PROJECT_PATH)/components/esp_hal_i2s/include/hal/i2s_types.h \
$(PROJECT_PATH)/components/esp_hal_jpeg/include/hal/jpeg_types.h \
$(PROJECT_PATH)/components/esp_hal_lcd/include/hal/lcd_types.h \
$(PROJECT_PATH)/components/esp_hal_mspi/include/hal/esp_flash_err.h \
$(PROJECT_PATH)/components/esp_hal_mspi/include/hal/spi_flash_types.h \
@@ -259,7 +261,6 @@ INPUT = \
$(PROJECT_PATH)/components/hal/include/hal/adc_types.h \
$(PROJECT_PATH)/components/hal/include/hal/color_types.h \
$(PROJECT_PATH)/components/hal/include/hal/dac_types.h \
$(PROJECT_PATH)/components/hal/include/hal/i2s_types.h \
$(PROJECT_PATH)/components/hal/include/hal/ledc_types.h \
$(PROJECT_PATH)/components/hal/include/hal/mcpwm_types.h \
$(PROJECT_PATH)/components/hal/include/hal/parlio_types.h \

2
docs/en/api-reference/peripherals/i2s.rst
View File

@@ -1279,4 +1279,4 @@ I2S Types
^^^^^^^^^
.. include-build-file:: inc/components/esp_driver_i2s/include/driver/i2s_types.inc
.. include-build-file:: inc/components/hal/include/hal/i2s_types.inc
.. include-build-file:: inc/components/esp_hal_i2s/include/hal/i2s_types.inc

2
docs/zh_CN/api-reference/peripherals/i2s.rst
View File

@@ -1279,4 +1279,4 @@ I2S 类型
^^^^^^^^
.. include-build-file:: inc/components/esp_driver_i2s/include/driver/i2s_types.inc
.. include-build-file:: inc/components/hal/include/hal/i2s_types.inc
.. include-build-file:: inc/components/esp_hal_i2s/include/hal/i2s_types.inc