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46,400 Commits 22 Branches 174 Tags
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3509 Commits

Author SHA1 Message Date
morris
ded4814c8d Merge branch 'fix/update_breakpoint_nums_on_c5_h4_v5.5' into 'release/v5.5' 
fix(soc): update breakpoint nums on c5 and h4 (v5.5)

See merge request espressif/esp-idf!44356
 2025-12-30 12:19:23 +08:00
morris
1851470481 Merge branch 'feat/p4eco6_ldo2dcdc_support_v5.5' into 'release/v5.5' 
feat (p4eco6): open dcdc switch by software when dcdc stable (v5.5)

See merge request espressif/esp-idf!44578
 2025-12-29 11:18:37 +08:00
Chen Jichang
2ff54ff5c5 fix(soc): update breakpoint nums on c5 and h4 2025-12-29 10:31:32 +08:00
Island
da5ff0c78c Merge branch 'fix/add_soc_caps_for_pawr_feat_v5.5' into 'release/v5.5' 
fix(ble): add soc caps feat for PAwR (v5.5)

See merge request espressif/esp-idf!44150
 2025-12-26 14:21:25 +08:00
chaijie@espressif.com
3fb705d852 feat (p4eco6): open dcdc switch by software when dcdc stable 2025-12-26 09:54:02 +08:00
morris
2a481f5bc7 Merge branch 'feat/isp_crop_driver_v5.5' into 'release/v5.5' 
feat(isp): support Crop driver on p4 rev3 (v5.5)

See merge request espressif/esp-idf!43446
 2025-12-26 09:51:13 +08:00
Chen Jichang
3678a25e4c fix(gdma): fix set dma burst size failure on p4 v3.0 2025-12-23 11:22:47 +08:00
Xiao Xufeng
faf6cc4f84 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 03:33:29 +08:00
Chen Chen
c9c25684ca feat(isp): support Crop driver on p4 rev3 
Add support for crop driver on p4eco5 and update example in
`isp/multi_pipelines`
 2025-12-15 15:11:45 +08:00
sibeibei
0f07ad18b6 fix: add mutex protection for software trigger RegDMA start to avoid data races 2025-12-11 20:32:53 +08:00
Jin Chen
7569042a61 fix(ble): add soc caps config for pawr feat on ESP32C61 
(cherry picked from commit d667a41826)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:10 +08:00
Jin Chen
0cce37f934 fix(ble): add soc caps config for pawr feat on ESP32C5 
(cherry picked from commit 19130df4f3)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:09 +08:00
Jin Chen
a6aa9bf7f5 fix(ble): add soc caps config for pawr feat on ESP32H2 
(cherry picked from commit 2eb79c71f1)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:08 +08:00
Jin Chen
b0b2130475 fix(ble): add soc caps config for pawr feat on ESP32C6 
(cherry picked from commit 4e4b863299)

Co-authored-by: cjin <jinchen@espressif.com>
 2025-12-11 16:23:07 +08:00
Jiang Jiang Jian
ddb9f5d9dc Merge branch 'fix/fix_mspi_write_stuck_after_reset_v5.5' into 'release/v5.5' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v5.5)

See merge request espressif/esp-idf!43732
 2025-12-04 10:34:56 +08:00
wuzhenghui
104145de7f fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-02 13:34:17 +08:00
gaoxu
dfef29c007 feat(rng): support P4 ECO5 TRNG 2025-12-01 15:31:44 +08:00
morris
1d5fcc6d2e Merge branch 'bugfix/uart_related_backports_v5.5' into 'release/v5.5' 
fix(uart): some related uart backports (v5.5)

See merge request espressif/esp-idf!43617
 2025-11-27 10:52:38 +08:00
Song Ruo Jing
0c15b9f6a4 refactor(ppa): avoid the use of yuv422_pack_order field in PPA driver 2025-11-24 11:41:26 +08:00
armando
304ebc0c74 change(p4): make v3 as default 2025-11-20 11:33:36 +08:00
morris
7b2f4f2b88 Merge branch 'fix/mipi_dsi_phy_clk_type_v5.5' into 'release/v5.5' 
fix(lcd): fix mipi dsi phy type for p4 version below 3.0 (v5.5)

See merge request espressif/esp-idf!43354
 2025-11-14 18:21:55 +08:00
morris
1c4f1f47cc Merge branch 'feature/esp32p4_eco5_io_hold_v5.5' into 'release/v5.5' 
feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 (v5.5)

See merge request espressif/esp-idf!43308
 2025-11-14 15:22:50 +08:00
Chen Jichang
f04318c605 fix(lcd): fix mipi dsi phy type for p4 version below 3.0 2025-11-14 11:07:26 +08:00
Michael (XIAO Xufeng)
c51b5e955a Merge branch 'feature/support_efuses_esp32p4_eco5_v5.5' into 'release/v5.5' 
feat(efuse): Support efuses for ESP32-P4 ECO5 (v5.5)

See merge request espressif/esp-idf!42651
 2025-11-13 17:11:10 +08:00
Song Ruo Jing
ea09a117ee feat(gpio): ESP32P4 ECO5 GPIO related update 2025-11-13 11:36:22 +08:00
Song Ruo Jing
9589ab5361 feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 2025-11-13 11:36:15 +08:00
harshal.patil
317a6f074d fix(mbedtls/port): Align AES and SHA DMA buffers to 16 when SPIRAM encryption is enabled 
- Targets that support GDMA and MSPI encryption module need data and addresses aligned to 16
 2025-11-11 17:45:11 +05:30
Michael (XIAO Xufeng)
d1e854920a Merge branch 'feat/p4_rev3_isp_awb_wbg_v5.5' into 'release/v5.5' 
isp: awb white balance gain feature and subwindow feature support on P4 ECO5 (v5.5)

See merge request espressif/esp-idf!42799
 2025-11-11 11:17:36 +08:00
Michael (XIAO Xufeng)
e66fc82cb7 Merge branch 'bugfix/fixed_possible_i2s_failure_on_p4_v5.5' into 'release/v5.5' 
ci(i2s): fixed occationally failure on P4 (v5.5)

See merge request espressif/esp-idf!42951
 2025-11-10 10:49:10 +08:00
armando
703da8c2c5 change(isp): make wbg standalone 2025-11-07 10:16:59 +08:00
armando
4cd83738f9 feat(isp): support AWB driver setting wbgain and subwindow feature 2025-11-07 10:16:56 +08:00
Konstantin Kondrashov
0f22c814b9 feat(efuse): Adds calibration efuses for ESP32-P4 ECO5 2025-11-05 11:58:00 +02:00
laokaiyao
5dc3eda4ad ci(i2s): fixed occationally failure on P4 
read write case can sometimes failed due to the low frequency of the default I2S clock source on P4.
 2025-11-04 11:07:11 +08:00
nilesh.kale
cf98517de1 feat: added test_cases for ECC P-384 curve operations 2025-10-31 10:38:52 +05:30
nilesh.kale
cf8068df75 feat(hal): add support for ESP32-P4 ECO5 ECC peripheral 
This commit also enabled constant time mode for ECC.
 2025-10-31 10:38:52 +05:30
wuzhenghui
72ea3de736 change(esp_hw_support): set HP/LP mem in retention mode in sleep 2025-10-29 17:22:19 +08:00
morris
5ab2e6e07e Merge branch 'feat/support_parlio_cs_on_p4_eco5_v5.5' into 'release/v5.5' 
feat(parlio_tx): support cs signal on esp32p4 eco5 (v5.5)

See merge request espressif/esp-idf!42781
 2025-10-28 11:08:21 +08:00
morris
4d14019457 Merge branch 'fix/p4_edma_size_v5.5' into 'release/v5.5' 
fix(gdma): correct the max burst size of p4 edma (v5.5)

See merge request espressif/esp-idf!41799
 2025-10-28 10:29:26 +08:00
morris
a0de5f7387 Merge branch 'feature/esp32p4_eco5_support_v5.5' into 'release/v5.5' 
feat(gpio/ledc/uart/2ddma/ppa): ESP32P4 ECO5 related updates (v5.5)

See merge request espressif/esp-idf!42816
 2025-10-27 15:50:42 +08:00
Jiang Jiang Jian
e2748c1c82 Merge branch 'fix/correct_adc_periph_num_on_c2_v5.5' into 'release/v5.5' 
fix(adc): fix ESP32-C2/P4 wrong adc periph num (v5.5)

See merge request espressif/esp-idf!41536
 2025-10-27 14:59:41 +08:00
morris
18531ed87e Merge branch 'feat/jpeg_eco5_v5.5' into 'release/v5.5' 
feat(jpeg): Add yuv444 yuv420 format support for encoder on esp32p4 eco5 , Add check for jpeg marker parser in order to enhance safety (backport v5.5)

See merge request espressif/esp-idf!42668
 2025-10-27 14:55:10 +08:00
Jiang Jiang Jian
6cb1869480 Merge branch 'feat/support_esp32p4_eco5_pmu_v5.5' into 'release/v5.5' 
feat(esp_hw_support): update esp32p4 eco5 lowpower features support  (v5.5)

See merge request espressif/esp-idf!42685
 2025-10-27 14:47:33 +08:00
morris
2df21069da Merge branch 'feat/spi_p4_eco5_support_v5.5' into 'release/v5.5' 
feat(driver_spi): update p4 eco5 spi and twai support (v5.5)

See merge request espressif/esp-idf!42805
 2025-10-27 14:22:46 +08:00
Chen Jichang
1597f60d52 feat(parlio_tx): support cs signal on esp32p4 eco5 2025-10-27 10:09:00 +08:00
morris
64f5d8da51 Merge branch 'fix/fix_xip_power_reset_stuck_issue_p4_rev3_v5.5' into 'release/v5.5' 
psram: fixed p4 rev3 xip stuck after board reset issue (v5.5)

See merge request espressif/esp-idf!42806
 2025-10-27 09:53:24 +08:00
morris
fb5d9af807 Merge branch 'feat/p4_eco5_pcnt_v5.5' into 'release/v5.5' 
feat(pcnt,mcpwm,rmt): update struct on p4 eco5 (v5.5)

See merge request espressif/esp-idf!42789
 2025-10-24 19:38:52 +08:00
morris
c048785509 Merge branch 'feat/p4_rev3_csi_v5.5' into 'release/v5.5' 
csi: support on p4 eco5 (v5.5)

See merge request espressif/esp-idf!42788
 2025-10-24 18:35:36 +08:00
morris
dfa0b751a0 Merge branch 'feature/support_i2s_on_p4_eco5_v5.5' into 'release/v5.5' 
change(i2s): update i2s soc and hal for p4 hw_ver3 (v5.5)

See merge request espressif/esp-idf!42738
 2025-10-24 16:40:50 +08:00
morris
25c6d757be Merge branch 'feature/support_touch_on_p4_eco5_v5.5' into 'release/v5.5' 
feat(touch): support touch sensor on p4 eco5 (v5.5)

See merge request espressif/esp-idf!42740
 2025-10-24 12:23:52 +08:00
morris
c38222d614 Merge branch 'feat/mspi_suspend_p4_eco5_v5.5' into 'release/v5.5' 
feat(spi_flash): Support flash suspend on esp32p4 resivion 3  etc (backport v5.5)

See merge request espressif/esp-idf!42690
 2025-10-24 12:12:41 +08:00