yanzihan@espressif.com
34b8f67a89
feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32p4
2025-06-25 18:22:02 +08:00
Jiang Jiang Jian
ee04629723
Merge branch 'feat/some_xip_psram_related_optimisations_and_fixes_v5.4' into 'release/v5.4'
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feat(esp_psram): Add some wasted XIP PSRAM memory in heap and PSRAM protection (v5.4)
See merge request espressif/esp-idf!38872
2025-05-26 19:46:08 +08:00
Li Shuai
7014cfc831
fix(esp_hw_support): fix modem wakeup req always high caused by pmu min slp cycle update
2025-05-07 14:25:05 +08:00
Li Shuai
d5ff59f144
change(esp_hw_support): add interface to calculate slow clock period by clock frequency
2025-05-07 14:15:20 +08:00
harshal.patil
9406fde68d
feat(cpu_region_protect): Enable basic memory protection for SPIRAM
2025-05-05 11:52:04 +05:30
wuzhenghui
dbd4934205
fix(esp_hw_support): specify optimize options to avoid dirtying L2 mem after L1D$ writeback
2025-04-25 17:13:27 +08:00
wuzhenghui
8cfe912053
fix(esp_hw_support): fix wrong APB clock freq on retenion
2025-04-25 17:13:26 +08:00
wuzhenghui
81860c55d6
feat(esp_hw_support): use non-lock regi2c fast-up cpll/mpll enable process after sleep wakeup
2025-04-25 17:13:22 +08:00
Jiang Jiang Jian
19e864060a
Merge branch 'fix/rmii_ref_ckl_v5.4' into 'release/v5.4'
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fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode (v5.4)
See merge request espressif/esp-idf!38039
2025-04-07 13:58:48 +08:00
Ondrej Kosta
e544d57179
fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode
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fixed units returned and used by periph_rtc_mpll_freq_set function
2025-04-01 08:32:09 +02:00
morris
8bce1430ee
Merge branch 'bugfix/lp_uart_baudrate_limitation_v5.4' into 'release/v5.4'
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fix(uart): LP UART does not have the pre-divider for its clock source (v5.4)
See merge request espressif/esp-idf!37594
2025-04-01 10:35:29 +08:00
wuzhenghui
7f88cf3ee9
change(esp_hw_support): only do mpll disable in lightsleep process
2025-03-08 14:06:12 +08:00
Song Ruo Jing
d8c1d9f603
fix(gpio): fix bad bit shift operation and OOB (h2) in io_mux.c
2025-03-07 21:16:18 +08:00
wuzhenghui
8e6ec50bcc
fix(esp_hw_support): fix esp32s2/esp32s3 RTC IOMUX clock management
2025-02-21 09:50:42 +08:00
Jiang Jiang Jian
f9ae8dfb04
Merge branch 'fix/esp32p4_lightsleep_fixes_v5.4' into 'release/v5.4'
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fix(esp_hw_support): some fixes of esp32p4 lightsleep retention & power switch process (v5.4)
See merge request espressif/esp-idf!37086
2025-02-20 13:48:50 +08:00
Jiang Jiang Jian
23db06892b
Merge branch 'feat/wait_pll_stable_after_sleep_wakeup_fix_xtal_v5.4' into 'release/v5.4'
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feat(esp_hw_support): wait pll stable after sleep wakeup (v5.4)
See merge request espressif/esp-idf!36018
2025-02-20 10:36:20 +08:00
wuzhenghui
b654a78646
change(esp_hw_support): wrapper sleep dcdc/ldo ops with ll
2025-02-19 14:32:22 +08:00
wuzhenghui
a63e9c5aef
fix(esp_hw_support): fix DCDC switch bad software powerdown
2025-02-19 14:32:15 +08:00
wuzhenghui
4542c463c6
change(esp_hw_support): not use ROM Cache invalidate in sleep process to avoid dirtying the L1 Cache
2025-02-19 14:32:12 +08:00
wuzhenghui
95fb085fe3
fix(esp_hw_support): add timer wakeup sleep duration check
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Closes https://github.com/espressif/esp-idf/issues/15255
2025-02-18 19:21:57 +08:00
wuzhenghui
003a7f6bcb
fix(esp_hw_support): fix lp/hp clock wait time calculation after wait pll ready
2025-02-17 16:53:28 +08:00
wuzhenghui
67a4de4e77
change(esp_hw_support): switch to sleep_flags earlier to identify sleep state
2025-02-17 16:53:28 +08:00
wuzhenghui
87c4227e44
change(esp_hw_support): wait pll calibration done in regdma link instead of wait fixed value
2025-02-17 16:53:27 +08:00
Jiang Jiang Jian
7cd2a1483e
Merge branch 'fix/fix_p4_deepsleep_io_leakage_v5.4' into 'release/v5.4'
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fix(esp_hw_support): fix esp32p4 JTAG pad deepsleep current leakage (v5.4)
See merge request espressif/esp-idf!36008
2025-01-07 10:53:13 +08:00
morris
cd1ce6164b
Merge branch 'refactor/fine_tune_dphy_pll_v5.4' into 'release/v5.4'
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feat(mipi): fine tune DPHY PLL clock (v5.4)
See merge request espressif/esp-idf!35291
2025-01-06 13:20:01 +08:00
wuzhenghui
c7c70a8ec6
fix(esp_hw_support): fix esp32p4 JTAG pad deepsleep current leakage
2024-12-26 16:03:42 +08:00
Song Ruo Jing
623351e791
fix(clk): add an inevitable kconfig option to be selected to use rc32k
2024-12-02 11:15:17 +08:00
morris
e7b555de8d
feat(mipi): fine tune DPHY PLL clock
2024-11-30 00:29:15 +08:00
Armando
04cd469e4a
feat(sdmmc): supported UHS-I SDR50 (100Mhz) and DDR50 mode
2024-11-13 11:12:10 +08:00
wuzhenghui
2558760224
fix(esp_hw_support): fix writeback cache to psram after vo2 powerdown
2024-11-04 14:08:28 +08:00
wuzhenghui
a1f9d5bcea
feat(esp_hw_support): support power down PSRAM or Flash during sleep for esp32p4 v1.0
2024-10-23 19:10:42 +08:00
zlq
da9521aef3
fix(pmu): modify parameter for P4 ECO2-VO1
2024-10-23 16:03:21 +08:00
Song Ruo Jing
ed91ad56da
Merge branch 'refactor/pll_pd_in_sleep_logic' into 'master'
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fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL
See merge request espressif/esp-idf!34241
2024-10-18 14:12:15 +08:00
Song Ruo Jing
7c0b1dc98c
fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL
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Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips
For PMU supported chips, powering down CPU PLL in sleep will be done by PMU, not sleep code
2024-10-17 12:41:15 +08:00
Song Ruo Jing
67a87a5fcd
fix(pmu): enable all func clock icg during retention
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This should only increase a tiny amount of the power consumption in the retention process,
but save debug time since some module register read/write relies not only APB but also func clock.
2024-10-17 12:41:15 +08:00
Armando
6db48cff25
feat(sleep): support vad wakeup hp core
2024-10-16 17:27:27 +08:00
C.S.M
99f1eace07
feat(bod): Update bod threshold on esp32p4-eco2
2024-10-12 18:03:24 +08:00
Jiang Jiang Jian
12cbdfef31
Merge branch 'feature/set_lp_cpu_power_mode_with_clock_src' into 'master'
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change(esp_hw_support): switch lp_cpu power mode with clock src selection to save lp_cpu working power
Closes AEG-1430
See merge request espressif/esp-idf!30556
2024-09-29 18:32:32 +08:00
wuzhenghui
6520c61cff
change(esp_hw_support): improve gpio deepsleep wakeup configuration code
2024-09-29 16:56:42 +08:00
wuzhenghui
9ffd8aa017
fix(esp_hw_support): fix coverity defects in sleep code
2024-09-29 16:56:42 +08:00
wuzhenghui
e1a341455a
fix(esp_hw_support): fix esp32p4 CPU frequency switching timing
2024-09-26 14:57:03 +08:00
wuzhenghui
04b2afed44
change(esp_hw_support): switch lp_cpu power mode with clock src to save lp_cpu working power
2024-09-26 11:23:06 +08:00
wuzhenghui
ef4c02dda2
revert(esp_hw_support): stall another core during cpu/mem/apb freq switching
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This reverts commit c2bb64fbe8
2024-09-25 20:19:15 +08:00
Mahavir Jain
2a6be654cd
Merge branch 'ci/enable_memprot_tests_for_esp32c61' into 'master'
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Clear PMA entries before usage and enable tests for ESP32-C61
Closes IDF-10932
See merge request espressif/esp-idf!33438
2024-09-20 21:32:18 +08:00
Marius Vikhammer
564d777018
Merge branch 'feature/lp_core_40_mhz' into 'master'
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feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
Closes IDF-10203
See merge request espressif/esp-idf!32450
2024-09-20 10:57:15 +08:00
Marius Vikhammer
00eb97725b
feat(system): support choosing xtal as rtc-fast clock src on P4 and C5
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With xtal as rtc-fast clock source the LP-Core can run at twice the default
clock frequency. 40 MHz as opposed to 20 MHz.
2024-09-19 17:30:44 +08:00
harshal.patil
7667d9ebbe
fix(cpu_region_protect): Reset PMA entries before using them
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- ROM uses some PMA entries so we clear such PMA entries before using them in ESP-IDF
2024-09-18 10:25:18 +05:30
Marius Vikhammer
5486653a18
Merge branch 'contrib/github_pr_14422' into 'master'
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feat(esp_system,ulp): LP core reserved mem optionally executable from HP core (GitHub PR)
Closes IDFGH-13533
See merge request espressif/esp-idf!33139
2024-09-12 09:10:22 +08:00
wuzhenghui
13e42707a0
feat(esp_hw_support): add clk tree source gate management api
2024-09-11 10:53:01 +08:00
wuzhenghui
05e74480f5
feat(esp_system): gate some clock by default to optmize esp32p4 active power
2024-09-11 10:53:00 +08:00
