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85 lines
3.2 KiB
C
85 lines
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdlib.h>
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#include <stdint.h>
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#include "esp_err.h"
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Cache msync flags
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*/
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/**
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* @brief Do an invalidation
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* - For cache-to-memory (C2M) direction: setting this flag will start an invalidation after the cache writeback operation
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* - For memory-to-cache (M2C) direction: setting / unsetting this flag will behave similarly, trigger an invalidation
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*/
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#define ESP_CACHE_MSYNC_FLAG_INVALIDATE BIT(0)
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/**
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* @brief Allow msync to a address block that are not aligned to the data cache line size
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*/
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#define ESP_CACHE_MSYNC_FLAG_UNALIGNED BIT(1)
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/**
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* @brief Cache msync direction: from Cache to memory
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* @note If you don't set direction (ESP_CACHE_MSYNC_FLAG_DIR_x flags), it is by default cache-to-memory (C2M) direction
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*/
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#define ESP_CACHE_MSYNC_FLAG_DIR_C2M BIT(2)
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/**
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* @brief Cache msync direction: from memory to Cache
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*/
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#define ESP_CACHE_MSYNC_FLAG_DIR_M2C BIT(3)
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/**
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* @brief Cache msync type: data
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* @note If you don't set type (ESP_CACHE_MSYNC_FLAG_TYPE_x flags), it is by default data type
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*/
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#define ESP_CACHE_MSYNC_FLAG_TYPE_DATA BIT(4)
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/**
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* @brief Cache msync type: instruction
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*/
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#define ESP_CACHE_MSYNC_FLAG_TYPE_INST BIT(5)
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/**
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* @brief Memory sync between Cache and storage memory
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*
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*
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* For cache-to-memory (C2M) direction:
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* - For cache writeback supported chips (you can refer to SOC_CACHE_WRITEBACK_SUPPORTED in soc_caps.h)
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* - This API will do a writeback to synchronise between cache and storage memory
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* - With ESP_CACHE_MSYNC_FLAG_INVALIDATE, this API will also invalidate the values that just written
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* - Note: although ESP32 is with PSRAM, but cache writeback isn't supported, so this API will do nothing on ESP32
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* - For other chips, this API will do nothing. The out-of-sync should be already dealt by the SDK
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*
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* For memory-to-cache (M2C) direction:
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* - This API will by default do an invalidation
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*
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* This API is cache-safe and thread-safe
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*
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* @note If you don't set direction (ESP_CACHE_MSYNC_FLAG_DIR_x flags), this API is by default C2M direction
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* @note If you don't set type (ESP_CACHE_MSYNC_FLAG_TYPE_x flags), this API is by default doing msync for data
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* @note You should not call this during any Flash operations (e.g. esp_flash APIs, nvs and some other APIs that are based on esp_flash APIs)
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* @note If XIP_From_PSRAM is enabled (by enabling both CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA), you can call this API during Flash operations
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*
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* @param[in] addr Starting address to do the msync
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* @param[in] size Size to do the msync
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* @param[in] flags Flags, see `ESP_CACHE_MSYNC_FLAG_x`
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*
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* @return
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* - ESP_OK:
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* - Successful msync
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* - For C2M direction, if this chip doesn't support cache writeback, if the input addr is a cache supported one, this API will return ESP_OK
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* - ESP_ERR_INVALID_ARG: Invalid argument, not cache supported addr, see printed logs
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*/
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esp_err_t esp_cache_msync(void *addr, size_t size, int flags);
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#ifdef __cplusplus
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}
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#endif
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