Ivan Grokhotkov 73e8afc5b9 soc: place constant data from rtc_clk.c into DRAM ...

In release mode, switches in rtc_clk_bbpll_set would be converted to
jump tables. These tables would be placed into .rodata, which caused
rtc_clk_cpu_freq_set to be unusable while cache is disabled. This
manifested itself in crashes when exiting from light sleep:

https://esp32.com/posting.php?mode=reply&f=13&t=3089#pr14590

2017-09-26 17:08:49 +08:00

..

elf_to_ld.sh

Initial public version

2016-08-17 23:08:22 +08:00

esp32.common.ld

soc: place constant data from rtc_clk.c into DRAM

2017-09-26 17:08:49 +08:00

esp32.ld

Provide a default for CONFIG_BT_RESERVE_DRAM

2017-08-30 17:55:00 +10:00

esp32.peripherals.ld

driver(touch): fix bug and add more features

2017-08-22 21:21:39 +08:00

esp32.rom.ld

component/bt : support adv & scan simultaneously

2017-09-12 16:10:30 +08:00

esp32.rom.nanofmt.ld

newlib: add "full" formatting support, add missing functions

2016-12-08 11:04:54 +08:00

esp32.rom.spiflash.ld

spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions

2017-04-13 17:54:42 +10:00

esp32.rom.spiram_incompatible_fns.ld

Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

2017-09-04 12:05:49 +08:00

esp32.spiram.rom-functions-dram.ld

Make sure functions that are in ROM in the non-external-ram-workaround version, are in RAM (and not in flash) in the ext-ram workaround version.

2017-09-13 10:36:56 +08:00

esp32.spiram.rom-functions-iram.ld

Make sure functions that are in ROM in the non-external-ram-workaround version, are in RAM (and not in flash) in the ext-ram workaround version.

2017-09-13 10:36:56 +08:00