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mirror of https://github.com/espressif/esp-idf.git synced 2025-10-29 12:28:58 +00:00
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b65d20d37142ab49d82793da99b72e2da9ae7791
esp-idf/components/riscv/include/riscv
History
wuzhenghui 1e11f287e1 change(esp_hw_support): disable CPU wait-for-event mode on cpu start
2025-02-18 19:21:09 +08:00
..
csr_hwlp.h
fix(riscv): make HWLP feature use direct saving of lazy saving
2024-05-21 17:27:46 +08:00
csr_pie.h
feat(riscv): add support for PIE coprocessor and HWLP feature
2024-05-20 10:47:58 +08:00
csr.h
fix(cpu_region_protect): Reset PMA entries before using them
2024-09-18 10:25:18 +05:30
encoding.h
change(esp_hw_support): disable CPU wait-for-event mode on cpu start
2025-02-18 19:21:09 +08:00
instruction_decode.h
refactor(tools): Tidy up core component files copyright ignore
2024-01-22 18:07:35 +08:00
interrupt.h
fix(esp32c5): add CLIC interrupt controller support for the ESP32-C5
2024-04-16 10:38:14 +08:00
rv_utils.h
feat(riscv): added api to disable branch predictor
2024-08-14 14:34:34 +08:00
rvruntime-frames.h
feat(riscv): add support for PIE coprocessor and HWLP feature
2024-05-20 10:47:58 +08:00
semihosting.h
semihosting: version 2
2022-05-05 09:12:42 +00:00
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