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https://github.com/espressif/esp-idf.git
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cb4d90186f
Introduce a new HAL API `usb_dwc_hal_set_fifo_config()` that allows advanced users to manually configure RX, Non-Periodic TX, and Periodic TX FIFO sizes. This offers fine-grained control beyond the previous bias-based sizing approach. The HAL function no longer returns `esp_err_t`, and internal validations are enforced via `HAL_ASSERT()`. Responsibility for input validation has been moved to the HCD layer. FIFO configuration must be applied before any USB pipes are created or activated. This feature is intended for use during `usb_host_install()`. If no custom FIFO configuration is provided (i.e., all values are zero), the driver falls back to a bias-based default layout based on Kconfig settings (`CONFIG_USB_HOST_HW_BUFFER_BIAS_*`). Bias resolution is done inside `hcd_port_init()`. The `port_obj_t` structure has been extended with a `fifo_config` field, which stores the configuration to allow re-application after a USB port reset. Obsolete FIFO bias enums (`usb_hal_fifo_bias_t`, `hcd_port_fifo_bias_t`) and related APIs (`hcd_port_set_fifo_bias()`) have been removed in favor of the new structure-based mechanism. The HCD initialization and port reset flow has been updated to use the explicit FIFO configuration. USB Host maintainer documentation (`maintainers.md`) has been updated accordingly. Test cases were updated to remove the usage of removed bias API and now rely on default or custom FIFO configuration.
546 lines
25 KiB
C
546 lines
25 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h> // For memset()
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#include <stdlib.h> // For abort()
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#include "sdkconfig.h"
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#include "soc/chip_revision.h"
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#include "soc/usb_dwc_periph.h"
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#include "hal/usb_dwc_hal.h"
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#include "hal/usb_dwc_ll.h"
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#include "hal/efuse_hal.h"
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#include "hal/assert.h"
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// ------------------------------------------------ Macros and Types ---------------------------------------------------
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// ---------------------- Constants ------------------------
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#define BENDPOINTADDRESS_NUM_MSK 0x0F //Endpoint number mask of the bEndpointAddress field of an endpoint descriptor
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#define BENDPOINTADDRESS_DIR_MSK 0x80 //Endpoint direction mask of the bEndpointAddress field of an endpoint descriptor
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#define CORE_REG_GSNPSID 0x4F54400A //Release number of USB_DWC used in Espressif's SoCs
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// -------------------- Configurable -----------------------
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/**
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* The following core interrupts will be enabled (listed LSB to MSB). Some of these
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* interrupts are enabled later than others.
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* - USB_DWC_LL_INTR_CORE_PRTINT
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* - USB_DWC_LL_INTR_CORE_HCHINT
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* - USB_DWC_LL_INTR_CORE_DISCONNINT
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* The following PORT interrupts cannot be masked, listed LSB to MSB
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* - USB_DWC_LL_INTR_HPRT_PRTCONNDET
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* - USB_DWC_LL_INTR_HPRT_PRTENCHNG
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* - USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG
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*/
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#define CORE_INTRS_EN_MSK (USB_DWC_LL_INTR_CORE_DISCONNINT)
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//Interrupts that pertain to core events
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#define CORE_EVENTS_INTRS_MSK (USB_DWC_LL_INTR_CORE_DISCONNINT | \
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USB_DWC_LL_INTR_CORE_HCHINT)
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//Interrupt that pertain to host port events
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#define PORT_EVENTS_INTRS_MSK (USB_DWC_LL_INTR_HPRT_PRTCONNDET | \
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USB_DWC_LL_INTR_HPRT_PRTENCHNG | \
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USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG)
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/**
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* The following channel interrupt bits are currently checked (in order LSB to MSB)
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* - USB_DWC_LL_INTR_CHAN_XFERCOMPL
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* - USB_DWC_LL_INTR_CHAN_CHHLTD
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* - USB_DWC_LL_INTR_CHAN_STALL
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* - USB_DWC_LL_INTR_CHAN_BBLEER
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* - USB_DWC_LL_INTR_CHAN_BNAINTR
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* - USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR
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*
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* Note the following points about channel interrupts:
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* - Not all bits are unmaskable under scatter/gather
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* - Those bits proxy their interrupt through the USB_DWC_LL_INTR_CHAN_CHHLTD bit
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* - USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR is always unmasked
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* - When USB_DWC_LL_INTR_CHAN_BNAINTR occurs, USB_DWC_LL_INTR_CHAN_CHHLTD will NOT.
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* - USB_DWC_LL_INTR_CHAN_AHBERR doesn't actually ever happen on our system (i.e., ESP32-S2, ESP32-S3):
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* - If the QTD list's starting address is an invalid address (e.g., NULL), the core will attempt to fetch that
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* address for a transfer descriptor and probably gets all zeroes. It will interpret the zero as a bad QTD and
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* return a USB_DWC_LL_INTR_CHAN_BNAINTR instead.
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* - If the QTD's buffer pointer is an invalid address, the core will attempt to read/write data to/from that
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* invalid buffer address with NO INDICATION OF ERROR. The transfer will be acknowledged and treated as
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* successful. Bad buffer pointers MUST BE CHECKED FROM HIGHER LAYERS INSTEAD.
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*/
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#define CHAN_INTRS_EN_MSK (USB_DWC_LL_INTR_CHAN_XFERCOMPL | \
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USB_DWC_LL_INTR_CHAN_CHHLTD | \
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USB_DWC_LL_INTR_CHAN_BNAINTR)
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#define CHAN_INTRS_ERROR_MSK (USB_DWC_LL_INTR_CHAN_STALL | \
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USB_DWC_LL_INTR_CHAN_BBLEER | \
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USB_DWC_LL_INTR_CHAN_BNAINTR | \
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USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR)
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// -------------------------------------------------- Core (Global) ----------------------------------------------------
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static void set_defaults(usb_dwc_hal_context_t *hal)
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{
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//GAHBCFG register
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usb_dwc_ll_gahbcfg_en_dma_mode(hal->dev);
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int hbstlen = 0; //Use AHB burst SINGLE by default
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#if CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP32S2_REV_MIN_FULL < 100
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/*
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Hardware errata workaround for the ESP32-S2 ECO0 (see ESP32-S2 Errata Document section 4.0 for full details).
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ESP32-S2 ECO0 has a hardware errata where the AHB bus arbiter may generate incorrect arbitration signals leading to
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the DWC_OTG corrupting the DMA transfers of other peripherals (or vice versa) on the same bus. The peripherals that
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share the same bus with DWC_OTG include I2C and SPI (see ESP32-S2 Errata Document for more details). To workaround
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this, the DWC_OTG's AHB should use INCR mode to prevent change of arbitration during a burst operation, thus
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avoiding this errata.
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Note: Setting AHB burst to INCR increases the likeliness of DMA underruns on other peripherals sharing the same bus
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arbiter as the DWC_OTG (e.g., I2C and SPI) as change of arbitration during the burst operation is not permitted.
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Users should keep this limitation in mind when the DWC_OTG transfers large data payloads (e.g., 512 MPS transfers)
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while this workaround is enabled.
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*/
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if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
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hbstlen = 1; //Set AHB burst to INCR to workaround hardware errata
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}
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#endif //CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP32S2_REV_MIN_FULL < 100
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usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen); //Set AHB burst mode
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//GUSBCFG register
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usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev); //Disable HNP
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usb_dwc_ll_gusbcfg_dis_srp_cap(hal->dev); //Disable SRP
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// If this USB-DWC supports HS PHY, use it
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if (hal->constant_config.hsphy_type != 0) {
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usb_dwc_ll_gusbcfg_set_timeout_cal(hal->dev, 5); // 5 PHY clocks for our HS PHY
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usb_dwc_ll_gusbcfg_set_utmi_phy(hal->dev);
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}
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//Enable interruts
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usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF); //Mask all interrupts first
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usb_dwc_ll_gintmsk_en_intrs(hal->dev, CORE_INTRS_EN_MSK); //Unmask global interrupts
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usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Clear interrupts
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usb_dwc_ll_gahbcfg_en_global_intr(hal->dev); //Enable interrupt signal
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//Enable host mode
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usb_dwc_ll_gusbcfg_force_host_mode(hal->dev);
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}
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void usb_dwc_hal_init(usb_dwc_hal_context_t *hal, int port_id)
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{
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// Check if a peripheral is alive by reading the core ID registers
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HAL_ASSERT(port_id < SOC_USB_OTG_PERIPH_NUM);
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usb_dwc_dev_t *dev = USB_DWC_LL_GET_HW(port_id);
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uint32_t core_id = usb_dwc_ll_gsnpsid_get_id(dev);
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HAL_ASSERT(core_id == CORE_REG_GSNPSID);
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(void) core_id; //Suppress unused variable warning if asserts are disabled
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// Initialize HAL context
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memset(hal, 0, sizeof(usb_dwc_hal_context_t));
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hal->dev = dev;
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// Save constant configuration of this USB-DWC instance
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/*
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* EPINFO_CTL is located at the end of FIFO, its size is fixed in HW.
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* The reserved size is always the worst-case, which is device mode that requires 4 locations per EP direction (including EP0).
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* Here we just read the FIFO size from HW register, to avoid any ambivalence
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*/
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hal->constant_config.fifo_size = usb_dwc_ll_ghwcfg_get_fifo_depth(dev);
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hal->constant_config.hsphy_type = usb_dwc_ll_ghwcfg_get_hsphy_type(dev);
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hal->constant_config.chan_num_total = usb_dwc_ll_ghwcfg_get_channel_num(dev);
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set_defaults(hal);
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}
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void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal)
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{
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//Disable and clear global interrupt
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usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF); //Disable all interrupts
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usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Clear interrupts
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usb_dwc_ll_gahbcfg_dis_global_intr(hal->dev); //Disable interrupt signal
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hal->dev = NULL;
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}
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void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal)
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{
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usb_dwc_ll_grstctl_core_soft_reset(hal->dev);
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while (usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(hal->dev)) {
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; // Wait until core reset is done
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}
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while (!usb_dwc_ll_grstctl_is_ahb_idle(hal->dev)) {
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; // Wait until AHB Master bus is idle before doing any other operations
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}
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// Set the default bits in USB-DWC registers
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set_defaults(hal);
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// Clear all the flags and channels
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hal->periodic_frame_list = NULL;
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hal->flags.val = 0;
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hal->channels.num_allocated = 0;
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hal->channels.chan_pend_intrs_msk = 0;
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if (hal->channels.hdls) {
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for (int i = 0; i < hal->constant_config.chan_num_total; i++) {
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hal->channels.hdls[i] = NULL;
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}
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}
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}
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bool usb_dwc_hal_fifo_config_is_valid(const usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *config)
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{
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if (!hal || !config) {
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return false;
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}
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uint32_t used_lines = config->rx_fifo_lines + config->nptx_fifo_lines + config->ptx_fifo_lines;
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return (used_lines <= hal->constant_config.fifo_size);
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}
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void usb_dwc_hal_set_fifo_config(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *config)
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{
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// Check internal HAL state
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HAL_ASSERT(hal != NULL);
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HAL_ASSERT(hal->channels.hdls != NULL);
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// Validate provided config
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HAL_ASSERT(config != NULL);
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// Check if configuration exceeds available FIFO memory
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HAL_ASSERT(usb_dwc_hal_fifo_config_is_valid(hal, config));
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// Ensure no active channels (must only be called before USB install completes)
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for (int i = 0; i < hal->constant_config.chan_num_total; i++) {
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if (hal->channels.hdls[i] != NULL) {
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HAL_ASSERT(!hal->channels.hdls[i]->flags.active);
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}
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}
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// Program FIFO size registers
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usb_dwc_ll_grxfsiz_set_fifo_size(hal->dev, config->rx_fifo_lines);// Set RX FIFO size (GRXFSIZ)
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// Set Non-Periodic TX FIFO (GNPTXFSIZ)
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// Offset = RX FIFO lines
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usb_dwc_ll_gnptxfsiz_set_fifo_size(hal->dev, config->rx_fifo_lines, config->nptx_fifo_lines);
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// Set Periodic TX FIFO (HPTXFSIZ)
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// Offset = RX + NPTX
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usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(hal->dev,
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config->rx_fifo_lines + config->nptx_fifo_lines,
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config->ptx_fifo_lines);
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// Flush all FIFOs
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usb_dwc_ll_grstctl_flush_nptx_fifo(hal->dev);
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usb_dwc_ll_grstctl_flush_ptx_fifo(hal->dev);
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usb_dwc_ll_grstctl_flush_rx_fifo(hal->dev);
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// Save configuration to HAL context
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hal->fifo_config = *config;
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hal->flags.fifo_sizes_set = 1;
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}
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void usb_dwc_hal_get_mps_limits(usb_dwc_hal_context_t *hal, usb_hal_fifo_mps_limits_t *mps_limits)
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{
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HAL_ASSERT(hal && mps_limits);
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HAL_ASSERT(hal->flags.fifo_sizes_set);
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const usb_dwc_hal_fifo_config_t *fifo_config = &(hal->fifo_config);
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mps_limits->in_mps = (fifo_config->rx_fifo_lines - 2) * 4; // Two lines are reserved for status quadlets internally by USB_DWC
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mps_limits->non_periodic_out_mps = fifo_config->nptx_fifo_lines * 4;
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mps_limits->periodic_out_mps = fifo_config->ptx_fifo_lines * 4;
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}
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// ---------------------------------------------------- Host Port ------------------------------------------------------
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static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal)
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{
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//Disable the hprt (connection) and disconnection interrupts to prevent repeated triggerings
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usb_dwc_ll_gintmsk_dis_intrs(hal->dev, USB_DWC_LL_INTR_CORE_PRTINT | USB_DWC_LL_INTR_CORE_DISCONNINT);
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hal->flags.dbnc_lock_enabled = 1;
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}
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void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal)
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{
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// Host Configuration
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usb_dwc_ll_hcfg_en_scatt_gatt_dma(hal->dev); // Enable Scatther-Gather DMA mode
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usb_dwc_ll_hcfg_dis_perio_sched(hal->dev); // Disable Periodic Scheduler (for now)
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// Configure PHY clock: Only for USB-DWC with FSLS PHY
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if (hal->constant_config.hsphy_type == 0) {
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usb_dwc_ll_hcfg_set_fsls_phy_clock(hal->dev);
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usb_dwc_ll_hfir_set_frame_interval(hal->dev);
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}
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}
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// ----------------------------------------------------- Channel -------------------------------------------------------
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// ----------------- Channel Allocation --------------------
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bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, void *chan_ctx)
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{
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HAL_ASSERT(hal->channels.hdls);
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HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set before attempting to allocate a channel
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//Attempt to allocate channel
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if (hal->channels.num_allocated == hal->constant_config.chan_num_total) {
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return false; //Out of free channels
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}
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int chan_idx = -1;
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for (int i = 0; i < hal->constant_config.chan_num_total; i++) {
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if (hal->channels.hdls[i] == NULL) {
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hal->channels.hdls[i] = chan_obj;
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chan_idx = i;
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hal->channels.num_allocated++;
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break;
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}
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}
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HAL_ASSERT(chan_idx != -1);
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//Initialize channel object
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memset(chan_obj, 0, sizeof(usb_dwc_hal_chan_t));
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chan_obj->flags.chan_idx = chan_idx;
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chan_obj->regs = usb_dwc_ll_chan_get_regs(hal->dev, chan_idx);
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chan_obj->chan_ctx = chan_ctx;
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//Note: EP characteristics configured separately
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//Clean and unmask the channel's interrupt
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usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs); //Clear the interrupt bits for that channel
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usb_dwc_ll_haintmsk_en_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
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usb_dwc_ll_hcintmsk_set_intr_mask(chan_obj->regs, CHAN_INTRS_EN_MSK); //Unmask interrupts for this channel
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usb_dwc_ll_hctsiz_init(chan_obj->regs);
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return true;
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}
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void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj)
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{
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HAL_ASSERT(hal->channels.hdls);
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if (chan_obj->type == USB_DWC_XFER_TYPE_INTR || chan_obj->type == USB_DWC_XFER_TYPE_ISOCHRONOUS) {
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//Unschedule this channel
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for (int i = 0; i < hal->frame_list_len; i++) {
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hal->periodic_frame_list[i] &= ~(1 << chan_obj->flags.chan_idx);
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}
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}
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//Can only free a channel when in the disabled state and descriptor list released
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HAL_ASSERT(!chan_obj->flags.active);
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//Disable channel's interrupt
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usb_dwc_ll_haintmsk_dis_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
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//Deallocate channel
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hal->channels.hdls[chan_obj->flags.chan_idx] = NULL;
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hal->channels.num_allocated--;
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HAL_ASSERT(hal->channels.num_allocated >= 0);
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}
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// ---------------- Channel Configuration ------------------
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void usb_dwc_hal_chan_set_ep_char(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, usb_dwc_hal_ep_char_t *ep_char)
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{
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//Cannot change ep_char whilst channel is still active or in error
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HAL_ASSERT(!chan_obj->flags.active);
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//Set the endpoint characteristics of the pipe
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usb_dwc_ll_hcchar_init(chan_obj->regs,
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ep_char->dev_addr,
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ep_char->bEndpointAddress & BENDPOINTADDRESS_NUM_MSK,
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ep_char->mps,
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ep_char->type,
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ep_char->bEndpointAddress & BENDPOINTADDRESS_DIR_MSK,
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ep_char->ls_via_fs_hub);
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//Save channel type
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chan_obj->type = ep_char->type;
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//If this is a periodic endpoint/channel, set its schedule in the frame list
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if (ep_char->type == USB_DWC_XFER_TYPE_ISOCHRONOUS || ep_char->type == USB_DWC_XFER_TYPE_INTR) {
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unsigned int interval_frame_list = ep_char->periodic.interval;
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unsigned int offset_frame_list = ep_char->periodic.offset;
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// Periodic Frame List works with USB frames. For HS endpoints we must divide interval[microframes] by 8 to get interval[frames]
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if (ep_char->periodic.is_hs) {
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interval_frame_list /= 8;
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offset_frame_list /= 8;
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}
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// Interval in Periodic Frame List must be power of 2.
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// This is not a HW restriction. It is just a lot easier to schedule channels like this.
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if (interval_frame_list >= (int)hal->frame_list_len) { // Upper limits is Periodic Frame List length
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interval_frame_list = (int)hal->frame_list_len;
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} else if (interval_frame_list >= 32) {
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interval_frame_list = 32;
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} else if (interval_frame_list >= 16) {
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interval_frame_list = 16;
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} else if (interval_frame_list >= 8) {
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interval_frame_list = 8;
|
|
} else if (interval_frame_list >= 4) {
|
|
interval_frame_list = 4;
|
|
} else if (interval_frame_list >= 2) {
|
|
interval_frame_list = 2;
|
|
} else { // Lower limit is 1
|
|
interval_frame_list = 1;
|
|
}
|
|
// Schedule the channel in the frame list
|
|
for (int i = 0; i < hal->frame_list_len; i+= interval_frame_list) {
|
|
int index = (offset_frame_list + i) % hal->frame_list_len;
|
|
hal->periodic_frame_list[index] |= 1 << chan_obj->flags.chan_idx;
|
|
}
|
|
// For HS endpoints we must write to sched_info field of HCTSIZ register to schedule microframes
|
|
// For FS endpoints sched_info is always 0xFF
|
|
// LS endpoints do not support periodic transfers
|
|
unsigned int tokens_per_frame = 0;
|
|
if (ep_char->periodic.is_hs) {
|
|
if (ep_char->periodic.interval >= 8) {
|
|
tokens_per_frame = 1; // 1 token every 8 microframes
|
|
} else if (ep_char->periodic.interval >= 4) {
|
|
tokens_per_frame = 2; // 1 token every 4 microframes
|
|
} else if (ep_char->periodic.interval >= 2) {
|
|
tokens_per_frame = 4; // 1 token every 2 microframes
|
|
} else {
|
|
tokens_per_frame = 8; // 1 token every microframe
|
|
}
|
|
} else {
|
|
tokens_per_frame = 8;
|
|
}
|
|
usb_dwc_ll_hctsiz_set_sched_info(chan_obj->regs, tokens_per_frame, ep_char->periodic.offset);
|
|
}
|
|
}
|
|
|
|
// ------------------- Channel Control ---------------------
|
|
|
|
void usb_dwc_hal_chan_activate(usb_dwc_hal_chan_t *chan_obj, void *xfer_desc_list, int desc_list_len, int start_idx)
|
|
{
|
|
// Cannot activate a channel that has already been enabled or is pending error handling
|
|
HAL_ASSERT(!chan_obj->flags.active);
|
|
// Make sure that PING is not enabled from previous transaction
|
|
usb_dwc_ll_hctsiz_set_dopng(chan_obj->regs, false);
|
|
// Set start address of the QTD list and starting QTD index
|
|
usb_dwc_ll_hcdma_set_qtd_list_addr(chan_obj->regs, xfer_desc_list, start_idx);
|
|
usb_dwc_ll_hctsiz_set_qtd_list_len(chan_obj->regs, desc_list_len);
|
|
usb_dwc_ll_hcchar_enable_chan(chan_obj->regs); // Start the channel
|
|
chan_obj->flags.active = 1;
|
|
}
|
|
|
|
bool usb_dwc_hal_chan_request_halt(usb_dwc_hal_chan_t *chan_obj)
|
|
{
|
|
if (chan_obj->flags.active) {
|
|
/*
|
|
Request a halt so long as the channel's active flag is set.
|
|
- If the underlying hardware channel is already halted but the channel is pending interrupt handling,
|
|
disabling the channel will have no effect (i.e., no channel interrupt is generated).
|
|
- If the underlying channel is currently active, disabling the channel will trigger a channel interrupt.
|
|
|
|
Regardless, setting the "halt_requested" should cause "usb_dwc_hal_chan_decode_intr()" to report the
|
|
USB_DWC_HAL_CHAN_EVENT_HALT_REQ event when channel interrupt is handled (pending or triggered).
|
|
*/
|
|
usb_dwc_ll_hcchar_disable_chan(chan_obj->regs);
|
|
chan_obj->flags.halt_requested = 1;
|
|
return false;
|
|
} else {
|
|
//Channel was never active to begin with, simply return true
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// ------------------------------------------------- Event Handling ----------------------------------------------------
|
|
|
|
usb_dwc_hal_port_event_t usb_dwc_hal_decode_intr(usb_dwc_hal_context_t *hal)
|
|
{
|
|
uint32_t intrs_core = usb_dwc_ll_gintsts_read_and_clear_intrs(hal->dev); //Read and clear core interrupts
|
|
uint32_t intrs_port = 0;
|
|
if (intrs_core & USB_DWC_LL_INTR_CORE_PRTINT) {
|
|
//There are host port interrupts. Read and clear those as well.
|
|
intrs_port = usb_dwc_ll_hprt_intr_read_and_clear(hal->dev);
|
|
}
|
|
//Note: Do not change order of checks. Regressing events (e.g. enable -> disabled, connected -> connected)
|
|
//always take precedence. ENABLED < DISABLED < CONN < DISCONN < OVRCUR
|
|
usb_dwc_hal_port_event_t event = USB_DWC_HAL_PORT_EVENT_NONE;
|
|
|
|
//Check if this is a core or port event
|
|
if ((intrs_core & CORE_EVENTS_INTRS_MSK) || (intrs_port & PORT_EVENTS_INTRS_MSK)) {
|
|
//Do not change the order of the following checks. Some events/interrupts take precedence over others
|
|
if (intrs_core & USB_DWC_LL_INTR_CORE_DISCONNINT) {
|
|
event = USB_DWC_HAL_PORT_EVENT_DISCONN;
|
|
debounce_lock_enable(hal);
|
|
//Mask the port connection and disconnection interrupts to prevent repeated triggering
|
|
} else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG) {
|
|
//Check if this is an overcurrent or an overcurrent cleared
|
|
if (usb_dwc_ll_hprt_get_port_overcur(hal->dev)) {
|
|
event = USB_DWC_HAL_PORT_EVENT_OVRCUR;
|
|
} else {
|
|
event = USB_DWC_HAL_PORT_EVENT_OVRCUR_CLR;
|
|
}
|
|
} else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTENCHNG) {
|
|
if (usb_dwc_ll_hprt_get_port_en(hal->dev)) { //Host port was enabled
|
|
event = USB_DWC_HAL_PORT_EVENT_ENABLED;
|
|
} else { //Host port has been disabled
|
|
event = USB_DWC_HAL_PORT_EVENT_DISABLED;
|
|
}
|
|
} else if (intrs_port & USB_DWC_LL_INTR_HPRT_PRTCONNDET && !hal->flags.dbnc_lock_enabled) {
|
|
event = USB_DWC_HAL_PORT_EVENT_CONN;
|
|
debounce_lock_enable(hal);
|
|
}
|
|
}
|
|
//Port events always take precedence over channel events
|
|
if (event == USB_DWC_HAL_PORT_EVENT_NONE && (intrs_core & USB_DWC_LL_INTR_CORE_HCHINT)) {
|
|
//One or more channels have pending interrupts. Store the mask of those channels
|
|
hal->channels.chan_pend_intrs_msk = usb_dwc_ll_haint_get_chan_intrs(hal->dev);
|
|
event = USB_DWC_HAL_PORT_EVENT_CHAN;
|
|
}
|
|
|
|
return event;
|
|
}
|
|
|
|
usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal)
|
|
{
|
|
HAL_ASSERT(hal->channels.hdls);
|
|
int chan_num = __builtin_ffs(hal->channels.chan_pend_intrs_msk);
|
|
if (chan_num) {
|
|
hal->channels.chan_pend_intrs_msk &= ~(1 << (chan_num - 1)); //Clear the pending bit for that channel
|
|
return hal->channels.hdls[chan_num - 1];
|
|
} else {
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
usb_dwc_hal_chan_event_t usb_dwc_hal_chan_decode_intr(usb_dwc_hal_chan_t *chan_obj)
|
|
{
|
|
uint32_t chan_intrs = usb_dwc_ll_hcint_read_and_clear_intrs(chan_obj->regs);
|
|
usb_dwc_hal_chan_event_t chan_event;
|
|
//Note: We don't assert on (chan_obj->flags.active) here as it could have been already cleared by usb_dwc_hal_chan_request_halt()
|
|
|
|
/*
|
|
Note: Do not change order of checks as some events take precedence over others.
|
|
Errors > Channel Halt Request > Transfer completed
|
|
*/
|
|
if (chan_intrs & CHAN_INTRS_ERROR_MSK) { //Note: Errors are uncommon, so we check against the entire interrupt mask to reduce frequency of entering this call path
|
|
HAL_ASSERT(chan_intrs & USB_DWC_LL_INTR_CHAN_CHHLTD); //An error should have halted the channel
|
|
//Store the error in hal context
|
|
usb_dwc_hal_chan_error_t error;
|
|
if (chan_intrs & USB_DWC_LL_INTR_CHAN_STALL) {
|
|
error = USB_DWC_HAL_CHAN_ERROR_STALL;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_BBLEER) {
|
|
error = USB_DWC_HAL_CHAN_ERROR_PKT_BBL;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_BNAINTR) {
|
|
error = USB_DWC_HAL_CHAN_ERROR_BNA;
|
|
} else { //USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR
|
|
error = USB_DWC_HAL_CHAN_ERROR_XCS_XACT;
|
|
}
|
|
//Update flags
|
|
chan_obj->error = error;
|
|
chan_obj->flags.active = 0;
|
|
//Save the error to be handled later
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_ERROR;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_CHHLTD) {
|
|
if (chan_obj->flags.halt_requested) {
|
|
chan_obj->flags.halt_requested = 0;
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_HALT_REQ;
|
|
} else {
|
|
//Must have been halted due to QTD HOC
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_CPLT;
|
|
}
|
|
chan_obj->flags.active = 0;
|
|
} else if (chan_intrs & USB_DWC_LL_INTR_CHAN_XFERCOMPL) {
|
|
/*
|
|
A transfer complete interrupt WITHOUT the channel halting only occurs when receiving a short interrupt IN packet
|
|
and the underlying QTD does not have the HOC bit set. This signifies the last packet of the Interrupt transfer
|
|
as all interrupt packets must MPS sized except the last.
|
|
*/
|
|
//The channel isn't halted yet, so we need to halt it manually to stop the execution of the next QTD/packet
|
|
usb_dwc_ll_hcchar_disable_chan(chan_obj->regs);
|
|
/*
|
|
After setting the halt bit, this will generate another channel halted interrupt. We treat this interrupt as
|
|
a NONE event, then cycle back with the channel halted interrupt to handle the CPLT event.
|
|
*/
|
|
chan_event = USB_DWC_HAL_CHAN_EVENT_NONE;
|
|
} else {
|
|
abort();
|
|
}
|
|
return chan_event;
|
|
}
|