Marius Vikhammer fcafa0de5d test(ulp): added larger delay in ULP FSM I_WR_REG instruction test ...

Test is flakey, could possibly be due to the ULP occasionally needing
a bit more time to start up.

2025-11-17 16:23:41 +08:00

..

lp_core

Merge branch 'bugfix/lp_core_array_bounds_p4_v5.4' into 'release/v5.4'

2025-09-01 10:52:46 +08:00

ulp_fsm

test(ulp): added larger delay in ULP FSM I_WR_REG instruction test

2025-11-17 16:23:41 +08:00

ulp_riscv

feat(ulp-riscv): Added unit test for RTC I2C

2024-02-21 11:46:19 +01:00

.build-test-rules.yml

feat(system): support choosing xtal as rtc-fast clock src on P4 and C5

2024-09-19 17:30:44 +08:00