mirror of
https://github.com/espressif/esp-idf.git
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323 lines
15 KiB
C
323 lines
15 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The long term plan is to have a single soc_caps.h for each peripheral.
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// During the refactoring and multichip support development process, we
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// seperate these information into periph_caps.h for each peripheral and
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// include them here.
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/*
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* These defines are parsed and imported as kconfig variables via the script
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* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
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*
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* If this file is changed the script will automatically run the script
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* and generate the kconfig variables as part of the pre-commit hooks.
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*
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* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c3/include/soc/'`
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*
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* For more information see `tools/gen_soc_caps_kconfig/README.md`
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*
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*/
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#pragma once
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_ADC_SUPPORTED 1
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#define SOC_DEDICATED_GPIO_SUPPORTED 1
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#define SOC_UART_SUPPORTED 1
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#define SOC_GDMA_SUPPORTED 1
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#define SOC_GPTIMER_SUPPORTED 1
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#define SOC_BT_SUPPORTED 1
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#define SOC_WIFI_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_KEY_PURPOSE_FIELD 0
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#define SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK 1
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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#define SOC_LEDC_SUPPORTED 1
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#define SOC_I2C_SUPPORTED 1
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#define SOC_GPSPI_SUPPORTED 1
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#define SOC_SHA_SUPPORTED 1
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#define SOC_ECC_SUPPORTED 1
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#define SOC_FLASH_ENC_SUPPORTED 1
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#define SOC_SECURE_BOOT_SUPPORTED 1
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#define SOC_SYSTIMER_SUPPORTED 1
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#define SOC_BOD_SUPPORTED 1
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_26M 1
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#define SOC_XTAL_SUPPORT_40M 1
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_DIG_CTRL_SUPPORTED 1
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#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
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#define SOC_ADC_MONITOR_SUPPORTED 1
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#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
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#define SOC_ADC_PERIPH_NUM (1U)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
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#define SOC_ADC_MAX_CHANNEL_NUM (5)
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#define SOC_ADC_ATTEN_NUM (4)
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/*!< Digital */
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#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
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#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
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#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
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#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
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#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
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#define SOC_ADC_DIGI_MONITOR_NUM (2)
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/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
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/*!< RTC */
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#define SOC_ADC_RTC_MIN_BITWIDTH (12)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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/*!< Calibration */
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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/*-------------------------- CACHE CAPS --------------------------------------*/
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#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
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/*-------------------------- CPU CAPS ----------------------------------------*/
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#define SOC_CPU_CORES_NUM (1U)
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#define SOC_CPU_INTR_NUM 32
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#define SOC_CPU_HAS_FLEXIBLE_INTC 1
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#define SOC_CPU_BREAKPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINTS_NUM 2
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#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
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#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
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/*-------------------------- GDMA CAPS -------------------------------------*/
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#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
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#define SOC_GDMA_PAIRS_PER_GROUP (1U) // Number of GDMA pairs in each group
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#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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// ESP32-C2 has 1 GPIO peripheral
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#define SOC_GPIO_PORT 1U
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#define SOC_GPIO_PIN_COUNT 21
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#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
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#define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
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// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins)
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// Force hold is a new function of ESP32-C2
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// GPIO0~5 on ESP32-C2 can support chip deep sleep wakeup
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#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
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#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
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#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
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// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
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#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL
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/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
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#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
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#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
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#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32-C2 has 1 I2C
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#define SOC_I2C_NUM (1U)
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#define SOC_I2C_FIFO_LEN (16) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
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// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_RTC (1)
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/*-------------------------- LEDC CAPS ---------------------------------------*/
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#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
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#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
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#define SOC_LEDC_CHANNEL_NUM (6)
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#define SOC_LEDC_TIMER_BIT_WIDTH (14)
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#define SOC_LEDC_SUPPORT_FADE_STOP (1)
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/*-------------------------- MMU CAPS ----------------------------------------*/
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#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
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#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U)
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#define SOC_MMU_PERIPH_NUM (1U)
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/*-------------------------- MPU CAPS ----------------------------------------*/
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#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
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#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
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#define SOC_MPU_REGIONS_MAX_NUM 8
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#define SOC_MPU_REGION_RO_SUPPORTED 0
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#define SOC_MPU_REGION_WO_SUPPORTED 0
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/*-------------------------- RTC CAPS --------------------------------------*/
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#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
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#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
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#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
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#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
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#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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/* No dedicated RTCIO subsystem on ESP32-C2. RTC functions are still supported
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* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
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#define SOC_RTCIO_PIN_COUNT (0U)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Due to very limited availability of the DMA channels, DMA support for the SHA peripheral is disabled */
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// #define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 2
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#define SOC_SPI_PERIPH_CS_NUM(i) 6
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#define SOC_SPI_MAX_CS_NUM 6
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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#define SOC_SPI_SUPPORT_DDRCLK 1
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#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
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#define SOC_SPI_SUPPORT_CD_SIG 1
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#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
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#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
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#define SOC_SPI_SUPPORT_CLK_XTAL 1
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#define SOC_SPI_SUPPORT_CLK_PLL_F40M 1
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// Peripheral supports DIO, DOUT, QIO, or QOUT
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// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
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#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
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// Peripheral supports output given level during its "dummy phase"
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#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
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#define SOC_MEMSPI_IS_INDEPENDENT 1
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#define SOC_SPI_MAX_PRE_DIVIDER 16
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/*-------------------------- SPI MEM CAPS ---------------------------------------*/
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#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
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#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
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#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
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#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
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#define SOC_SPI_MEM_SUPPORT_WRAP (1)
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#define SOC_MEMSPI_SRC_FREQ_60M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_30M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
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#define SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED 1
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/*-------------------------- SYSTIMER CAPS ----------------------------------*/
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#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
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#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
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#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
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#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
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#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5
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#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
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#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
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/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
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#define SOC_TIMER_GROUPS (1U)
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#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
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#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
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#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
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#define SOC_TIMER_GROUP_TOTAL_TIMERS (1U)
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/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
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#define SOC_MWDT_SUPPORT_XTAL (1)
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/*-------------------------- eFuse CAPS----------------------------*/
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#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
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#define SOC_EFUSE_DIS_PAD_JTAG 1
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#define SOC_EFUSE_DIS_DIRECT_BOOT 1
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/*-------------------------- Secure Boot CAPS----------------------------*/
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#define SOC_SECURE_BOOT_V2_ECC 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS (1U)
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/*-------------------------- Flash Encryption CAPS----------------------------*/
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#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32)
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED 1
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/*-------------------------- UART CAPS ---------------------------------------*/
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// ESP32-C2 has 2 UARTs
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#define SOC_UART_NUM (2)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_SUPPORT_PLL_F40M_CLK (1) /*!< Support APB as the clock source */
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#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
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#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
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/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
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#define SOC_COEX_HW_PTI (1)
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/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
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#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
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#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
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/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
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#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
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/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
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#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
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/*-------------------------- Power Management CAPS ----------------------------*/
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#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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/*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */
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#define SOC_CLK_RC_FAST_D256_SUPPORTED (1)
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#define SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 (1)
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< ESP32C2 only supports to connect an external oscillator, not a crystal */
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/*------------------------------------ WI-FI CAPS ------------------------------------*/
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#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
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#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */
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#define SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW (1) /*!< Support delta early time for rf phy on/off */
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/*---------------------------------- Bluetooth CAPS ----------------------------------*/
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#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
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#define SOC_BLE_MESH_SUPPORTED (0) /*!< Support BLE MESH */
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#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
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#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
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#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
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#define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
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/*------------------------------------- PHY CAPS -------------------------------------*/
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#define SOC_PHY_IMPROVE_RX_11B (1)
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#define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi and BLE*/
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