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fix(examples): Fix IPC ISR RISC-V test for ESP32-P4 rev3

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Remove checks for MSTATUS and MCAUSE values that
may vary in different chip revisions.
This commit is contained in:
Konstantin Kondrashov
2025-11-20 12:38:30 +02:00
committed by Sudeep Mohanty
parent 6534932340
commit ec85de2bec
1 changed files with 0 additions and 4 deletions
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4
examples/system/ipc/ipc_isr/riscv/pytest_ipc_isr_riscv.py
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@@ -7,15 +7,11 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize('target', ['esp32p4'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14423')
def test_ipc_isr_riscv(dut: Dut) -> None:
dut.expect_exact('example: Start')
dut.expect_exact('example: MSTATUS = 0x11880')
dut.expect_exact('example: in[0] = 0x1')
dut.expect_exact('example: in[1] = 0x2')
dut.expect_exact('example: in[2] = 0x3')
dut.expect_exact('example: out[0] = (in[0] | in[1] | in[2]) = 0x3')
dut.expect_exact('example: out[1] = (in[0] + in[1] + in[2]) = 0x6')
dut.expect_exact('example: out[2] = MCAUSE of other cpu = 0xb800002c')
dut.expect_exact('example: out[3] = MSTATUS of other cpu = 0x11880')
dut.expect_exact('example: End')