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feat(2ddma): ESP32P4 ECO5 2DDMA related updates

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Added one more pair of 2DDMA channels
Priority bit width increased corespondingly
Added three new CSC modes for RX channel 0
This commit is contained in:
Song Ruo Jing
2025-09-12 16:45:58 +08:00
parent a9b2bd1b72
commit e69eeb7355
14 changed files with 2227 additions and 10000 deletions
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23
components/esp_hw_support/dma/dma2d.c
View File

@@ -23,7 +23,6 @@
#include "hal/dma2d_ll.h"
#include "soc/dma2d_channel.h"
#include "soc/dma2d_periph.h"
#include "soc/soc_caps.h"
#include "esp_bit_defs.h"
/**
@@ -365,20 +364,20 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
_lock_acquire(&s_platform.mutex);
if (!s_platform.groups[group_id]) {
dma2d_group_t *pre_alloc_group = heap_caps_calloc(1, sizeof(dma2d_group_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(SOC_DMA2D_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(SOC_DMA2D_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS);
if (pre_alloc_group && pre_alloc_tx_channels && pre_alloc_rx_channels) {
pre_alloc_group->group_id = group_id;
pre_alloc_group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
TAILQ_INIT(&pre_alloc_group->pending_trans_tailq);
pre_alloc_group->tx_channel_free_mask = (1 << SOC_DMA2D_TX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->rx_channel_free_mask = (1 << SOC_DMA2D_RX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_TX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_RX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->tx_channel_reserved_mask = dma2d_tx_channel_reserved_mask[group_id];
pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id];
pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
pre_alloc_group->intr_priority = -1;
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i];
dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i];
tx_chan->base.group = pre_alloc_group;
@@ -386,7 +385,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
tx_chan->base.direction = DMA2D_CHANNEL_DIRECTION_TX;
tx_chan->base.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
}
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
pre_alloc_group->rx_chans[i] = &pre_alloc_rx_channels[i];
dma2d_rx_channel_t *rx_chan = pre_alloc_group->rx_chans[i];
rx_chan->base.group = pre_alloc_group;
@@ -435,7 +434,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
// Allocate TX and RX interrupts
if (s_platform.groups[group_id]) {
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i];
if (rx_chan->base.intr == NULL) {
ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i],
@@ -450,7 +449,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
}
}
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i];
if (tx_chan->base.intr == NULL) {
ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i],
@@ -510,12 +509,12 @@ esp_err_t dma2d_release_pool(dma2d_pool_handle_t dma2d_pool)
}
if (do_deinitialize) {
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
if (dma2d_group->rx_chans[i]->base.intr) {
esp_intr_free(dma2d_group->rx_chans[i]->base.intr);
}
}
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
if (dma2d_group->tx_chans[i]->base.intr) {
esp_intr_free(dma2d_group->tx_chans[i]->base.intr);
}
@@ -983,7 +982,7 @@ esp_err_t dma2d_force_end(dma2d_trans_t *trans, bool *need_yield)
// Stop the RX channel and its bundled TX channels first
dma2d_stop(&rx_chan->base);
uint32_t tx_chans = rx_chan->bundled_tx_channel_mask;
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
if (tx_chans & (1 << i)) {
dma2d_stop(&group->tx_chans[i]->base);
}

4
components/esp_hw_support/dma/dma2d_priv.h
View File

@@ -57,8 +57,8 @@ struct dma2d_group_t {
uint8_t rx_channel_reserved_mask; // Bit mask indicating the being reserved RX channels
uint32_t tx_periph_m2m_free_id_mask; // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment
uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment
dma2d_tx_channel_t *tx_chans[SOC_DMA2D_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels
dma2d_rx_channel_t *rx_chans[SOC_DMA2D_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels
dma2d_tx_channel_t *tx_chans[DMA2D_LL_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels
dma2d_rx_channel_t *rx_chans[DMA2D_LL_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels
int intr_priority; // All channels in the same group should share the same interrupt priority
};

2
components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c
View File

@@ -22,7 +22,7 @@
// This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of
// transactions being send to a queue, and waiting for free channels becoming available, and being picked to start the
// real hardware operation.
#define M2M_TRANS_TIMES (8)
#define M2M_TRANS_TIMES (12)
// Descriptor and buffer address and size should aligned to 64 bytes (the cacheline size alignment restriction) to be used by CPU

4
components/esp_system/port/soc/esp32p4/system_internal.c
View File

@@ -53,11 +53,11 @@ void esp_system_reset_modules_on_exit(void)
}
}
if (dma2d_ll_is_bus_clock_enabled(0)) {
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
dma2d_ll_rx_abort(DMA2D_LL_GET_HW(0), i, true);
while (!dma2d_ll_rx_is_reset_avail(DMA2D_LL_GET_HW(0), i));
}
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
dma2d_ll_tx_abort(DMA2D_LL_GET_HW(0), i, true);
while (!dma2d_ll_tx_is_reset_avail(DMA2D_LL_GET_HW(0), i));
}

184
components/hal/esp32p4/include/hal/dma2d_ll.h
View File

@@ -11,8 +11,10 @@
#include "hal/dma2d_types.h"
#include "soc/dma2d_channel.h"
#include "soc/dma2d_struct.h"
#include "soc/soc_caps.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/config.h"
#include "soc/soc.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -22,6 +24,14 @@ extern "C" {
#define DMA2D_LL_GET_HW(id) (((id) == 0) ? (&DMA2D) : NULL)
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define DMA2D_LL_TX_CHANNELS_PER_GROUP SOC_DMA2D_TX_CHANNELS_PER_GROUP // Number of 2D-DMA TX (OUT) channels in each group
#define DMA2D_LL_RX_CHANNELS_PER_GROUP SOC_DMA2D_RX_CHANNELS_PER_GROUP // Number of 2D-DMA RX (IN) channels in each group
#else
#define DMA2D_LL_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group
#define DMA2D_LL_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group
#endif
// 2D-DMA interrupts
#define DMA2D_LL_RX_EVENT_MASK (0x3FFF)
#define DMA2D_LL_TX_EVENT_MASK (0x1FFF)
@@ -57,8 +67,11 @@ extern "C" {
// Bit masks that are used to indicate availability of some sub-features in the channels
#define DMA2D_LL_TX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // TX channels that support reorder feature
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2 | BIT3) // TX channels that support color space conversion feature
#else
#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2) // TX channels that support color space conversion feature
#endif
#define DMA2D_LL_RX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // RX channels that support reorder feature
#define DMA2D_LL_RX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0) // RX channels that support color space conversion feature
@@ -158,16 +171,13 @@ static inline uint32_t dma2d_ll_get_scramble_order_sel(dma2d_scramble_order_t or
}
/////////////////////////////////////// RX ///////////////////////////////////////////
#define DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, ch, reg) ((volatile void*[]){&dev->in_channel0.reg, &dev->in_channel1.reg}[(ch)])
/**
* @brief Get 2D-DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_int_st_chn_reg_t *reg = (volatile dma2d_in_int_st_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st);
return reg->val;
return dev->in_channel[channel].in_int_st.val & DMA2D_LL_RX_EVENT_MASK;
}
/**
@@ -176,11 +186,10 @@ static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
volatile dma2d_in_int_ena_chn_reg_t *reg = (volatile dma2d_in_int_ena_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_ena);
if (enable) {
reg->val = reg->val | (mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val | (mask & DMA2D_LL_RX_EVENT_MASK);
} else {
reg->val = reg->val & ~(mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val & ~(mask & DMA2D_LL_RX_EVENT_MASK);
}
}
@@ -190,8 +199,7 @@ static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t chann
__attribute__((always_inline))
static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t channel, uint32_t mask)
{
volatile dma2d_in_int_clr_chn_reg_t *reg = (volatile dma2d_in_int_clr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_clr);
reg->val = (mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_clr.val = (mask & DMA2D_LL_RX_EVENT_MASK);
}
/**
@@ -199,7 +207,7 @@ static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t
*/
static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *dev, uint32_t channel)
{
return (volatile void *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st);
return (volatile void *)(&dev->in_channel[channel].in_int_st);
}
/**
@@ -208,8 +216,7 @@ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *d
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_check_owner_chn = enable;
dev->in_channel[channel].in_conf0.in_check_owner_chn = enable;
}
/**
@@ -218,8 +225,7 @@ static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t cha
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_page_bound_en_chn = enable;
dev->in_channel[channel].in_conf0.in_page_bound_en_chn = enable;
}
/**
@@ -249,8 +255,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t
// Unsupported data burst length
abort();
}
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_mem_burst_length_chn = sel;
dev->in_channel[channel].in_conf0.in_mem_burst_length_chn = sel;
}
/**
@@ -259,8 +264,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->indscr_burst_en_chn = enable;
dev->in_channel[channel].in_conf0.indscr_burst_en_chn = enable;
}
/**
@@ -269,9 +273,8 @@ static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_
__attribute__((always_inline))
static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_rst_chn = 1;
reg->in_rst_chn = 0;
dev->in_channel[channel].in_conf0.in_rst_chn = 1;
dev->in_channel[channel].in_conf0.in_rst_chn = 0;
}
/**
@@ -280,8 +283,7 @@ static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state);
return reg->in_reset_avail_chn;
return dev->in_channel[channel].in_state.in_reset_avail_chn;
}
/**
@@ -290,8 +292,7 @@ static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel
__attribute__((always_inline))
static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool disable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_cmd_disable_chn = disable;
dev->in_channel[channel].in_conf0.in_cmd_disable_chn = disable;
}
/**
@@ -300,8 +301,7 @@ static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool di
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_dscr_port(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_dscr_port_en_chn = enable;
dev->in_channel[channel].in_conf0.in_dscr_port_en_chn = enable;
}
/**
@@ -328,8 +328,7 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c
// Unsupported macro block size
abort();
}
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_macro_block_size_chn = sel;
dev->in_channel[channel].in_conf0.in_macro_block_size_chn = sel;
}
/**
@@ -338,9 +337,8 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_pop_chn_reg_t *reg = (volatile dma2d_in_pop_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_pop);
reg->infifo_pop_chn = 1;
return reg->infifo_rdata_chn;
dev->in_channel[channel].in_pop.infifo_pop_chn = 1;
return dev->in_channel[channel].in_pop.infifo_rdata_chn;
}
/**
@@ -349,8 +347,7 @@ static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile dma2d_in_link_addr_chn_reg_t *reg = (volatile dma2d_in_link_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_addr);
reg->inlink_addr_chn = addr;
dev->in_channel[channel].in_link_addr.inlink_addr_chn = addr;
}
/**
@@ -359,8 +356,7 @@ static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel,
__attribute__((always_inline))
static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_start_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_start_chn = 1;
}
/**
@@ -369,8 +365,7 @@ static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_stop_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_stop_chn = 1;
}
/**
@@ -379,8 +374,7 @@ static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_restart_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_restart_chn = 1;
}
/**
@@ -389,8 +383,7 @@ static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t channel, int owner)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_auto_ret_chn = owner;
dev->in_channel[channel].in_link_conf.inlink_auto_ret_chn = owner;
}
/**
@@ -399,8 +392,7 @@ static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
return reg->inlink_park_chn;
return dev->in_channel[channel].in_link_conf.inlink_park_chn;
}
/**
@@ -409,8 +401,7 @@ static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t chann
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state);
return (reg->in_state_chn == 0);
return (dev->in_channel[channel].in_state.in_state_chn == 0);
}
/**
@@ -419,8 +410,7 @@ static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_suc_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_suc_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_suc_eof_des_addr);
return reg->val;
return dev->in_channel[channel].in_suc_eof_des_addr.val;
}
/**
@@ -429,8 +419,7 @@ static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, u
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_err_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_err_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_err_eof_des_addr);
return reg->val;
return dev->in_channel[channel].in_err_eof_des_addr.val;
}
/**
@@ -439,18 +428,7 @@ static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uin
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_prefetched_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_dscr_chn_reg_t *reg = (volatile dma2d_in_dscr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_dscr);
return reg->val;
}
/**
* @brief Set priority for 2D-DMA RX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_priority_chn = prio;
return dev->in_channel[channel].in_dscr.val;
}
/**
@@ -459,10 +437,8 @@ static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel,
__attribute__((always_inline))
static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t channel, dma2d_trigger_peripheral_t periph, int periph_id)
{
volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel);
peri_sel_reg->in_peri_sel_chn = periph_id;
volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
conf0_reg->in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M);
dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = periph_id;
dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M);
}
/**
@@ -471,10 +447,8 @@ static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t chan
__attribute__((always_inline))
static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel);
peri_sel_reg->in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE;
volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
conf0_reg->in_mem_trans_en_chn = false;
dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE;
dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = false;
}
// REORDER FUNCTION (Only CH0 supports this feature)
@@ -485,8 +459,7 @@ static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_reorder(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_reorder_en_chn = enable;
dev->in_channel[channel].in_conf0.in_reorder_en_chn = enable;
}
// COLOR SPACE CONVERSION FUNCTION
@@ -524,6 +497,17 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
proc_en = false;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV444_TO_YUV422:
input_sel = 0;
proc_en = false;
output_sel = 2;
break;
case DMA2D_CSC_RX_YUV444_TO_YUV420:
case DMA2D_CSC_RX_YUV422_TO_YUV420:
input_sel = 0;
proc_en = false;
output_sel = 3;
break;
case DMA2D_CSC_RX_YUV420_TO_RGB888_601:
case DMA2D_CSC_RX_YUV422_TO_RGB888_601:
input_sel = 0;
@@ -581,13 +565,13 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
abort();
}
dev->in_channel0.in_color_convert.in_color_input_sel_chn = input_sel;
dev->in_channel0.in_color_convert.in_color_3b_proc_en_chn = proc_en;
dev->in_channel0.in_color_convert.in_color_output_sel_chn = output_sel;
dev->in_channel[channel].in_color_convert.in_color_input_sel_chn = input_sel;
dev->in_channel[channel].in_color_convert.in_color_3b_proc_en_chn = proc_en;
dev->in_channel[channel].in_color_convert.in_color_output_sel_chn = output_sel;
if (proc_en) {
HAL_ASSERT(table);
typeof(dev->in_channel0.in_color_param_group) color_param_group;
typeof(dev->in_channel[channel].in_color_param_group) color_param_group;
color_param_group.param_h.a = table[0][0];
color_param_group.param_h.b = table[0][1];
@@ -604,12 +588,12 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
color_param_group.param_l.c = table[2][2];
color_param_group.param_l.d = table[2][3];
dev->in_channel0.in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0];
dev->in_channel0.in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1];
dev->in_channel0.in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0];
dev->in_channel0.in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1];
dev->in_channel0.in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0];
dev->in_channel0.in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1];
dev->in_channel[channel].in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0];
dev->in_channel[channel].in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1];
dev->in_channel[channel].in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0];
dev->in_channel[channel].in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1];
dev->in_channel[channel].in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0];
dev->in_channel[channel].in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1];
}
}
@@ -620,7 +604,7 @@ __attribute__((always_inline))
static inline void dma2d_ll_rx_set_csc_pre_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order)
{
HAL_ASSERT(channel == 0); // Only channel 0 supports scramble
dev->in_channel0.in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order);
dev->in_channel[channel].in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order);
}
/**
@@ -630,7 +614,7 @@ __attribute__((always_inline))
static inline void dma2d_ll_rx_set_csc_post_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order)
{
HAL_ASSERT(channel == 0); // Only channel 0 supports scramble
dev->in_channel0.in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order);
dev->in_channel[channel].in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order);
}
// Arbiter
@@ -659,8 +643,7 @@ static inline void dma2d_ll_rx_set_arb_timeout(dma2d_dev_t *dev, uint32_t timeou
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t channel, uint32_t token_num)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_token_num_chn = token_num;
dev->in_channel[channel].in_arb.in_arb_token_num_chn = token_num;
}
/**
@@ -669,20 +652,22 @@ static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t chan
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_arb_token_num(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
return reg->in_arb_token_num_chn;
return dev->in_channel[channel].in_arb.in_arb_token_num_chn;
}
/**
* @brief Set 2D-DMA RX channel arbiter priority
* @brief Set priority for 2D-DMA RX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_priority_chn = priority;
dev->in_channel[channel].in_arb.in_arb_priority_chn = priority;
}
// ETM
// note that in_ch1 in_etm_conf register addr is different before and after rev3 chip!
/////////////////////////////////////// TX ///////////////////////////////////////////
/**
* @brief Get 2D-DMA TX channel interrupt status word
@@ -954,15 +939,6 @@ static inline uint32_t dma2d_ll_tx_get_prefetched_desc_addr(dma2d_dev_t *dev, ui
return dev->out_channel[channel].out_dscr.val;
}
/**
* @brief Set priority for 2D-DMA TX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->out_channel[channel].out_arb.out_arb_priority_chn = prio;
}
/**
* @brief Connect 2D-DMA TX channel to a given peripheral
*/
@@ -1165,10 +1141,10 @@ static inline uint32_t dma2d_ll_tx_get_arb_token_num(dma2d_dev_t *dev, uint32_t
}
/**
* @brief Set 2D-DMA TX channel arbiter priority
* @brief Set priority for 2D-DMA TX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
{
dev->out_channel[channel].out_arb.out_arb_priority_chn = priority;
}

9
components/hal/include/hal/dma2d_types.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -236,8 +236,9 @@ typedef enum {
typedef enum {
DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */
DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */
DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444 conversion */
DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444 conversion */
DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444-MIPI conversion */
DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422 to YUV420-MIPI conversion */
DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444-MIPI conversion */
DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */
@@ -246,6 +247,8 @@ typedef enum {
DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444 to YUV422-MIPI conversion */
DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444 to YUV420-MIPI conversion */
DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */

2
components/soc/esp32p4/dma2d_periph.c
View File

@@ -14,10 +14,12 @@ const dma2d_signal_conn_t dma2d_periph_signals = {
[0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
[2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE,
[3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0
},
.rx_irq_id = {
[0] = ETS_DMA2D_IN_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_IN_CH1_INTR_SOURCE,
[2] = ETS_DMA2D_IN_CH2_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0
}
}
}

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -629,11 +629,11 @@ config SOC_DMA2D_GROUPS
config SOC_DMA2D_TX_CHANNELS_PER_GROUP
int
default 3
default 4
config SOC_DMA2D_RX_CHANNELS_PER_GROUP
int
default 2
default 3
config SOC_ETM_GROUPS
int

4
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -225,8 +225,8 @@
/*-------------------------- 2D-DMA CAPS -------------------------------------*/
#define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups
#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group
#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group
#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (4) // Number of 2D-DMA TX (OUT) channels in each group (4th channel only exists on P4 ver. >= 3.0)
#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA RX (IN) channels in each group (3rd channel only exists on P4 ver. >= 3.0)
// #define SOC_DMA2D_SUPPORT_ETM (1) // Support ETM submodule
/*-------------------------- ETM CAPS --------------------------------------*/

45
components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1763,42 +1763,21 @@ typedef struct {
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf;
volatile dma2d_in_color_convert_chn_reg_t in_color_convert;
volatile dma2d_in_scramble_chn_reg_t in_scramble;
volatile dma2d_color_param_group_chn_reg_t in_color_param_group;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_570[36];
} dma2d_in_ch0_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
volatile dma2d_in_int_st_chn_reg_t in_int_st;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
volatile dma2d_infifo_status_chn_reg_t infifo_status;
volatile dma2d_in_pop_chn_reg_t in_pop;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
volatile dma2d_in_state_chn_reg_t in_state;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile dma2d_in_dscr_chn_reg_t in_dscr;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_64c[45];
} dma2d_in_ch1_reg_t;
union {
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in1_etm_conf; /* specific for channel1 */
};
volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */
volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */
volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; /* On ver. less than 3.0, channel 1 in_etm_conf register is at the in_ro_pd_conf addr. Here is to only be compatible with new ECOs. Workaround should be done in LL layer. */
uint32_t reserved_in[36];
} dma2d_in_chn_reg_t;
typedef struct dma2d_dev_t {
volatile dma2d_out_chn_reg_t out_channel[3];
uint32_t reserved_300[128];
volatile dma2d_in_ch0_reg_t in_channel0;
volatile dma2d_in_ch1_reg_t in_channel1;
volatile dma2d_in_chn_reg_t in_channel[2];
uint32_t reserved_700[192];
volatile dma2d_axi_err_reg_t axi_err;
volatile dma2d_rst_conf_reg_t rst_conf;

7537
components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h
View File

File diff suppressed because it is too large Load Diff

2085
components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h
View File

File diff suppressed because it is too large Load Diff

2128
components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h
View File

File diff suppressed because it is too large Load Diff

196
components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h
View File

@@ -10,11 +10,8 @@
extern "C" {
#endif
//TODO: IDF-13427
/** Group: out */
/** Type of out_conf0_chn register
* Configures the tx direction of channel 0
* Configures the tx direction of channel n
*/
typedef union {
struct {
@@ -48,7 +45,7 @@ typedef union {
*/
uint32_t out_loop_test_chn:1;
/** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
* Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64
* Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64
* bytes 4: 128 bytes
*/
uint32_t out_mem_burst_length_chn:3;
@@ -92,7 +89,7 @@ typedef union {
} dma2d_out_conf0_chn_reg_t;
/** Type of out_int_raw_chn register
* Raw interrupt status of TX channel 0
* Raw interrupt status of TX channel n
*/
typedef union {
struct {
@@ -160,7 +157,7 @@ typedef union {
} dma2d_out_int_raw_chn_reg_t;
/** Type of out_int_ena_chn register
* Interrupt enable bits of TX channel 0
* Interrupt enable bits of TX channel n
*/
typedef union {
struct {
@@ -222,7 +219,7 @@ typedef union {
} dma2d_out_int_ena_chn_reg_t;
/** Type of out_int_st_chn register
* Masked interrupt status of TX channel 0
* Masked interrupt status of TX channel n
*/
typedef union {
struct {
@@ -284,7 +281,7 @@ typedef union {
} dma2d_out_int_st_chn_reg_t;
/** Type of out_int_clr_chn register
* Interrupt clear bits of TX channel 0
* Interrupt clear bits of TX channel n
*/
typedef union {
struct {
@@ -346,20 +343,20 @@ typedef union {
} dma2d_out_int_clr_chn_reg_t;
/** Type of outfifo_status_chn register
* Represents the status of the tx fifo of channel 0
* Represents the status of the tx fifo of channel n
*/
typedef union {
struct {
/** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Tx FIFO full signal for Tx channel n.
*/
uint32_t outfifo_full_l2_chn:1;
/** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Tx FIFO empty signal for Tx channel n.
*/
uint32_t outfifo_empty_l2_chn:1;
/** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Tx FIFO for Tx channel n.
*/
uint32_t outfifo_cnt_l2_chn:4;
uint32_t reserved_6:1;
@@ -396,27 +393,27 @@ typedef union {
*/
uint32_t out_remain_under_8b_chn:1;
/** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Tx FIFO full signal for Tx channel n.
*/
uint32_t outfifo_full_l1_chn:1;
/** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Tx FIFO empty signal for Tx channel n.
*/
uint32_t outfifo_empty_l1_chn:1;
/** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Tx FIFO for Tx channel n.
*/
uint32_t outfifo_cnt_l1_chn:5;
/** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Tx FIFO full signal for Tx channel n.
*/
uint32_t outfifo_full_l3_chn:1;
/** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Tx FIFO empty signal for Tx channel n.
*/
uint32_t outfifo_empty_l3_chn:1;
/** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Tx FIFO for Tx channel n.
*/
uint32_t outfifo_cnt_l3_chn:5;
uint32_t reserved_29:3;
@@ -425,7 +422,7 @@ typedef union {
} dma2d_outfifo_status_chn_reg_t;
/** Type of out_push_chn register
* Configures the tx fifo of channel 0
* Configures the tx fifo of channel n
*/
typedef union {
struct {
@@ -443,7 +440,7 @@ typedef union {
} dma2d_out_push_chn_reg_t;
/** Type of out_link_conf_chn register
* Configures the tx descriptor operations of channel 0
* Configures the tx descriptor operations of channel n
*/
typedef union {
struct {
@@ -471,7 +468,7 @@ typedef union {
} dma2d_out_link_conf_chn_reg_t;
/** Type of out_link_addr_chn register
* Configures the tx descriptor address of channel 0
* Configures the tx descriptor address of channel n
*/
typedef union {
struct {
@@ -484,7 +481,7 @@ typedef union {
} dma2d_out_link_addr_chn_reg_t;
/** Type of out_state_chn register
* Represents the working status of the tx descriptor of channel 0
* Represents the working status of the tx descriptor of channel n
*/
typedef union {
struct {
@@ -510,7 +507,7 @@ typedef union {
} dma2d_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -524,7 +521,7 @@ typedef union {
} dma2d_out_eof_des_addr_chn_reg_t;
/** Type of out_dscr_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -537,7 +534,7 @@ typedef union {
} dma2d_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -550,7 +547,7 @@ typedef union {
} dma2d_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -563,7 +560,7 @@ typedef union {
} dma2d_out_dscr_bf1_chn_reg_t;
/** Type of out_peri_sel_chn register
* Configures the tx peripheral of channel 0
* Configures the tx peripheral of channel n
*/
typedef union {
struct {
@@ -578,7 +575,7 @@ typedef union {
} dma2d_out_peri_sel_chn_reg_t;
/** Type of out_arb_chn register
* Configures the tx arbiter of channel 0
* Configures the tx arbiter of channel n
*/
typedef union {
struct {
@@ -586,17 +583,17 @@ typedef union {
* Set the max number of token count of arbiter
*/
uint32_t out_arb_token_num_chn:4;
/** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1;
/** out_arb_priority_chn : R/W; bitpos: [7:4]; default: 1;
* Set the priority of channel
*/
uint32_t out_arb_priority_chn:2;
uint32_t reserved_6:26;
uint32_t out_arb_priority_chn:4;
uint32_t reserved_8:24;
};
uint32_t val;
} dma2d_out_arb_chn_reg_t;
/** Type of out_ro_status_chn register
* Represents the status of the tx reorder module of channel 0
* Represents the status of the tx reorder module of channel n
*/
typedef union {
struct {
@@ -628,7 +625,7 @@ typedef union {
} dma2d_out_ro_status_chn_reg_t;
/** Type of out_ro_pd_conf_chn register
* Configures the tx reorder memory of channel 0
* Configures the tx reorder memory of channel n
*/
typedef union {
struct {
@@ -652,7 +649,7 @@ typedef union {
} dma2d_out_ro_pd_conf_chn_reg_t;
/** Type of out_color_convert_chn register
* Configures the tx color convert of channel 0
* Configures the tx color convert of channel n
*/
typedef union {
struct {
@@ -678,7 +675,7 @@ typedef union {
} dma2d_out_color_convert_chn_reg_t;
/** Type of out_scramble_chn register
* Configures the tx scramble of channel 0
* Configures the tx scramble of channel n
*/
typedef union {
struct {
@@ -693,7 +690,7 @@ typedef union {
} dma2d_out_scramble_chn_reg_t;
/** Type of out_etm_conf_chn register
* Configures the tx etm of channel 0
* Configures the tx etm of channel n
*/
typedef union {
struct {
@@ -732,10 +729,8 @@ typedef union {
uint32_t val;
} dma2d_out_dscr_port_blk_chn_reg_t;
/** Group: in */
/** Type of in_conf0_chn register
* Configures the rx direction of channel 0
* Configures the rx direction of channel n
*/
typedef union {
struct {
@@ -808,7 +803,7 @@ typedef union {
} dma2d_in_conf0_chn_reg_t;
/** Type of in_int_raw_chn register
* Raw interrupt status of RX channel 0
* Raw interrupt status of RX channel n
*/
typedef union {
struct {
@@ -880,7 +875,7 @@ typedef union {
} dma2d_in_int_raw_chn_reg_t;
/** Type of in_int_ena_chn register
* Interrupt enable bits of RX channel 0
* Interrupt enable bits of RX channel n
*/
typedef union {
struct {
@@ -946,7 +941,7 @@ typedef union {
} dma2d_in_int_ena_chn_reg_t;
/** Type of in_int_st_chn register
* Masked interrupt status of RX channel 0
* Masked interrupt status of RX channel n
*/
typedef union {
struct {
@@ -1012,7 +1007,7 @@ typedef union {
} dma2d_in_int_st_chn_reg_t;
/** Type of in_int_clr_chn register
* Interrupt clear bits of RX channel 0
* Interrupt clear bits of RX channel n
*/
typedef union {
struct {
@@ -1078,20 +1073,20 @@ typedef union {
} dma2d_in_int_clr_chn_reg_t;
/** Type of infifo_status_chn register
* Represents the status of the rx fifo of channel 0
* Represents the status of the rx fifo of channel n
*/
typedef union {
struct {
/** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
* Rx FIFO full signal for Rx channel.
* Rx FIFO full signal for Rx channel n.
*/
uint32_t infifo_full_l2_chn:1;
/** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
* Rx FIFO empty signal for Rx channel.
* Rx FIFO empty signal for Rx channel n.
*/
uint32_t infifo_empty_l2_chn:1;
/** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
* The register stores the byte number of the data in Rx FIFO for Rx channel.
* The register stores the byte number of the data in Rx FIFO for Rx channel n.
*/
uint32_t infifo_cnt_l2_chn:4;
uint32_t reserved_6:1;
@@ -1128,27 +1123,27 @@ typedef union {
*/
uint32_t in_remain_under_8b_chn:1;
/** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Rx FIFO full signal for Tx channel n.
*/
uint32_t infifo_full_l1_chn:1;
/** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Rx FIFO empty signal for Tx channel n.
*/
uint32_t infifo_empty_l1_chn:1;
/** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Rx FIFO for Rx channel n.
*/
uint32_t infifo_cnt_l1_chn:5;
/** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Rx FIFO full signal for Rx channel n.
*/
uint32_t infifo_full_l3_chn:1;
/** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Rx FIFO empty signal for Rx channel n.
*/
uint32_t infifo_empty_l3_chn:1;
/** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Rx FIFO for Rx channel n.
*/
uint32_t infifo_cnt_l3_chn:5;
uint32_t reserved_29:3;
@@ -1157,7 +1152,7 @@ typedef union {
} dma2d_infifo_status_chn_reg_t;
/** Type of in_pop_chn register
* Configures the rx fifo of channel 0
* Configures the rx fifo of channel n
*/
typedef union {
struct {
@@ -1175,7 +1170,7 @@ typedef union {
} dma2d_in_pop_chn_reg_t;
/** Type of in_link_conf_chn register
* Configures the rx descriptor operations of channel 0
* Configures the rx descriptor operations of channel n
*/
typedef union {
struct {
@@ -1208,7 +1203,7 @@ typedef union {
} dma2d_in_link_conf_chn_reg_t;
/** Type of in_link_addr_chn register
* Configures the rx descriptor address of channel 0
* Configures the rx descriptor address of channel n
*/
typedef union {
struct {
@@ -1221,7 +1216,7 @@ typedef union {
} dma2d_in_link_addr_chn_reg_t;
/** Type of in_state_chn register
* Represents the working status of the rx descriptor of channel 0
* Represents the working status of the rx descriptor of channel n
*/
typedef union {
struct {
@@ -1247,7 +1242,7 @@ typedef union {
} dma2d_in_state_chn_reg_t;
/** Type of in_suc_eof_des_addr_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1261,7 +1256,7 @@ typedef union {
} dma2d_in_suc_eof_des_addr_chn_reg_t;
/** Type of in_err_eof_des_addr_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1275,7 +1270,7 @@ typedef union {
} dma2d_in_err_eof_des_addr_chn_reg_t;
/** Type of in_dscr_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1288,7 +1283,7 @@ typedef union {
} dma2d_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1301,7 +1296,7 @@ typedef union {
} dma2d_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1314,7 +1309,7 @@ typedef union {
} dma2d_in_dscr_bf1_chn_reg_t;
/** Type of in_peri_sel_chn register
* Configures the rx peripheral of channel 0
* Configures the rx peripheral of channel n
*/
typedef union {
struct {
@@ -1329,7 +1324,7 @@ typedef union {
} dma2d_in_peri_sel_chn_reg_t;
/** Type of in_arb_chn register
* Configures the rx arbiter of channel 0
* Configures the rx arbiter of channel n
*/
typedef union {
struct {
@@ -1337,17 +1332,17 @@ typedef union {
* Set the max number of token count of arbiter
*/
uint32_t in_arb_token_num_chn:4;
/** in_arb_priority_chn : R/W; bitpos: [4]; default: 1;
/** in_arb_priority_chn : R/W; bitpos: [7:4]; default: 1;
* Set the priority of channel
*/
uint32_t in_arb_priority_chn:1;
uint32_t reserved_5:27;
uint32_t in_arb_priority_chn:4;
uint32_t reserved_8:24;
};
uint32_t val;
} dma2d_in_arb_chn_reg_t;
/** Type of in_ro_status_chn register
* Represents the status of the rx reorder module of channel 0
* Represents the status of the rx reorder module of channel n
*/
typedef union {
struct {
@@ -1379,7 +1374,7 @@ typedef union {
} dma2d_in_ro_status_chn_reg_t;
/** Type of in_ro_pd_conf_chn register
* Configures the rx reorder memory of channel 0
* Configures the rx reorder memory of channel n
*/
typedef union {
struct {
@@ -1403,13 +1398,13 @@ typedef union {
} dma2d_in_ro_pd_conf_chn_reg_t;
/** Type of in_color_convert_chn register
* Configures the tx color convert of channel 0
* Configures the Rx color convert of channel n
*/
typedef union {
struct {
/** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
* Set final color convert process and output type 0: RGB888 to RGB565 1:
* output directly
* output directly 2: YUV444 to YUV422 3: YUV444 to YUV420
*/
uint32_t in_color_output_sel_chn:2;
/** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
@@ -1428,7 +1423,7 @@ typedef union {
} dma2d_in_color_convert_chn_reg_t;
/** Type of in_scramble_chn register
* Configures the rx scramble of channel 0
* Configures the rx scramble of channel n
*/
typedef union {
struct {
@@ -1448,7 +1443,7 @@ typedef union {
} dma2d_in_scramble_chn_reg_t;
/** Type of in_etm_conf_chn register
* Configures the rx etm of channel 0
* Configures the rx etm of channel n
*/
typedef union {
struct {
@@ -1469,8 +1464,6 @@ typedef union {
uint32_t val;
} dma2d_in_etm_conf_chn_reg_t;
/** Group: Status Registers */
/** Type of axi_err register
* Represents the status of th axi bus
*/
@@ -1514,7 +1507,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36716816;
/** date : R/W; bitpos: [31:0]; default: 37822864;
* register version.
*/
uint32_t date:32;
@@ -1522,8 +1515,6 @@ typedef union {
uint32_t val;
} dma2d_date_reg_t;
/** Group: Configuration Registers */
/** Type of rst_conf register
* Configures the reset of axi
*/
@@ -1681,7 +1672,6 @@ typedef union {
uint32_t val;
} dma2d_rdn_eco_low_reg_t;
/** Type of in/out_color_param_h/m/l_chn register
* Configures the rx/tx color convert parameter of channel n
*/
@@ -1713,12 +1703,14 @@ typedef union {
uint32_t val[2];
} dma2d_color_param_reg_t;
typedef struct {
volatile dma2d_color_param_reg_t param_h;
volatile dma2d_color_param_reg_t param_m;
volatile dma2d_color_param_reg_t param_l;
} dma2d_color_param_group_chn_reg_t;
typedef struct {
volatile dma2d_out_conf0_chn_reg_t out_conf0;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw;
@@ -1746,32 +1738,6 @@ typedef struct {
uint32_t reserved_out[36];
} dma2d_out_chn_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
volatile dma2d_in_int_st_chn_reg_t in_int_st;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
volatile dma2d_infifo_status_chn_reg_t infifo_status;
volatile dma2d_in_pop_chn_reg_t in_pop;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
volatile dma2d_in_state_chn_reg_t in_state;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile dma2d_in_dscr_chn_reg_t in_dscr;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf;
volatile dma2d_in_color_convert_chn_reg_t in_color_convert;
volatile dma2d_in_scramble_chn_reg_t in_scramble;
volatile dma2d_color_param_group_chn_reg_t in_color_param_group;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_570[36];
} dma2d_in_ch0_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
@@ -1792,16 +1758,20 @@ typedef struct {
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */
volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */
volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */
volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_64c[45];
} dma2d_in_ch1_reg_t;
uint32_t reserved_in[36];
} dma2d_in_chn_reg_t;
typedef struct dma2d_dev_t {
volatile dma2d_out_chn_reg_t out_channel[3];
uint32_t reserved_300[128];
volatile dma2d_in_ch0_reg_t in_channel0;
volatile dma2d_in_ch1_reg_t in_channel1;
uint32_t reserved_700[192];
volatile dma2d_out_chn_reg_t out_channel[4];
uint32_t reserved_400[64];
volatile dma2d_in_chn_reg_t in_channel[3];
uint32_t reserved_800[128];
volatile dma2d_axi_err_reg_t axi_err;
volatile dma2d_rst_conf_reg_t rst_conf;
volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;